tarmac_base.hh revision 13915
16145SN/A/* 26145SN/A * Copyright (c) 2011,2017-2018 ARM Limited 36145SN/A * All rights reserved 46145SN/A * 56145SN/A * The license below extends only to copyright in the software and shall 66145SN/A * not be construed as granting a license to any other intellectual 76145SN/A * property including but not limited to intellectual property relating 86145SN/A * to a hardware implementation of the functionality of the software 96145SN/A * licensed hereunder. You may use the software subject to the license 106145SN/A * terms below provided that you ensure that this notice is replicated 116145SN/A * unmodified and in its entirety in all distributions of the software, 126145SN/A * modified or unmodified, in source code or in binary form. 136145SN/A * 146145SN/A * Redistribution and use in source and binary forms, with or without 156145SN/A * modification, are permitted provided that the following conditions are 166145SN/A * met: redistributions of source code must retain the above copyright 176145SN/A * notice, this list of conditions and the following disclaimer; 186145SN/A * redistributions in binary form must reproduce the above copyright 196145SN/A * notice, this list of conditions and the following disclaimer in the 206145SN/A * documentation and/or other materials provided with the distribution; 216145SN/A * neither the name of the copyright holders nor the names of its 226145SN/A * contributors may be used to endorse or promote products derived from 236145SN/A * this software without specific prior written permission. 246145SN/A * 256145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297832SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307832SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 319356Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 328232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336154SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347054SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 358257SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367054SN/A * 378255SBrad.Beckmann@amd.com * Authors: Giacomo Gabrielli 387054SN/A * Giacomo Travaglini 396145SN/A */ 407055SN/A 417055SN/A/** 427054SN/A * @file: This file contains the data structure used to rappresent 438257SBrad.Beckmann@amd.com * Tarmac entities/informations. These data structures will 446145SN/A * be used and extended by either the Tarmac Parser and 456145SN/A * the Tarmac Tracer. 466145SN/A * Instruction execution is matched by Records, so that for 476145SN/A * every instruction executed there is a corresponding record. 486145SN/A * A trace is made of Records (Generated or Parsed) and a record 496145SN/A * is made of Entries. 506145SN/A */ 516145SN/A 527054SN/A#ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__ 537054SN/A#define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__ 547054SN/A 557054SN/A#include "arch/arm/registers.hh" 567054SN/A#include "base/trace.hh" 577054SN/A#include "base/types.hh" 587054SN/A#include "cpu/static_inst.hh" 597054SN/A#include "sim/insttracer.hh" 606145SN/A 616876SN/Aclass ThreadContext; 626876SN/A 636145SN/Anamespace Trace { 646876SN/A 658257SBrad.Beckmann@amd.comclass TarmacBaseRecord : public InstRecord 668257SBrad.Beckmann@amd.com{ 676881SN/A public: 687454SN/A /** TARMAC trace record type. */ 697454SN/A enum TarmacRecordType { 706145SN/A TARMAC_INST, 716881SN/A TARMAC_REG, 726881SN/A TARMAC_MEM, 736879SN/A TARMAC_UNSUPPORTED, 746881SN/A }; 756285SN/A 767054SN/A /** ARM instruction set state. */ 777054SN/A enum ISetState { ISET_ARM, ISET_THUMB, ISET_A64, 786879SN/A ISET_UNSUPPORTED }; 799109SBrad.Beckmann@amd.com 806879SN/A /** ARM register type. */ 816879SN/A enum RegType { REG_R, REG_X, REG_S, REG_D, REG_Q, REG_MISC }; 828257SBrad.Beckmann@amd.com 838257SBrad.Beckmann@amd.com /** TARMAC instruction trace record. */ 848257SBrad.Beckmann@amd.com struct InstEntry 858257SBrad.Beckmann@amd.com { 868257SBrad.Beckmann@amd.com InstEntry() = default; 877054SN/A InstEntry(ThreadContext* thread, 888257SBrad.Beckmann@amd.com ArmISA::PCState pc, 898257SBrad.Beckmann@amd.com const StaticInstPtr staticInst, 908257SBrad.Beckmann@amd.com bool predicate); 916881SN/A 928257SBrad.Beckmann@amd.com bool taken; 938257SBrad.Beckmann@amd.com Addr addr; 948257SBrad.Beckmann@amd.com ArmISA::MachInst opcode; 956881SN/A std::string disassemble; 968257SBrad.Beckmann@amd.com ISetState isetstate; 977054SN/A ArmISA::OperatingMode mode; 988257SBrad.Beckmann@amd.com }; 996145SN/A 1008257SBrad.Beckmann@amd.com /** TARMAC register trace record. */ 1018257SBrad.Beckmann@amd.com struct RegEntry 1028257SBrad.Beckmann@amd.com { 1038257SBrad.Beckmann@amd.com RegEntry() = default; 1048257SBrad.Beckmann@amd.com RegEntry(ArmISA::PCState pc); 1057054SN/A 1066145SN/A RegType type; 1078257SBrad.Beckmann@amd.com RegIndex index; 1087054SN/A ISetState isetstate; 1098257SBrad.Beckmann@amd.com uint64_t valueHi; 1108257SBrad.Beckmann@amd.com uint64_t valueLo; 1118257SBrad.Beckmann@amd.com }; 1126881SN/A 1138257SBrad.Beckmann@amd.com /** TARMAC memory access trace record (stores only). */ 1148257SBrad.Beckmann@amd.com struct MemEntry 1158257SBrad.Beckmann@amd.com { 1168257SBrad.Beckmann@amd.com MemEntry() = default; 1178257SBrad.Beckmann@amd.com MemEntry(uint8_t _size, Addr _addr, uint64_t _data); 1188257SBrad.Beckmann@amd.com 1198257SBrad.Beckmann@amd.com uint8_t size; 1208257SBrad.Beckmann@amd.com Addr addr; 1218257SBrad.Beckmann@amd.com uint64_t data; 1228257SBrad.Beckmann@amd.com }; 1238257SBrad.Beckmann@amd.com 1247054SN/A public: 1256145SN/A TarmacBaseRecord(Tick _when, ThreadContext *_thread, 1266145SN/A const StaticInstPtr _staticInst, ArmISA::PCState _pc, 1278257SBrad.Beckmann@amd.com const StaticInstPtr _macroStaticInst = NULL); 1288257SBrad.Beckmann@amd.com 1298257SBrad.Beckmann@amd.com virtual void dump() = 0; 1308257SBrad.Beckmann@amd.com 1318257SBrad.Beckmann@amd.com /** 1326285SN/A * Returns the Instruction Set State according to the current 1337054SN/A * PCState. 1347054SN/A * 1356881SN/A * @param pc program counter (PCState) variable 1368257SBrad.Beckmann@amd.com * @return Instruction Set State for the given PCState 1378257SBrad.Beckmann@amd.com */ 1388257SBrad.Beckmann@amd.com static ISetState pcToISetState(ArmISA::PCState pc); 1398257SBrad.Beckmann@amd.com}; 1408257SBrad.Beckmann@amd.com 1416881SN/A 1426881SN/A} // namespace Trace 1436881SN/A 1447054SN/A#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__ 1457054SN/A