tarmac_base.cc revision 13915
112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 2017-2018 ARM Limited 312641Sgiacomo.travaglini@arm.com * All rights reserved 412641Sgiacomo.travaglini@arm.com * 512641Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612641Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712641Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812641Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912641Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012641Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112641Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212641Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312641Sgiacomo.travaglini@arm.com * 1412641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412641Sgiacomo.travaglini@arm.com * 2512641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612641Sgiacomo.travaglini@arm.com * 3712641Sgiacomo.travaglini@arm.com * Authors: Giacomo Travaglini 3812641Sgiacomo.travaglini@arm.com */ 3912641Sgiacomo.travaglini@arm.com 4012641Sgiacomo.travaglini@arm.com#include "arch/arm/tracers/tarmac_base.hh" 4112641Sgiacomo.travaglini@arm.com 4212641Sgiacomo.travaglini@arm.com#include <algorithm> 4312641Sgiacomo.travaglini@arm.com#include <string> 4412641Sgiacomo.travaglini@arm.com 4512641Sgiacomo.travaglini@arm.com#include "config/the_isa.hh" 4612641Sgiacomo.travaglini@arm.com#include "cpu/reg_class.hh" 4712641Sgiacomo.travaglini@arm.com#include "cpu/static_inst.hh" 4812641Sgiacomo.travaglini@arm.com#include "cpu/thread_context.hh" 4912641Sgiacomo.travaglini@arm.com 5013915Sgabeblack@google.comusing namespace ArmISA; 5112641Sgiacomo.travaglini@arm.com 5212641Sgiacomo.travaglini@arm.comnamespace Trace { 5312641Sgiacomo.travaglini@arm.com 5412641Sgiacomo.travaglini@arm.comTarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread, 5512641Sgiacomo.travaglini@arm.com const StaticInstPtr _staticInst, 5612641Sgiacomo.travaglini@arm.com PCState _pc, 5712641Sgiacomo.travaglini@arm.com const StaticInstPtr _macroStaticInst) 5812641Sgiacomo.travaglini@arm.com : InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst) 5912641Sgiacomo.travaglini@arm.com{ 6012641Sgiacomo.travaglini@arm.com} 6112641Sgiacomo.travaglini@arm.com 6212641Sgiacomo.travaglini@arm.comTarmacBaseRecord::InstEntry::InstEntry( 6312641Sgiacomo.travaglini@arm.com ThreadContext* thread, 6412641Sgiacomo.travaglini@arm.com PCState pc, 6512641Sgiacomo.travaglini@arm.com const StaticInstPtr staticInst, 6612641Sgiacomo.travaglini@arm.com bool predicate) 6712641Sgiacomo.travaglini@arm.com : taken(predicate) , 6812641Sgiacomo.travaglini@arm.com addr(pc.instAddr()) , 6912641Sgiacomo.travaglini@arm.com opcode(staticInst->machInst & 0xffffffff), 7012641Sgiacomo.travaglini@arm.com disassemble(staticInst->disassemble(addr)), 7112641Sgiacomo.travaglini@arm.com isetstate(pcToISetState(pc)), 7212641Sgiacomo.travaglini@arm.com mode(MODE_USER) 7312641Sgiacomo.travaglini@arm.com{ 7412641Sgiacomo.travaglini@arm.com 7512641Sgiacomo.travaglini@arm.com // Operating mode gained by reading the architectural register (CPSR) 7612641Sgiacomo.travaglini@arm.com const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR); 7712641Sgiacomo.travaglini@arm.com mode = (OperatingMode) (uint8_t)cpsr.mode; 7812641Sgiacomo.travaglini@arm.com 7912641Sgiacomo.travaglini@arm.com // In Tarmac, instruction names are printed in capital 8012641Sgiacomo.travaglini@arm.com // letters. 8112641Sgiacomo.travaglini@arm.com std::for_each(disassemble.begin(), disassemble.end(), 8212641Sgiacomo.travaglini@arm.com [](char& c) { c = toupper(c); }); 8312641Sgiacomo.travaglini@arm.com} 8412641Sgiacomo.travaglini@arm.com 8512641Sgiacomo.travaglini@arm.comTarmacBaseRecord::RegEntry::RegEntry(PCState pc) 8612641Sgiacomo.travaglini@arm.com : isetstate(pcToISetState(pc)) 8712641Sgiacomo.travaglini@arm.com{ 8812641Sgiacomo.travaglini@arm.com} 8912641Sgiacomo.travaglini@arm.com 9012641Sgiacomo.travaglini@arm.comTarmacBaseRecord::MemEntry::MemEntry ( 9112641Sgiacomo.travaglini@arm.com uint8_t _size, 9212641Sgiacomo.travaglini@arm.com Addr _addr, 9312641Sgiacomo.travaglini@arm.com uint64_t _data) 9412641Sgiacomo.travaglini@arm.com : size(_size), addr(_addr), data(_data) 9512641Sgiacomo.travaglini@arm.com{ 9612641Sgiacomo.travaglini@arm.com} 9712641Sgiacomo.travaglini@arm.com 9812641Sgiacomo.travaglini@arm.comTarmacBaseRecord::ISetState 9912641Sgiacomo.travaglini@arm.comTarmacBaseRecord::pcToISetState(PCState pc) 10012641Sgiacomo.travaglini@arm.com{ 10112641Sgiacomo.travaglini@arm.com TarmacBaseRecord::ISetState isetstate; 10212641Sgiacomo.travaglini@arm.com 10312641Sgiacomo.travaglini@arm.com if (pc.aarch64()) 10412641Sgiacomo.travaglini@arm.com isetstate = TarmacBaseRecord::ISET_A64; 10512641Sgiacomo.travaglini@arm.com else if (!pc.thumb() && !pc.jazelle()) 10612641Sgiacomo.travaglini@arm.com isetstate = TarmacBaseRecord::ISET_ARM; 10712641Sgiacomo.travaglini@arm.com else if (pc.thumb() && !pc.jazelle()) 10812641Sgiacomo.travaglini@arm.com isetstate = TarmacBaseRecord::ISET_THUMB; 10912641Sgiacomo.travaglini@arm.com else 11012641Sgiacomo.travaglini@arm.com // No Jazelle state in TARMAC 11112641Sgiacomo.travaglini@arm.com isetstate = TarmacBaseRecord::ISET_UNSUPPORTED; 11212641Sgiacomo.travaglini@arm.com 11312641Sgiacomo.travaglini@arm.com return isetstate; 11412641Sgiacomo.travaglini@arm.com} 11512641Sgiacomo.travaglini@arm.com 11612641Sgiacomo.travaglini@arm.com} // namespace Trace 117