tarmac_base.cc revision 13915 
1/*
2 * Copyright (c) 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Travaglini
38 */
39
40#include "arch/arm/tracers/tarmac_base.hh"
41
42#include <algorithm>
43#include <string>
44
45#include "config/the_isa.hh"
46#include "cpu/reg_class.hh"
47#include "cpu/static_inst.hh"
48#include "cpu/thread_context.hh"
49
50using namespace ArmISA;
51
52namespace Trace {
53
54TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
55                                   const StaticInstPtr _staticInst,
56                                   PCState _pc,
57                                   const StaticInstPtr _macroStaticInst)
58    : InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
59{
60}
61
62TarmacBaseRecord::InstEntry::InstEntry(
63    ThreadContext* thread,
64    PCState pc,
65    const StaticInstPtr staticInst,
66    bool predicate)
67        : taken(predicate) ,
68          addr(pc.instAddr()) ,
69          opcode(staticInst->machInst & 0xffffffff),
70          disassemble(staticInst->disassemble(addr)),
71          isetstate(pcToISetState(pc)),
72          mode(MODE_USER)
73{
74
75    // Operating mode gained by reading the architectural register (CPSR)
76    const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
77    mode = (OperatingMode) (uint8_t)cpsr.mode;
78
79    // In Tarmac, instruction names are printed in capital
80    // letters.
81    std::for_each(disassemble.begin(), disassemble.end(),
82                  [](char& c) { c = toupper(c); });
83}
84
85TarmacBaseRecord::RegEntry::RegEntry(PCState pc)
86  : isetstate(pcToISetState(pc))
87{
88}
89
90TarmacBaseRecord::MemEntry::MemEntry (
91    uint8_t _size,
92    Addr _addr,
93    uint64_t _data)
94      : size(_size), addr(_addr), data(_data)
95{
96}
97
98TarmacBaseRecord::ISetState
99TarmacBaseRecord::pcToISetState(PCState pc)
100{
101    TarmacBaseRecord::ISetState isetstate;
102
103    if (pc.aarch64())
104        isetstate = TarmacBaseRecord::ISET_A64;
105    else if (!pc.thumb() && !pc.jazelle())
106        isetstate = TarmacBaseRecord::ISET_ARM;
107    else if (pc.thumb() && !pc.jazelle())
108        isetstate = TarmacBaseRecord::ISET_THUMB;
109    else
110        // No Jazelle state in TARMAC
111        isetstate = TarmacBaseRecord::ISET_UNSUPPORTED;
112
113    return isetstate;
114}
115
116} // namespace Trace
117