tlbi_op.cc revision 13882
112605Sgiacomo.travaglini@arm.com/* 213882Sgiacomo.travaglini@arm.com * Copyright (c) 2018-2019 ARM Limited 312605Sgiacomo.travaglini@arm.com * All rights reserved 412605Sgiacomo.travaglini@arm.com * 512605Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612605Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712605Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812605Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912605Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012605Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112605Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212605Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312605Sgiacomo.travaglini@arm.com * 1412605Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512605Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612605Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712605Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812605Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912605Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012605Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112605Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212605Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312605Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412605Sgiacomo.travaglini@arm.com * 2512605Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612605Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712605Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812605Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912605Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012605Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112605Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212605Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312605Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412605Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512605Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612605Sgiacomo.travaglini@arm.com * 3712605Sgiacomo.travaglini@arm.com * Authors: Giacomo Travaglini 3812605Sgiacomo.travaglini@arm.com */ 3912605Sgiacomo.travaglini@arm.com 4012605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh" 4112605Sgiacomo.travaglini@arm.com 4212605Sgiacomo.travaglini@arm.com#include "arch/arm/tlb.hh" 4312605Sgiacomo.travaglini@arm.com#include "cpu/checker/cpu.hh" 4412605Sgiacomo.travaglini@arm.com 4512605Sgiacomo.travaglini@arm.comnamespace ArmISA { 4612605Sgiacomo.travaglini@arm.com 4712605Sgiacomo.travaglini@arm.comvoid 4812605Sgiacomo.travaglini@arm.comTLBIALL::operator()(ThreadContext* tc) 4912605Sgiacomo.travaglini@arm.com{ 5012605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL); 5112605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL); 5212605Sgiacomo.travaglini@arm.com 5312605Sgiacomo.travaglini@arm.com // If CheckerCPU is connected, need to notify it of a flush 5412605Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 5512605Sgiacomo.travaglini@arm.com if (checker) { 5612605Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushAllSecurity(secureLookup, 5712605Sgiacomo.travaglini@arm.com targetEL); 5812605Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushAllSecurity(secureLookup, 5912605Sgiacomo.travaglini@arm.com targetEL); 6012605Sgiacomo.travaglini@arm.com } 6112605Sgiacomo.travaglini@arm.com} 6212605Sgiacomo.travaglini@arm.com 6312605Sgiacomo.travaglini@arm.comvoid 6412605Sgiacomo.travaglini@arm.comITLBIALL::operator()(ThreadContext* tc) 6512605Sgiacomo.travaglini@arm.com{ 6612605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL); 6712605Sgiacomo.travaglini@arm.com} 6812605Sgiacomo.travaglini@arm.com 6912605Sgiacomo.travaglini@arm.comvoid 7012605Sgiacomo.travaglini@arm.comDTLBIALL::operator()(ThreadContext* tc) 7112605Sgiacomo.travaglini@arm.com{ 7212605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL); 7312605Sgiacomo.travaglini@arm.com} 7412605Sgiacomo.travaglini@arm.com 7512605Sgiacomo.travaglini@arm.comvoid 7612605Sgiacomo.travaglini@arm.comTLBIASID::operator()(ThreadContext* tc) 7712605Sgiacomo.travaglini@arm.com{ 7812605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 7912605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 8012605Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 8112605Sgiacomo.travaglini@arm.com if (checker) { 8212605Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL); 8312605Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL); 8412605Sgiacomo.travaglini@arm.com } 8512605Sgiacomo.travaglini@arm.com} 8612605Sgiacomo.travaglini@arm.com 8712605Sgiacomo.travaglini@arm.comvoid 8812605Sgiacomo.travaglini@arm.comITLBIASID::operator()(ThreadContext* tc) 8912605Sgiacomo.travaglini@arm.com{ 9012605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 9112605Sgiacomo.travaglini@arm.com} 9212605Sgiacomo.travaglini@arm.com 9312605Sgiacomo.travaglini@arm.comvoid 9412605Sgiacomo.travaglini@arm.comDTLBIASID::operator()(ThreadContext* tc) 9512605Sgiacomo.travaglini@arm.com{ 9612605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 9712605Sgiacomo.travaglini@arm.com} 9812605Sgiacomo.travaglini@arm.com 9912605Sgiacomo.travaglini@arm.comvoid 10012605Sgiacomo.travaglini@arm.comTLBIALLN::operator()(ThreadContext* tc) 10112605Sgiacomo.travaglini@arm.com{ 10213882Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushAllNs(targetEL); 10313882Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushAllNs(targetEL); 10412605Sgiacomo.travaglini@arm.com 10512605Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 10612605Sgiacomo.travaglini@arm.com if (checker) { 10713882Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushAllNs(targetEL); 10813882Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushAllNs(targetEL); 10912605Sgiacomo.travaglini@arm.com } 11012605Sgiacomo.travaglini@arm.com} 11112605Sgiacomo.travaglini@arm.com 11212605Sgiacomo.travaglini@arm.comvoid 11312605Sgiacomo.travaglini@arm.comTLBIMVAA::operator()(ThreadContext* tc) 11412605Sgiacomo.travaglini@arm.com{ 11513882Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushMva(addr, secureLookup, targetEL); 11613882Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL); 11712605Sgiacomo.travaglini@arm.com 11812605Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 11912605Sgiacomo.travaglini@arm.com if (checker) { 12013882Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushMva(addr, secureLookup, targetEL); 12113882Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL); 12212605Sgiacomo.travaglini@arm.com } 12312605Sgiacomo.travaglini@arm.com} 12412605Sgiacomo.travaglini@arm.com 12512605Sgiacomo.travaglini@arm.comvoid 12612605Sgiacomo.travaglini@arm.comTLBIMVA::operator()(ThreadContext* tc) 12712605Sgiacomo.travaglini@arm.com{ 12812605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushMvaAsid(addr, asid, 12912605Sgiacomo.travaglini@arm.com secureLookup, targetEL); 13012605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushMvaAsid(addr, asid, 13112605Sgiacomo.travaglini@arm.com secureLookup, targetEL); 13212605Sgiacomo.travaglini@arm.com 13312605Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 13412605Sgiacomo.travaglini@arm.com if (checker) { 13512605Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushMvaAsid( 13612605Sgiacomo.travaglini@arm.com addr, asid, secureLookup, targetEL); 13712605Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushMvaAsid( 13812605Sgiacomo.travaglini@arm.com addr, asid, secureLookup, targetEL); 13912605Sgiacomo.travaglini@arm.com } 14012605Sgiacomo.travaglini@arm.com} 14112605Sgiacomo.travaglini@arm.com 14212605Sgiacomo.travaglini@arm.comvoid 14312605Sgiacomo.travaglini@arm.comITLBIMVA::operator()(ThreadContext* tc) 14412605Sgiacomo.travaglini@arm.com{ 14512605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushMvaAsid( 14612605Sgiacomo.travaglini@arm.com addr, asid, secureLookup, targetEL); 14712605Sgiacomo.travaglini@arm.com} 14812605Sgiacomo.travaglini@arm.com 14912605Sgiacomo.travaglini@arm.comvoid 15012605Sgiacomo.travaglini@arm.comDTLBIMVA::operator()(ThreadContext* tc) 15112605Sgiacomo.travaglini@arm.com{ 15212605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushMvaAsid( 15312605Sgiacomo.travaglini@arm.com addr, asid, secureLookup, targetEL); 15412605Sgiacomo.travaglini@arm.com} 15512605Sgiacomo.travaglini@arm.com 15612605Sgiacomo.travaglini@arm.comvoid 15712605Sgiacomo.travaglini@arm.comTLBIIPA::operator()(ThreadContext* tc) 15812605Sgiacomo.travaglini@arm.com{ 15912605Sgiacomo.travaglini@arm.com getITBPtr(tc)->flushIpaVmid(addr, 16013882Sgiacomo.travaglini@arm.com secureLookup, targetEL); 16112605Sgiacomo.travaglini@arm.com getDTBPtr(tc)->flushIpaVmid(addr, 16213882Sgiacomo.travaglini@arm.com secureLookup, targetEL); 16312605Sgiacomo.travaglini@arm.com 16412605Sgiacomo.travaglini@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 16512605Sgiacomo.travaglini@arm.com if (checker) { 16612605Sgiacomo.travaglini@arm.com getITBPtr(checker)->flushIpaVmid(addr, 16713882Sgiacomo.travaglini@arm.com secureLookup, targetEL); 16812605Sgiacomo.travaglini@arm.com getDTBPtr(checker)->flushIpaVmid(addr, 16913882Sgiacomo.travaglini@arm.com secureLookup, targetEL); 17012605Sgiacomo.travaglini@arm.com } 17112605Sgiacomo.travaglini@arm.com} 17212605Sgiacomo.travaglini@arm.com 17312605Sgiacomo.travaglini@arm.com} // namespace ArmISA 174