tlbi_op.cc revision 13882 
1/*
2 * Copyright (c) 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Travaglini
38 */
39
40#include "arch/arm/tlbi_op.hh"
41
42#include "arch/arm/tlb.hh"
43#include "cpu/checker/cpu.hh"
44
45namespace ArmISA {
46
47void
48TLBIALL::operator()(ThreadContext* tc)
49{
50    getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
51    getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
52
53    // If CheckerCPU is connected, need to notify it of a flush
54    CheckerCPU *checker = tc->getCheckerCpuPtr();
55    if (checker) {
56        getITBPtr(checker)->flushAllSecurity(secureLookup,
57                                               targetEL);
58        getDTBPtr(checker)->flushAllSecurity(secureLookup,
59                                               targetEL);
60    }
61}
62
63void
64ITLBIALL::operator()(ThreadContext* tc)
65{
66    getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
67}
68
69void
70DTLBIALL::operator()(ThreadContext* tc)
71{
72    getDTBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
73}
74
75void
76TLBIASID::operator()(ThreadContext* tc)
77{
78    getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
79    getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
80    CheckerCPU *checker = tc->getCheckerCpuPtr();
81    if (checker) {
82        getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL);
83        getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL);
84    }
85}
86
87void
88ITLBIASID::operator()(ThreadContext* tc)
89{
90    getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
91}
92
93void
94DTLBIASID::operator()(ThreadContext* tc)
95{
96    getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
97}
98
99void
100TLBIALLN::operator()(ThreadContext* tc)
101{
102    getITBPtr(tc)->flushAllNs(targetEL);
103    getDTBPtr(tc)->flushAllNs(targetEL);
104
105    CheckerCPU *checker = tc->getCheckerCpuPtr();
106    if (checker) {
107        getITBPtr(checker)->flushAllNs(targetEL);
108        getDTBPtr(checker)->flushAllNs(targetEL);
109    }
110}
111
112void
113TLBIMVAA::operator()(ThreadContext* tc)
114{
115    getITBPtr(tc)->flushMva(addr, secureLookup, targetEL);
116    getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL);
117
118    CheckerCPU *checker = tc->getCheckerCpuPtr();
119    if (checker) {
120        getITBPtr(checker)->flushMva(addr, secureLookup, targetEL);
121        getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL);
122    }
123}
124
125void
126TLBIMVA::operator()(ThreadContext* tc)
127{
128    getITBPtr(tc)->flushMvaAsid(addr, asid,
129                                  secureLookup, targetEL);
130    getDTBPtr(tc)->flushMvaAsid(addr, asid,
131                                  secureLookup, targetEL);
132
133    CheckerCPU *checker = tc->getCheckerCpuPtr();
134    if (checker) {
135        getITBPtr(checker)->flushMvaAsid(
136            addr, asid, secureLookup, targetEL);
137        getDTBPtr(checker)->flushMvaAsid(
138            addr, asid, secureLookup, targetEL);
139    }
140}
141
142void
143ITLBIMVA::operator()(ThreadContext* tc)
144{
145    getITBPtr(tc)->flushMvaAsid(
146        addr, asid, secureLookup, targetEL);
147}
148
149void
150DTLBIMVA::operator()(ThreadContext* tc)
151{
152    getDTBPtr(tc)->flushMvaAsid(
153        addr, asid, secureLookup, targetEL);
154}
155
156void
157TLBIIPA::operator()(ThreadContext* tc)
158{
159    getITBPtr(tc)->flushIpaVmid(addr,
160        secureLookup, targetEL);
161    getDTBPtr(tc)->flushIpaVmid(addr,
162        secureLookup, targetEL);
163
164    CheckerCPU *checker = tc->getCheckerCpuPtr();
165    if (checker) {
166        getITBPtr(checker)->flushIpaVmid(addr,
167            secureLookup, targetEL);
168        getDTBPtr(checker)->flushIpaVmid(addr,
169            secureLookup, targetEL);
170    }
171}
172
173} // namespace ArmISA
174