system.hh revision 12318
12567SN/A/* 212317Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2013, 2015-2017 ARM Limited 37650SAli.Saidi@ARM.com * All rights reserved 47650SAli.Saidi@ARM.com * 57650SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67650SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77650SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87650SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97650SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107650SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117650SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127650SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137650SAli.Saidi@ARM.com * 142567SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152567SN/A * All rights reserved. 162567SN/A * 172567SN/A * Redistribution and use in source and binary forms, with or without 182567SN/A * modification, are permitted provided that the following conditions are 192567SN/A * met: redistributions of source code must retain the above copyright 202567SN/A * notice, this list of conditions and the following disclaimer; 212567SN/A * redistributions in binary form must reproduce the above copyright 222567SN/A * notice, this list of conditions and the following disclaimer in the 232567SN/A * documentation and/or other materials provided with the distribution; 242567SN/A * neither the name of the copyright holders nor the names of its 252567SN/A * contributors may be used to endorse or promote products derived from 262567SN/A * this software without specific prior written permission. 272567SN/A * 282567SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292567SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302567SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312567SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322567SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332567SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342567SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352567SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362567SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372567SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382567SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 412567SN/A */ 422567SN/A 436757SAli.Saidi@ARM.com#ifndef __ARCH_ARM_SYSTEM_HH__ 446757SAli.Saidi@ARM.com#define __ARCH_ARM_SYSTEM_HH__ 452567SN/A 4611234Sandreas.sandberg@arm.com#include <memory> 472567SN/A#include <string> 482567SN/A#include <vector> 492567SN/A 508229Snate@binkert.org#include "kern/linux/events.hh" 516757SAli.Saidi@ARM.com#include "params/ArmSystem.hh" 5210810Sbr@bsdpad.com#include "params/GenericArmSystem.hh" 532567SN/A#include "sim/sim_object.hh" 542567SN/A#include "sim/system.hh" 552567SN/A 5610844Sandreas.sandberg@arm.comclass GenericTimer; 5710037SARM gem5 Developersclass ThreadContext; 5810037SARM gem5 Developers 596757SAli.Saidi@ARM.comclass ArmSystem : public System 602567SN/A{ 618285SPrakash.Ramrakhyani@arm.com protected: 627650SAli.Saidi@ARM.com /** 637650SAli.Saidi@ARM.com * PC based event to skip the dprink() call and emulate its 647650SAli.Saidi@ARM.com * functionality 657650SAli.Saidi@ARM.com */ 667650SAli.Saidi@ARM.com Linux::DebugPrintkEvent *debugPrintkEvent; 677650SAli.Saidi@ARM.com 6811234Sandreas.sandberg@arm.com /** Bootloaders */ 6911234Sandreas.sandberg@arm.com std::vector<std::unique_ptr<ObjectFile>> bootLoaders; 7011234Sandreas.sandberg@arm.com 718286SAli.Saidi@ARM.com /** 728286SAli.Saidi@ARM.com * Pointer to the bootloader object 738286SAli.Saidi@ARM.com */ 748286SAli.Saidi@ARM.com ObjectFile *bootldr; 758286SAli.Saidi@ARM.com 7610037SARM gem5 Developers /** 7710037SARM gem5 Developers * True if this system implements the Security Extensions 7810037SARM gem5 Developers */ 7910037SARM gem5 Developers const bool _haveSecurity; 8010037SARM gem5 Developers 8110037SARM gem5 Developers /** 8210037SARM gem5 Developers * True if this system implements the Large Physical Address Extension 8310037SARM gem5 Developers */ 8410037SARM gem5 Developers const bool _haveLPAE; 8510037SARM gem5 Developers 8610037SARM gem5 Developers /** 8710037SARM gem5 Developers * True if this system implements the virtualization Extensions 8810037SARM gem5 Developers */ 8910037SARM gem5 Developers const bool _haveVirtualization; 9010037SARM gem5 Developers 9110037SARM gem5 Developers /** 9210037SARM gem5 Developers * Pointer to the Generic Timer wrapper. 9310037SARM gem5 Developers */ 9410037SARM gem5 Developers GenericTimer *_genericTimer; 9510037SARM gem5 Developers 9610037SARM gem5 Developers /** 9710037SARM gem5 Developers * True if the register width of the highest implemented exception level is 9810037SARM gem5 Developers * 64 bits (ARMv8) 9910037SARM gem5 Developers */ 10010037SARM gem5 Developers bool _highestELIs64; 10110037SARM gem5 Developers 10210037SARM gem5 Developers /** 10310037SARM gem5 Developers * Reset address if the highest implemented exception level is 64 bits 10410037SARM gem5 Developers * (ARMv8) 10510037SARM gem5 Developers */ 10610037SARM gem5 Developers const Addr _resetAddr64; 10710037SARM gem5 Developers 10810037SARM gem5 Developers /** 10910037SARM gem5 Developers * Supported physical address range in bits if the highest implemented 11010037SARM gem5 Developers * exception level is 64 bits (ARMv8) 11110037SARM gem5 Developers */ 11210037SARM gem5 Developers const uint8_t _physAddrRange64; 11310037SARM gem5 Developers 11410037SARM gem5 Developers /** 11510037SARM gem5 Developers * True if ASID is 16 bits in AArch64 (ARMv8) 11610037SARM gem5 Developers */ 11710037SARM gem5 Developers const bool _haveLargeAsid64; 11810037SARM gem5 Developers 11912005Sandreas.sandberg@arm.com /** 12012005Sandreas.sandberg@arm.com * Range for memory-mapped m5 pseudo ops. The range will be 12112005Sandreas.sandberg@arm.com * invalid/empty if disabled. 12212005Sandreas.sandberg@arm.com */ 12312005Sandreas.sandberg@arm.com const AddrRange _m5opRange; 12412005Sandreas.sandberg@arm.com 12511234Sandreas.sandberg@arm.com protected: 12611234Sandreas.sandberg@arm.com /** 12711234Sandreas.sandberg@arm.com * Get a boot loader that matches the kernel. 12811234Sandreas.sandberg@arm.com * 12911234Sandreas.sandberg@arm.com * @param obj Kernel binary 13011234Sandreas.sandberg@arm.com * @return Pointer to boot loader ObjectFile or nullptr if there 13111234Sandreas.sandberg@arm.com * is no matching boot loader. 13211234Sandreas.sandberg@arm.com */ 13311234Sandreas.sandberg@arm.com ObjectFile *getBootLoader(ObjectFile *const obj); 13411234Sandreas.sandberg@arm.com 1352567SN/A public: 1366757SAli.Saidi@ARM.com typedef ArmSystemParams Params; 1378286SAli.Saidi@ARM.com const Params * 1388286SAli.Saidi@ARM.com params() const 1398286SAli.Saidi@ARM.com { 1408286SAli.Saidi@ARM.com return dynamic_cast<const Params *>(_params); 1418286SAli.Saidi@ARM.com } 1428286SAli.Saidi@ARM.com 1436757SAli.Saidi@ARM.com ArmSystem(Params *p); 1446757SAli.Saidi@ARM.com ~ArmSystem(); 1458286SAli.Saidi@ARM.com 1468706Sandreas.hansson@arm.com /** 1478706Sandreas.hansson@arm.com * Initialise the system 1488706Sandreas.hansson@arm.com */ 1498706Sandreas.hansson@arm.com virtual void initState(); 1508286SAli.Saidi@ARM.com 1513553SN/A virtual Addr fixFuncEventAddr(Addr addr) 1523553SN/A { 1537693SAli.Saidi@ARM.com // Remove the low bit that thumb symbols have set 1547693SAli.Saidi@ARM.com // but that aren't actually odd aligned 1557693SAli.Saidi@ARM.com if (addr & 0x1) 1567720Sgblack@eecs.umich.edu return addr & ~1; 1573553SN/A return addr; 1583553SN/A } 1599050Schander.sudanthi@arm.com 1609050Schander.sudanthi@arm.com /** true if this a multiprocessor system */ 1619050Schander.sudanthi@arm.com bool multiProc; 16210037SARM gem5 Developers 16310037SARM gem5 Developers /** Returns true if this system implements the Security Extensions */ 16410037SARM gem5 Developers bool haveSecurity() const { return _haveSecurity; } 16510037SARM gem5 Developers 16610037SARM gem5 Developers /** Returns true if this system implements the Large Physical Address 16710037SARM gem5 Developers * Extension */ 16810037SARM gem5 Developers bool haveLPAE() const { return _haveLPAE; } 16910037SARM gem5 Developers 17010037SARM gem5 Developers /** Returns true if this system implements the virtualization 17110037SARM gem5 Developers * Extensions 17210037SARM gem5 Developers */ 17310037SARM gem5 Developers bool haveVirtualization() const { return _haveVirtualization; } 17410037SARM gem5 Developers 17510037SARM gem5 Developers /** Sets the pointer to the Generic Timer. */ 17610037SARM gem5 Developers void setGenericTimer(GenericTimer *generic_timer) 17710037SARM gem5 Developers { 17810037SARM gem5 Developers _genericTimer = generic_timer; 17910037SARM gem5 Developers } 18010037SARM gem5 Developers 18110844Sandreas.sandberg@arm.com /** Get a pointer to the system's generic timer model */ 18210844Sandreas.sandberg@arm.com GenericTimer *getGenericTimer() const { return _genericTimer; } 18310037SARM gem5 Developers 18410037SARM gem5 Developers /** Returns true if the register width of the highest implemented exception 18510037SARM gem5 Developers * level is 64 bits (ARMv8) */ 18610037SARM gem5 Developers bool highestELIs64() const { return _highestELIs64; } 18710037SARM gem5 Developers 18810037SARM gem5 Developers /** Returns the highest implemented exception level */ 18910037SARM gem5 Developers ExceptionLevel highestEL() const 19010037SARM gem5 Developers { 19110037SARM gem5 Developers if (_haveSecurity) 19210037SARM gem5 Developers return EL3; 19311574SCurtis.Dunham@arm.com if (_haveVirtualization) 19411574SCurtis.Dunham@arm.com return EL2; 19510037SARM gem5 Developers return EL1; 19610037SARM gem5 Developers } 19710037SARM gem5 Developers 19810037SARM gem5 Developers /** Returns the reset address if the highest implemented exception level is 19910037SARM gem5 Developers * 64 bits (ARMv8) */ 20010037SARM gem5 Developers Addr resetAddr64() const { return _resetAddr64; } 20110037SARM gem5 Developers 20210037SARM gem5 Developers /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */ 20310037SARM gem5 Developers bool haveLargeAsid64() const { return _haveLargeAsid64; } 20410037SARM gem5 Developers 20510037SARM gem5 Developers /** Returns the supported physical address range in bits if the highest 20610037SARM gem5 Developers * implemented exception level is 64 bits (ARMv8) */ 20710037SARM gem5 Developers uint8_t physAddrRange64() const { return _physAddrRange64; } 20810037SARM gem5 Developers 20910037SARM gem5 Developers /** Returns the supported physical address range in bits */ 21010037SARM gem5 Developers uint8_t physAddrRange() const 21110037SARM gem5 Developers { 21210037SARM gem5 Developers if (_highestELIs64) 21310037SARM gem5 Developers return _physAddrRange64; 21410037SARM gem5 Developers if (_haveLPAE) 21510037SARM gem5 Developers return 40; 21610037SARM gem5 Developers return 32; 21710037SARM gem5 Developers } 21810037SARM gem5 Developers 21910037SARM gem5 Developers /** Returns the physical address mask */ 22010037SARM gem5 Developers Addr physAddrMask() const 22110037SARM gem5 Developers { 22210037SARM gem5 Developers return mask(physAddrRange()); 22310037SARM gem5 Developers } 22410037SARM gem5 Developers 22512005Sandreas.sandberg@arm.com /** 22612005Sandreas.sandberg@arm.com * Range used by memory-mapped m5 pseudo-ops if enabled. Returns 22712005Sandreas.sandberg@arm.com * an invalid/empty range if disabled. 22812005Sandreas.sandberg@arm.com */ 22912005Sandreas.sandberg@arm.com const AddrRange &m5opRange() const { return _m5opRange; } 23012005Sandreas.sandberg@arm.com 23112317Sgiacomo.travaglini@arm.com /** 23212317Sgiacomo.travaglini@arm.com * Returns a valid ArmSystem pointer if using ARM ISA, it fails 23312317Sgiacomo.travaglini@arm.com * otherwise. 23412317Sgiacomo.travaglini@arm.com */ 23512317Sgiacomo.travaglini@arm.com static ArmSystem* getArmSystem(ThreadContext *tc); 23612317Sgiacomo.travaglini@arm.com 23710037SARM gem5 Developers /** Returns true if the system of a specific thread context implements the 23810037SARM gem5 Developers * Security Extensions 23910037SARM gem5 Developers */ 24010037SARM gem5 Developers static bool haveSecurity(ThreadContext *tc); 24110037SARM gem5 Developers 24210037SARM gem5 Developers /** Returns true if the system of a specific thread context implements the 24310037SARM gem5 Developers * virtualization Extensions 24410037SARM gem5 Developers */ 24510037SARM gem5 Developers static bool haveVirtualization(ThreadContext *tc); 24610037SARM gem5 Developers 24710037SARM gem5 Developers /** Returns true if the system of a specific thread context implements the 24810037SARM gem5 Developers * Large Physical Address Extension 24910037SARM gem5 Developers */ 25010037SARM gem5 Developers static bool haveLPAE(ThreadContext *tc); 25110037SARM gem5 Developers 25210037SARM gem5 Developers /** Returns true if the register width of the highest implemented exception 25310037SARM gem5 Developers * level for the system of a specific thread context is 64 bits (ARMv8) 25410037SARM gem5 Developers */ 25510037SARM gem5 Developers static bool highestELIs64(ThreadContext *tc); 25610037SARM gem5 Developers 25710037SARM gem5 Developers /** Returns the highest implemented exception level for the system of a 25810037SARM gem5 Developers * specific thread context 25910037SARM gem5 Developers */ 26010037SARM gem5 Developers static ExceptionLevel highestEL(ThreadContext *tc); 26110037SARM gem5 Developers 26212318Sgiacomo.travaglini@arm.com /** Return true if the system implements a specific exception level */ 26312318Sgiacomo.travaglini@arm.com static bool haveEL(ThreadContext *tc, ExceptionLevel el); 26412318Sgiacomo.travaglini@arm.com 26512318Sgiacomo.travaglini@arm.com /** Returns the reset address if the highest implemented exception level 26612318Sgiacomo.travaglini@arm.com * for the system of a specific thread context is 64 bits (ARMv8) 26710037SARM gem5 Developers */ 26810037SARM gem5 Developers static Addr resetAddr64(ThreadContext *tc); 26910037SARM gem5 Developers 27010037SARM gem5 Developers /** Returns the supported physical address range in bits for the system of a 27110037SARM gem5 Developers * specific thread context 27210037SARM gem5 Developers */ 27310037SARM gem5 Developers static uint8_t physAddrRange(ThreadContext *tc); 27410037SARM gem5 Developers 27510037SARM gem5 Developers /** Returns the physical address mask for the system of a specific thread 27610037SARM gem5 Developers * context 27710037SARM gem5 Developers */ 27810037SARM gem5 Developers static Addr physAddrMask(ThreadContext *tc); 27910037SARM gem5 Developers 28010037SARM gem5 Developers /** Returns true if ASID is 16 bits for the system of a specific thread 28110037SARM gem5 Developers * context while in AArch64 (ARMv8) */ 28210037SARM gem5 Developers static bool haveLargeAsid64(ThreadContext *tc); 28310810Sbr@bsdpad.com}; 28410037SARM gem5 Developers 28510810Sbr@bsdpad.comclass GenericArmSystem : public ArmSystem 28610810Sbr@bsdpad.com{ 28710810Sbr@bsdpad.com public: 28810810Sbr@bsdpad.com typedef GenericArmSystemParams Params; 28910810Sbr@bsdpad.com const Params * 29010810Sbr@bsdpad.com params() const 29110810Sbr@bsdpad.com { 29210810Sbr@bsdpad.com return dynamic_cast<const Params *>(_params); 29310810Sbr@bsdpad.com } 29410810Sbr@bsdpad.com 29510810Sbr@bsdpad.com GenericArmSystem(Params *p) : ArmSystem(p) {}; 29610810Sbr@bsdpad.com virtual ~GenericArmSystem() {}; 29710810Sbr@bsdpad.com 29810810Sbr@bsdpad.com /** 29910810Sbr@bsdpad.com * Initialise the system 30010810Sbr@bsdpad.com */ 30110810Sbr@bsdpad.com virtual void initState(); 3022567SN/A}; 3032567SN/A 3042567SN/A#endif 305