system.hh revision 12318 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61  protected:
62    /**
63     * PC based event to skip the dprink() call and emulate its
64     * functionality
65     */
66    Linux::DebugPrintkEvent *debugPrintkEvent;
67
68    /** Bootloaders */
69    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71    /**
72     * Pointer to the bootloader object
73     */
74    ObjectFile *bootldr;
75
76    /**
77     * True if this system implements the Security Extensions
78     */
79    const bool _haveSecurity;
80
81    /**
82     * True if this system implements the Large Physical Address Extension
83     */
84    const bool _haveLPAE;
85
86    /**
87     * True if this system implements the virtualization Extensions
88     */
89    const bool _haveVirtualization;
90
91    /**
92     * Pointer to the Generic Timer wrapper.
93     */
94    GenericTimer *_genericTimer;
95
96    /**
97     * True if the register width of the highest implemented exception level is
98     * 64 bits (ARMv8)
99     */
100    bool _highestELIs64;
101
102    /**
103     * Reset address if the highest implemented exception level is 64 bits
104     * (ARMv8)
105     */
106    const Addr _resetAddr64;
107
108    /**
109     * Supported physical address range in bits if the highest implemented
110     * exception level is 64 bits (ARMv8)
111     */
112    const uint8_t _physAddrRange64;
113
114    /**
115     * True if ASID is 16 bits in AArch64 (ARMv8)
116     */
117    const bool _haveLargeAsid64;
118
119    /**
120     * Range for memory-mapped m5 pseudo ops. The range will be
121     * invalid/empty if disabled.
122     */
123    const AddrRange _m5opRange;
124
125  protected:
126    /**
127     * Get a boot loader that matches the kernel.
128     *
129     * @param obj Kernel binary
130     * @return Pointer to boot loader ObjectFile or nullptr if there
131     *         is no matching boot loader.
132     */
133    ObjectFile *getBootLoader(ObjectFile *const obj);
134
135  public:
136    typedef ArmSystemParams Params;
137    const Params *
138    params() const
139    {
140        return dynamic_cast<const Params *>(_params);
141    }
142
143    ArmSystem(Params *p);
144    ~ArmSystem();
145
146    /**
147     * Initialise the system
148     */
149    virtual void initState();
150
151    virtual Addr fixFuncEventAddr(Addr addr)
152    {
153        // Remove the low bit that thumb symbols have set
154        // but that aren't actually odd aligned
155        if (addr & 0x1)
156            return addr & ~1;
157        return addr;
158    }
159
160    /** true if this a multiprocessor system */
161    bool multiProc;
162
163    /** Returns true if this system implements the Security Extensions */
164    bool haveSecurity() const { return _haveSecurity; }
165
166    /** Returns true if this system implements the Large Physical Address
167     * Extension */
168    bool haveLPAE() const { return _haveLPAE; }
169
170    /** Returns true if this system implements the virtualization
171      * Extensions
172      */
173    bool haveVirtualization() const { return _haveVirtualization; }
174
175    /** Sets the pointer to the Generic Timer. */
176    void setGenericTimer(GenericTimer *generic_timer)
177    {
178        _genericTimer = generic_timer;
179    }
180
181    /** Get a pointer to the system's generic timer model */
182    GenericTimer *getGenericTimer() const { return _genericTimer; }
183
184    /** Returns true if the register width of the highest implemented exception
185     * level is 64 bits (ARMv8) */
186    bool highestELIs64() const { return _highestELIs64; }
187
188    /** Returns the highest implemented exception level */
189    ExceptionLevel highestEL() const
190    {
191        if (_haveSecurity)
192            return EL3;
193        if (_haveVirtualization)
194            return EL2;
195        return EL1;
196    }
197
198    /** Returns the reset address if the highest implemented exception level is
199     * 64 bits (ARMv8) */
200    Addr resetAddr64() const { return _resetAddr64; }
201
202    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
203    bool haveLargeAsid64() const { return _haveLargeAsid64; }
204
205    /** Returns the supported physical address range in bits if the highest
206     * implemented exception level is 64 bits (ARMv8) */
207    uint8_t physAddrRange64() const { return _physAddrRange64; }
208
209    /** Returns the supported physical address range in bits */
210    uint8_t physAddrRange() const
211    {
212        if (_highestELIs64)
213            return _physAddrRange64;
214        if (_haveLPAE)
215            return 40;
216        return 32;
217    }
218
219    /** Returns the physical address mask */
220    Addr physAddrMask() const
221    {
222        return mask(physAddrRange());
223    }
224
225    /**
226     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
227     * an invalid/empty range if disabled.
228     */
229    const AddrRange &m5opRange() const { return _m5opRange; }
230
231    /**
232     * Returns a valid ArmSystem pointer if using ARM ISA, it fails
233     * otherwise.
234     */
235    static ArmSystem* getArmSystem(ThreadContext *tc);
236
237    /** Returns true if the system of a specific thread context implements the
238     * Security Extensions
239     */
240    static bool haveSecurity(ThreadContext *tc);
241
242    /** Returns true if the system of a specific thread context implements the
243     * virtualization Extensions
244     */
245    static bool haveVirtualization(ThreadContext *tc);
246
247    /** Returns true if the system of a specific thread context implements the
248     * Large Physical Address Extension
249     */
250    static bool haveLPAE(ThreadContext *tc);
251
252    /** Returns true if the register width of the highest implemented exception
253     * level for the system of a specific thread context is 64 bits (ARMv8)
254     */
255    static bool highestELIs64(ThreadContext *tc);
256
257    /** Returns the highest implemented exception level for the system of a
258     * specific thread context
259     */
260    static ExceptionLevel highestEL(ThreadContext *tc);
261
262    /** Return true if the system implements a specific exception level */
263    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
264
265    /** Returns the reset address if the highest implemented exception level
266     * for the system of a specific thread context is 64 bits (ARMv8)
267     */
268    static Addr resetAddr64(ThreadContext *tc);
269
270    /** Returns the supported physical address range in bits for the system of a
271     * specific thread context
272     */
273    static uint8_t physAddrRange(ThreadContext *tc);
274
275    /** Returns the physical address mask for the system of a specific thread
276     * context
277     */
278    static Addr physAddrMask(ThreadContext *tc);
279
280    /** Returns true if ASID is 16 bits for the system of a specific thread
281     * context while in AArch64 (ARMv8) */
282    static bool haveLargeAsid64(ThreadContext *tc);
283};
284
285class GenericArmSystem : public ArmSystem
286{
287  public:
288    typedef GenericArmSystemParams Params;
289    const Params *
290    params() const
291    {
292        return dynamic_cast<const Params *>(_params);
293    }
294
295    GenericArmSystem(Params *p) : ArmSystem(p) {};
296    virtual ~GenericArmSystem() {};
297
298    /**
299     * Initialise the system
300     */
301    virtual void initState();
302};
303
304#endif
305