process.cc revision 8232
16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2010 ARM Limited 36691Stjones1@inf.ed.ac.uk * All rights reserved 46691Stjones1@inf.ed.ac.uk * 56691Stjones1@inf.ed.ac.uk * The license below extends only to copyright in the software and shall 66691Stjones1@inf.ed.ac.uk * not be construed as granting a license to any other intellectual 76691Stjones1@inf.ed.ac.uk * property including but not limited to intellectual property relating 86691Stjones1@inf.ed.ac.uk * to a hardware implementation of the functionality of the software 96691Stjones1@inf.ed.ac.uk * licensed hereunder. You may use the software subject to the license 106691Stjones1@inf.ed.ac.uk * terms below provided that you ensure that this notice is replicated 116691Stjones1@inf.ed.ac.uk * unmodified and in its entirety in all distributions of the software, 126691Stjones1@inf.ed.ac.uk * modified or unmodified, in source code or in binary form. 136691Stjones1@inf.ed.ac.uk * 146691Stjones1@inf.ed.ac.uk * Copyright (c) 2007-2008 The Florida State University 156691Stjones1@inf.ed.ac.uk * All rights reserved. 166691Stjones1@inf.ed.ac.uk * 176691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 186691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 196691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 206691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 216691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 226691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 236691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 246691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 256691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 266691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 276691Stjones1@inf.ed.ac.uk * 286691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396691Stjones1@inf.ed.ac.uk * 406691Stjones1@inf.ed.ac.uk * Authors: Stephen Hines 416691Stjones1@inf.ed.ac.uk * Ali Saidi 4210687SAndreas.Sandberg@ARM.com */ 436691Stjones1@inf.ed.ac.uk 448229Snate@binkert.org#include "arch/arm/isa_traits.hh" 456691Stjones1@inf.ed.ac.uk#include "arch/arm/process.hh" 466691Stjones1@inf.ed.ac.uk#include "arch/arm/types.hh" 476691Stjones1@inf.ed.ac.uk#include "base/loader/elf_object.hh" 486691Stjones1@inf.ed.ac.uk#include "base/loader/object_file.hh" 496691Stjones1@inf.ed.ac.uk#include "base/misc.hh" 506691Stjones1@inf.ed.ac.uk#include "cpu/thread_context.hh" 516691Stjones1@inf.ed.ac.uk#include "debug/Stack.hh" 526691Stjones1@inf.ed.ac.uk#include "mem/page_table.hh" 536691Stjones1@inf.ed.ac.uk#include "mem/translating_port.hh" 546691Stjones1@inf.ed.ac.uk#include "sim/byteswap.hh" 556691Stjones1@inf.ed.ac.uk#include "sim/process_impl.hh" 566691Stjones1@inf.ed.ac.uk#include "sim/system.hh" 576691Stjones1@inf.ed.ac.uk 586691Stjones1@inf.ed.ac.ukusing namespace std; 596691Stjones1@inf.ed.ac.ukusing namespace ArmISA; 606691Stjones1@inf.ed.ac.uk 616691Stjones1@inf.ed.ac.ukArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile, 626691Stjones1@inf.ed.ac.uk ObjectFile::Arch _arch) 636691Stjones1@inf.ed.ac.uk : LiveProcess(params, objFile), arch(_arch) 646691Stjones1@inf.ed.ac.uk{ 6510558Salexandru.dutu@amd.com stack_base = 0xbf000000L; 6610558Salexandru.dutu@amd.com 676691Stjones1@inf.ed.ac.uk // Set pointer for next thread stack. Reserve 8M for main stack. 686691Stjones1@inf.ed.ac.uk next_thread_stack_base = stack_base - (8 * 1024 * 1024); 6910558Salexandru.dutu@amd.com 7010558Salexandru.dutu@amd.com // Set up break point (Top of Heap) 7110558Salexandru.dutu@amd.com brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 726691Stjones1@inf.ed.ac.uk brk_point = roundUp(brk_point, VMPageSize); 736691Stjones1@inf.ed.ac.uk 746691Stjones1@inf.ed.ac.uk // Set up region for mmaps. For now, start at bottom of kuseg space. 756691Stjones1@inf.ed.ac.uk mmap_start = mmap_end = 0x40000000L; 766691Stjones1@inf.ed.ac.uk} 776691Stjones1@inf.ed.ac.uk 786691Stjones1@inf.ed.ac.ukvoid 796691Stjones1@inf.ed.ac.ukArmLiveProcess::initState() 806691Stjones1@inf.ed.ac.uk{ 816691Stjones1@inf.ed.ac.uk LiveProcess::initState(); 826691Stjones1@inf.ed.ac.uk argsInit(MachineBytes, VMPageSize); 836691Stjones1@inf.ed.ac.uk for (int i = 0; i < contextIds.size(); i++) { 846691Stjones1@inf.ed.ac.uk ThreadContext * tc = system->getThreadContext(contextIds[i]); 856691Stjones1@inf.ed.ac.uk CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 866691Stjones1@inf.ed.ac.uk // Enable the floating point coprocessors. 876691Stjones1@inf.ed.ac.uk cpacr.cp10 = 0x3; 886691Stjones1@inf.ed.ac.uk cpacr.cp11 = 0x3; 896691Stjones1@inf.ed.ac.uk tc->setMiscReg(MISCREG_CPACR, cpacr); 906691Stjones1@inf.ed.ac.uk // Generically enable floating point support. 916691Stjones1@inf.ed.ac.uk FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 926691Stjones1@inf.ed.ac.uk fpexc.en = 1; 936691Stjones1@inf.ed.ac.uk tc->setMiscReg(MISCREG_FPEXC, fpexc); 946691Stjones1@inf.ed.ac.uk } 956691Stjones1@inf.ed.ac.uk} 966691Stjones1@inf.ed.ac.uk 976691Stjones1@inf.ed.ac.ukvoid 986691Stjones1@inf.ed.ac.ukArmLiveProcess::argsInit(int intSize, int pageSize) 996691Stjones1@inf.ed.ac.uk{ 1006691Stjones1@inf.ed.ac.uk typedef AuxVector<uint32_t> auxv_t; 1016691Stjones1@inf.ed.ac.uk std::vector<auxv_t> auxv; 1026691Stjones1@inf.ed.ac.uk 1036691Stjones1@inf.ed.ac.uk string filename; 1046691Stjones1@inf.ed.ac.uk if (argv.size() < 1) 1056691Stjones1@inf.ed.ac.uk filename = ""; 1066691Stjones1@inf.ed.ac.uk else 1076691Stjones1@inf.ed.ac.uk filename = argv[0]; 1086691Stjones1@inf.ed.ac.uk 1096691Stjones1@inf.ed.ac.uk //We want 16 byte alignment 1106691Stjones1@inf.ed.ac.uk uint64_t align = 16; 1116691Stjones1@inf.ed.ac.uk 1126691Stjones1@inf.ed.ac.uk // load object file into target memory 1136691Stjones1@inf.ed.ac.uk objFile->loadSections(initVirtMem); 1146691Stjones1@inf.ed.ac.uk 1156691Stjones1@inf.ed.ac.uk enum ArmCpuFeature { 1166691Stjones1@inf.ed.ac.uk Arm_Swp = 1 << 0, 1176691Stjones1@inf.ed.ac.uk Arm_Half = 1 << 1, 1186691Stjones1@inf.ed.ac.uk Arm_Thumb = 1 << 2, 1196691Stjones1@inf.ed.ac.uk Arm_26Bit = 1 << 3, 1206691Stjones1@inf.ed.ac.uk Arm_FastMult = 1 << 4, 1216691Stjones1@inf.ed.ac.uk Arm_Fpa = 1 << 5, 1226691Stjones1@inf.ed.ac.uk Arm_Vfp = 1 << 6, 1236691Stjones1@inf.ed.ac.uk Arm_Edsp = 1 << 7, 1246691Stjones1@inf.ed.ac.uk Arm_Java = 1 << 8, 1256691Stjones1@inf.ed.ac.uk Arm_Iwmmxt = 1 << 9, 1266691Stjones1@inf.ed.ac.uk Arm_Crunch = 1 << 10, 1276691Stjones1@inf.ed.ac.uk Arm_ThumbEE = 1 << 11, 1286691Stjones1@inf.ed.ac.uk Arm_Neon = 1 << 12, 1296691Stjones1@inf.ed.ac.uk Arm_Vfpv3 = 1 << 13, 1306691Stjones1@inf.ed.ac.uk Arm_Vfpv3d16 = 1 << 14 1316691Stjones1@inf.ed.ac.uk }; 1326691Stjones1@inf.ed.ac.uk 1336691Stjones1@inf.ed.ac.uk //Setup the auxilliary vectors. These will already have endian conversion. 1346691Stjones1@inf.ed.ac.uk //Auxilliary vectors are loaded only for elf formatted executables. 1356691Stjones1@inf.ed.ac.uk ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 13610194SGeoffrey.Blake@arm.com if (elfObject) { 13710194SGeoffrey.Blake@arm.com uint32_t features = 1386691Stjones1@inf.ed.ac.uk Arm_Swp | 1396691Stjones1@inf.ed.ac.uk Arm_Half | 1406691Stjones1@inf.ed.ac.uk Arm_Thumb | 1416691Stjones1@inf.ed.ac.uk// Arm_26Bit | 1426691Stjones1@inf.ed.ac.uk Arm_FastMult | 1436691Stjones1@inf.ed.ac.uk// Arm_Fpa | 1446691Stjones1@inf.ed.ac.uk Arm_Vfp | 1456691Stjones1@inf.ed.ac.uk Arm_Edsp | 1466691Stjones1@inf.ed.ac.uk// Arm_Java | 1476691Stjones1@inf.ed.ac.uk// Arm_Iwmmxt | 1486691Stjones1@inf.ed.ac.uk// Arm_Crunch | 1496691Stjones1@inf.ed.ac.uk Arm_ThumbEE | 1506691Stjones1@inf.ed.ac.uk Arm_Neon | 1516691Stjones1@inf.ed.ac.uk Arm_Vfpv3 | 1526691Stjones1@inf.ed.ac.uk Arm_Vfpv3d16 | 1536691Stjones1@inf.ed.ac.uk 0; 1546691Stjones1@inf.ed.ac.uk 1556691Stjones1@inf.ed.ac.uk //Bits which describe the system hardware capabilities 1566691Stjones1@inf.ed.ac.uk //XXX Figure out what these should be 1576691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 1586691Stjones1@inf.ed.ac.uk //The system page size 1596691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize)); 1606691Stjones1@inf.ed.ac.uk //Frequency at which times() increments 1616691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 1626691Stjones1@inf.ed.ac.uk // For statically linked executables, this is the virtual address of the 1636972Stjones1@inf.ed.ac.uk // program header tables if they appear in the executable image 1646972Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 1656691Stjones1@inf.ed.ac.uk // This is the size of a program header entry from the elf file. 1666691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 1676691Stjones1@inf.ed.ac.uk // This is the number of program headers from the original elf file. 1688888Sgeoffrey.blake@arm.com auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 1698888Sgeoffrey.blake@arm.com //This is the address of the elf "interpreter", It should be set 1708888Sgeoffrey.blake@arm.com //to 0 for regular executables. It should be something else 1718888Sgeoffrey.blake@arm.com //(not sure what) for dynamic libraries. 1729738Sandreas@sandberg.pp.se auxv.push_back(auxv_t(M5_AT_BASE, 0)); 1736691Stjones1@inf.ed.ac.uk 1746691Stjones1@inf.ed.ac.uk //XXX Figure out what this should be. 1756691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 1766691Stjones1@inf.ed.ac.uk //The entry point to the program 1776691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 1786691Stjones1@inf.ed.ac.uk //Different user and group IDs 1796691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_UID, uid())); 1807811Ssteve.reinhardt@amd.com auxv.push_back(auxv_t(M5_AT_EUID, euid())); 1816691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_GID, gid())); 1826691Stjones1@inf.ed.ac.uk auxv.push_back(auxv_t(M5_AT_EGID, egid())); 183 //Whether to enable "secure mode" in the executable 184 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 185 186 // Pointer to 16 bytes of random data 187 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 188 189 //The filename of the program 190 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 191 //The string "v71" -- ARM v7 architecture 192 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 193 } 194 195 //Figure out how big the initial stack nedes to be 196 197 // A sentry NULL void pointer at the top of the stack. 198 int sentry_size = intSize; 199 200 string platform = "v71"; 201 int platform_size = platform.size() + 1; 202 203 // Bytes for AT_RANDOM above, we'll just keep them 0 204 int aux_random_size = 16; // as per the specification 205 206 // The aux vectors are put on the stack in two groups. The first group are 207 // the vectors that are generated as the elf is loaded. The second group 208 // are the ones that were computed ahead of time and include the platform 209 // string. 210 int aux_data_size = filename.size() + 1; 211 212 int env_data_size = 0; 213 for (int i = 0; i < envp.size(); ++i) { 214 env_data_size += envp[i].size() + 1; 215 } 216 int arg_data_size = 0; 217 for (int i = 0; i < argv.size(); ++i) { 218 arg_data_size += argv[i].size() + 1; 219 } 220 221 int info_block_size = 222 sentry_size + env_data_size + arg_data_size + 223 aux_data_size + platform_size + aux_random_size; 224 225 //Each auxilliary vector is two 4 byte words 226 int aux_array_size = intSize * 2 * (auxv.size() + 1); 227 228 int envp_array_size = intSize * (envp.size() + 1); 229 int argv_array_size = intSize * (argv.size() + 1); 230 231 int argc_size = intSize; 232 233 //Figure out the size of the contents of the actual initial frame 234 int frame_size = 235 info_block_size + 236 aux_array_size + 237 envp_array_size + 238 argv_array_size + 239 argc_size; 240 241 //There needs to be padding after the auxiliary vector data so that the 242 //very bottom of the stack is aligned properly. 243 int partial_size = frame_size; 244 int aligned_partial_size = roundUp(partial_size, align); 245 int aux_padding = aligned_partial_size - partial_size; 246 247 int space_needed = frame_size + aux_padding; 248 249 stack_min = stack_base - space_needed; 250 stack_min = roundDown(stack_min, align); 251 stack_size = stack_base - stack_min; 252 253 // map memory 254 pTable->allocate(roundDown(stack_min, pageSize), 255 roundUp(stack_size, pageSize)); 256 257 // map out initial stack contents 258 uint32_t sentry_base = stack_base - sentry_size; 259 uint32_t aux_data_base = sentry_base - aux_data_size; 260 uint32_t env_data_base = aux_data_base - env_data_size; 261 uint32_t arg_data_base = env_data_base - arg_data_size; 262 uint32_t platform_base = arg_data_base - platform_size; 263 uint32_t aux_random_base = platform_base - aux_random_size; 264 uint32_t auxv_array_base = aux_random_base - aux_array_size - aux_padding; 265 uint32_t envp_array_base = auxv_array_base - envp_array_size; 266 uint32_t argv_array_base = envp_array_base - argv_array_size; 267 uint32_t argc_base = argv_array_base - argc_size; 268 269 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 270 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 271 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 272 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 273 DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 274 DPRINTF(Stack, "0x%x - platform base\n", platform_base); 275 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 276 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 277 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 278 DPRINTF(Stack, "0x%x - argc \n", argc_base); 279 DPRINTF(Stack, "0x%x - stack min\n", stack_min); 280 281 // write contents to stack 282 283 // figure out argc 284 uint32_t argc = argv.size(); 285 uint32_t guestArgc = ArmISA::htog(argc); 286 287 //Write out the sentry void * 288 uint32_t sentry_NULL = 0; 289 initVirtMem->writeBlob(sentry_base, 290 (uint8_t*)&sentry_NULL, sentry_size); 291 292 //Fix up the aux vectors which point to other data 293 for (int i = auxv.size() - 1; i >= 0; i--) { 294 if (auxv[i].a_type == M5_AT_PLATFORM) { 295 auxv[i].a_val = platform_base; 296 initVirtMem->writeString(platform_base, platform.c_str()); 297 } else if (auxv[i].a_type == M5_AT_EXECFN) { 298 auxv[i].a_val = aux_data_base; 299 initVirtMem->writeString(aux_data_base, filename.c_str()); 300 } else if (auxv[i].a_type == M5_AT_RANDOM) { 301 auxv[i].a_val = aux_random_base; 302 // Just leave the value 0, we don't want randomness 303 } 304 } 305 306 //Copy the aux stuff 307 for(int x = 0; x < auxv.size(); x++) 308 { 309 initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 310 (uint8_t*)&(auxv[x].a_type), intSize); 311 initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 312 (uint8_t*)&(auxv[x].a_val), intSize); 313 } 314 //Write out the terminating zeroed auxilliary vector 315 const uint64_t zero = 0; 316 initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 317 (uint8_t*)&zero, 2 * intSize); 318 319 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 320 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 321 322 initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 323 324 ThreadContext *tc = system->getThreadContext(contextIds[0]); 325 //Set the stack pointer register 326 tc->setIntReg(StackPointerReg, stack_min); 327 //A pointer to a function to run when the program exits. We'll set this 328 //to zero explicitly to make sure this isn't used. 329 tc->setIntReg(ArgumentReg0, 0); 330 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 331 if (argv.size() > 0) { 332 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 333 argv[argv.size() - 1].size() - 1); 334 } else { 335 tc->setIntReg(ArgumentReg1, 0); 336 } 337 if (envp.size() > 0) { 338 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 339 envp[envp.size() - 1].size() - 1); 340 } else { 341 tc->setIntReg(ArgumentReg2, 0); 342 } 343 344 PCState pc; 345 pc.thumb(arch == ObjectFile::Thumb); 346 pc.nextThumb(pc.thumb()); 347 pc.set(objFile->entryPoint() & ~mask(1)); 348 tc->pcState(pc); 349 350 //Align the "stack_min" to a page boundary. 351 stack_min = roundDown(stack_min, pageSize); 352} 353 354ArmISA::IntReg 355ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i) 356{ 357 assert(i < 6); 358 return tc->readIntReg(ArgumentReg0 + i++); 359} 360 361uint64_t 362ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i, int width) 363{ 364 assert(width == 32 || width == 64); 365 if (width == 32) 366 return getSyscallArg(tc, i); 367 368 // 64 bit arguments are passed starting in an even register 369 if (i % 2 != 0) 370 i++; 371 372 // Registers r0-r6 can be used 373 assert(i < 5); 374 uint64_t val; 375 val = tc->readIntReg(ArgumentReg0 + i++); 376 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 377 return val; 378} 379 380 381void 382ArmLiveProcess::setSyscallArg(ThreadContext *tc, 383 int i, ArmISA::IntReg val) 384{ 385 assert(i < 4); 386 tc->setIntReg(ArgumentReg0 + i, val); 387} 388 389void 390ArmLiveProcess::setSyscallReturn(ThreadContext *tc, 391 SyscallReturn return_value) 392{ 393 tc->setIntReg(ReturnValueReg, return_value.value()); 394} 395