process.cc revision 13122:32e21edd0a61
1/* 2 * Copyright (c) 2010, 2012, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 * Ali Saidi 42 */ 43 44#include "arch/arm/process.hh" 45 46#include "arch/arm/isa_traits.hh" 47#include "arch/arm/types.hh" 48#include "base/loader/elf_object.hh" 49#include "base/loader/object_file.hh" 50#include "base/logging.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Stack.hh" 53#include "mem/page_table.hh" 54#include "params/Process.hh" 55#include "sim/aux_vector.hh" 56#include "sim/byteswap.hh" 57#include "sim/process_impl.hh" 58#include "sim/syscall_return.hh" 59#include "sim/system.hh" 60 61using namespace std; 62using namespace ArmISA; 63 64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile, 65 ObjectFile::Arch _arch) 66 : Process(params, 67 new EmulationPageTable(params->name, params->pid, PageBytes), 68 objFile), 69 arch(_arch) 70{ 71 fatal_if(params->useArchPT, "Arch page tables not implemented."); 72} 73 74ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, 75 ObjectFile::Arch _arch) 76 : ArmProcess(params, objFile, _arch) 77{ 78 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 79 objFile->bssSize(), PageBytes); 80 Addr stack_base = 0xbf000000L; 81 Addr max_stack_size = 8 * 1024 * 1024; 82 Addr next_thread_stack_base = stack_base - max_stack_size; 83 Addr mmap_end = 0x40000000L; 84 85 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 86 next_thread_stack_base, mmap_end); 87} 88 89ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile, 90 ObjectFile::Arch _arch) 91 : ArmProcess(params, objFile, _arch) 92{ 93 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 94 objFile->bssSize(), PageBytes); 95 Addr stack_base = 0x7fffff0000L; 96 Addr max_stack_size = 8 * 1024 * 1024; 97 Addr next_thread_stack_base = stack_base - max_stack_size; 98 Addr mmap_end = 0x4000000000L; 99 100 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 101 next_thread_stack_base, mmap_end); 102} 103 104void 105ArmProcess32::initState() 106{ 107 Process::initState(); 108 argsInit<uint32_t>(PageBytes, INTREG_SP); 109 for (int i = 0; i < contextIds.size(); i++) { 110 ThreadContext * tc = system->getThreadContext(contextIds[i]); 111 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 112 // Enable the floating point coprocessors. 113 cpacr.cp10 = 0x3; 114 cpacr.cp11 = 0x3; 115 tc->setMiscReg(MISCREG_CPACR, cpacr); 116 // Generically enable floating point support. 117 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 118 fpexc.en = 1; 119 tc->setMiscReg(MISCREG_FPEXC, fpexc); 120 } 121} 122 123void 124ArmProcess64::initState() 125{ 126 Process::initState(); 127 argsInit<uint64_t>(PageBytes, INTREG_SP0); 128 for (int i = 0; i < contextIds.size(); i++) { 129 ThreadContext * tc = system->getThreadContext(contextIds[i]); 130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 131 cpsr.mode = MODE_EL0T; 132 tc->setMiscReg(MISCREG_CPSR, cpsr); 133 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 134 // Enable the floating point coprocessors. 135 cpacr.cp10 = 0x3; 136 cpacr.cp11 = 0x3; 137 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr); 138 // Generically enable floating point support. 139 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 140 fpexc.en = 1; 141 tc->setMiscReg(MISCREG_FPEXC, fpexc); 142 } 143} 144 145uint32_t 146ArmProcess32::armHwcapImpl() const 147{ 148 enum ArmCpuFeature { 149 Arm_Swp = 1 << 0, 150 Arm_Half = 1 << 1, 151 Arm_Thumb = 1 << 2, 152 Arm_26Bit = 1 << 3, 153 Arm_FastMult = 1 << 4, 154 Arm_Fpa = 1 << 5, 155 Arm_Vfp = 1 << 6, 156 Arm_Edsp = 1 << 7, 157 Arm_Java = 1 << 8, 158 Arm_Iwmmxt = 1 << 9, 159 Arm_Crunch = 1 << 10, 160 Arm_ThumbEE = 1 << 11, 161 Arm_Neon = 1 << 12, 162 Arm_Vfpv3 = 1 << 13, 163 Arm_Vfpv3d16 = 1 << 14 164 }; 165 166 return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult | 167 Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon | 168 Arm_Vfpv3 | Arm_Vfpv3d16; 169} 170 171uint32_t 172ArmProcess64::armHwcapImpl() const 173{ 174 // In order to know what these flags mean, please refer to Linux 175 // /Documentation/arm64/elf_hwcaps.txt text file. 176 enum ArmCpuFeature { 177 Arm_Fp = 1 << 0, 178 Arm_Asimd = 1 << 1, 179 Arm_Evtstrm = 1 << 2, 180 Arm_Aes = 1 << 3, 181 Arm_Pmull = 1 << 4, 182 Arm_Sha1 = 1 << 5, 183 Arm_Sha2 = 1 << 6, 184 Arm_Crc32 = 1 << 7, 185 Arm_Atomics = 1 << 8, 186 Arm_Fphp = 1 << 9, 187 Arm_Asimdhp = 1 << 10, 188 Arm_Cpuid = 1 << 11, 189 Arm_Asimdrdm = 1 << 12, 190 Arm_Jscvt = 1 << 13, 191 Arm_Fcma = 1 << 14, 192 Arm_Lrcpc = 1 << 15, 193 Arm_Dcpop = 1 << 16, 194 Arm_Sha3 = 1 << 17, 195 Arm_Sm3 = 1 << 18, 196 Arm_Sm4 = 1 << 19, 197 Arm_Asimddp = 1 << 20, 198 Arm_Sha512 = 1 << 21, 199 Arm_Sve = 1 << 22, 200 Arm_Asimdfhm = 1 << 23, 201 Arm_Dit = 1 << 24, 202 Arm_Uscat = 1 << 25, 203 Arm_Ilrcpc = 1 << 26, 204 Arm_Flagm = 1 << 27 205 }; 206 207 uint32_t hwcap = 0; 208 209 ThreadContext *tc = system->getThreadContext(contextIds[0]); 210 211 const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1); 212 213 hwcap |= (pf_r0.fp == 0) ? Arm_Fp : 0; 214 hwcap |= (pf_r0.fp == 1) ? Arm_Fphp | Arm_Fp : 0; 215 hwcap |= (pf_r0.advsimd == 0) ? Arm_Asimd : 0; 216 hwcap |= (pf_r0.advsimd == 1) ? Arm_Asimdhp | Arm_Asimd : 0; 217 hwcap |= (pf_r0.sve >= 1) ? Arm_Sve : 0; 218 hwcap |= (pf_r0.dit >= 1) ? Arm_Dit : 0; 219 220 const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1); 221 222 hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0; 223 hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0; 224 hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0; 225 hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0; 226 hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0; 227 hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0; 228 hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0; 229 hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0; 230 hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0; 231 hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0; 232 hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0; 233 hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0; 234 hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0; 235 hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0; 236 237 const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1); 238 239 hwcap |= (isa_r1.dpb >= 1) ? Arm_Dcpop : 0; 240 hwcap |= (isa_r1.jscvt >= 1) ? Arm_Jscvt : 0; 241 hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0; 242 hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0; 243 hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0; 244 245 const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1); 246 247 hwcap |= (mm_fr2.at >= 1) ? Arm_Uscat : 0; 248 249 return hwcap; 250} 251 252template <class IntType> 253void 254ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) 255{ 256 int intSize = sizeof(IntType); 257 258 typedef AuxVector<IntType> auxv_t; 259 std::vector<auxv_t> auxv; 260 261 string filename; 262 if (argv.size() < 1) 263 filename = ""; 264 else 265 filename = argv[0]; 266 267 //We want 16 byte alignment 268 uint64_t align = 16; 269 270 // Patch the ld_bias for dynamic executables. 271 updateBias(); 272 273 // load object file into target memory 274 objFile->loadSections(initVirtMem); 275 276 //Setup the auxilliary vectors. These will already have endian conversion. 277 //Auxilliary vectors are loaded only for elf formatted executables. 278 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 279 if (elfObject) { 280 281 if (objFile->getOpSys() == ObjectFile::Linux) { 282 IntType features = armHwcap<IntType>(); 283 284 //Bits which describe the system hardware capabilities 285 //XXX Figure out what these should be 286 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 287 //Frequency at which times() increments 288 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 289 //Whether to enable "secure mode" in the executable 290 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 291 // Pointer to 16 bytes of random data 292 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 293 //The filename of the program 294 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 295 //The string "v71" -- ARM v7 architecture 296 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 297 } 298 299 //The system page size 300 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes)); 301 // For statically linked executables, this is the virtual address of the 302 // program header tables if they appear in the executable image 303 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 304 // This is the size of a program header entry from the elf file. 305 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 306 // This is the number of program headers from the original elf file. 307 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 308 // This is the base address of the ELF interpreter; it should be 309 // zero for static executables or contain the base address for 310 // dynamic executables. 311 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 312 //XXX Figure out what this should be. 313 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 314 //The entry point to the program 315 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 316 //Different user and group IDs 317 auxv.push_back(auxv_t(M5_AT_UID, uid())); 318 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 319 auxv.push_back(auxv_t(M5_AT_GID, gid())); 320 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 321 } 322 323 //Figure out how big the initial stack nedes to be 324 325 // A sentry NULL void pointer at the top of the stack. 326 int sentry_size = intSize; 327 328 string platform = "v71"; 329 int platform_size = platform.size() + 1; 330 331 // Bytes for AT_RANDOM above, we'll just keep them 0 332 int aux_random_size = 16; // as per the specification 333 334 // The aux vectors are put on the stack in two groups. The first group are 335 // the vectors that are generated as the elf is loaded. The second group 336 // are the ones that were computed ahead of time and include the platform 337 // string. 338 int aux_data_size = filename.size() + 1; 339 340 int env_data_size = 0; 341 for (int i = 0; i < envp.size(); ++i) { 342 env_data_size += envp[i].size() + 1; 343 } 344 int arg_data_size = 0; 345 for (int i = 0; i < argv.size(); ++i) { 346 arg_data_size += argv[i].size() + 1; 347 } 348 349 int info_block_size = 350 sentry_size + env_data_size + arg_data_size + 351 aux_data_size + platform_size + aux_random_size; 352 353 //Each auxilliary vector is two 4 byte words 354 int aux_array_size = intSize * 2 * (auxv.size() + 1); 355 356 int envp_array_size = intSize * (envp.size() + 1); 357 int argv_array_size = intSize * (argv.size() + 1); 358 359 int argc_size = intSize; 360 361 //Figure out the size of the contents of the actual initial frame 362 int frame_size = 363 info_block_size + 364 aux_array_size + 365 envp_array_size + 366 argv_array_size + 367 argc_size; 368 369 //There needs to be padding after the auxiliary vector data so that the 370 //very bottom of the stack is aligned properly. 371 int partial_size = frame_size; 372 int aligned_partial_size = roundUp(partial_size, align); 373 int aux_padding = aligned_partial_size - partial_size; 374 375 int space_needed = frame_size + aux_padding; 376 377 memState->setStackMin(memState->getStackBase() - space_needed); 378 memState->setStackMin(roundDown(memState->getStackMin(), align)); 379 memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 380 381 // map memory 382 allocateMem(roundDown(memState->getStackMin(), pageSize), 383 roundUp(memState->getStackSize(), pageSize)); 384 385 // map out initial stack contents 386 IntType sentry_base = memState->getStackBase() - sentry_size; 387 IntType aux_data_base = sentry_base - aux_data_size; 388 IntType env_data_base = aux_data_base - env_data_size; 389 IntType arg_data_base = env_data_base - arg_data_size; 390 IntType platform_base = arg_data_base - platform_size; 391 IntType aux_random_base = platform_base - aux_random_size; 392 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding; 393 IntType envp_array_base = auxv_array_base - envp_array_size; 394 IntType argv_array_base = envp_array_base - argv_array_size; 395 IntType argc_base = argv_array_base - argc_size; 396 397 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 398 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 399 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 400 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 401 DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 402 DPRINTF(Stack, "0x%x - platform base\n", platform_base); 403 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 404 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 405 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 406 DPRINTF(Stack, "0x%x - argc \n", argc_base); 407 DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin()); 408 409 // write contents to stack 410 411 // figure out argc 412 IntType argc = argv.size(); 413 IntType guestArgc = ArmISA::htog(argc); 414 415 //Write out the sentry void * 416 IntType sentry_NULL = 0; 417 initVirtMem.writeBlob(sentry_base, 418 (uint8_t*)&sentry_NULL, sentry_size); 419 420 //Fix up the aux vectors which point to other data 421 for (int i = auxv.size() - 1; i >= 0; i--) { 422 if (auxv[i].getHostAuxType() == M5_AT_PLATFORM) { 423 auxv[i].setAuxVal(platform_base); 424 initVirtMem.writeString(platform_base, platform.c_str()); 425 } else if (auxv[i].getHostAuxType() == M5_AT_EXECFN) { 426 auxv[i].setAuxVal(aux_data_base); 427 initVirtMem.writeString(aux_data_base, filename.c_str()); 428 } else if (auxv[i].getHostAuxType() == M5_AT_RANDOM) { 429 auxv[i].setAuxVal(aux_random_base); 430 // Just leave the value 0, we don't want randomness 431 } 432 } 433 434 //Copy the aux stuff 435 for (int x = 0; x < auxv.size(); x++) { 436 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 437 (uint8_t*)&(auxv[x].getAuxType()), 438 intSize); 439 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 440 (uint8_t*)&(auxv[x].getAuxVal()), 441 intSize); 442 } 443 //Write out the terminating zeroed auxilliary vector 444 const uint64_t zero = 0; 445 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 446 (uint8_t*)&zero, 2 * intSize); 447 448 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 449 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 450 451 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 452 453 ThreadContext *tc = system->getThreadContext(contextIds[0]); 454 //Set the stack pointer register 455 tc->setIntReg(spIndex, memState->getStackMin()); 456 //A pointer to a function to run when the program exits. We'll set this 457 //to zero explicitly to make sure this isn't used. 458 tc->setIntReg(ArgumentReg0, 0); 459 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 460 if (argv.size() > 0) { 461 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 462 argv[argv.size() - 1].size() - 1); 463 } else { 464 tc->setIntReg(ArgumentReg1, 0); 465 } 466 if (envp.size() > 0) { 467 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 468 envp[envp.size() - 1].size() - 1); 469 } else { 470 tc->setIntReg(ArgumentReg2, 0); 471 } 472 473 PCState pc; 474 pc.thumb(arch == ObjectFile::Thumb); 475 pc.nextThumb(pc.thumb()); 476 pc.aarch64(arch == ObjectFile::Arm64); 477 pc.nextAArch64(pc.aarch64()); 478 pc.set(getStartPC() & ~mask(1)); 479 tc->pcState(pc); 480 481 //Align the "stackMin" to a page boundary. 482 memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 483} 484 485ArmISA::IntReg 486ArmProcess32::getSyscallArg(ThreadContext *tc, int &i) 487{ 488 assert(i < 6); 489 return tc->readIntReg(ArgumentReg0 + i++); 490} 491 492ArmISA::IntReg 493ArmProcess64::getSyscallArg(ThreadContext *tc, int &i) 494{ 495 assert(i < 8); 496 return tc->readIntReg(ArgumentReg0 + i++); 497} 498 499ArmISA::IntReg 500ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) 501{ 502 assert(width == 32 || width == 64); 503 if (width == 32) 504 return getSyscallArg(tc, i); 505 506 // 64 bit arguments are passed starting in an even register 507 if (i % 2 != 0) 508 i++; 509 510 // Registers r0-r6 can be used 511 assert(i < 5); 512 uint64_t val; 513 val = tc->readIntReg(ArgumentReg0 + i++); 514 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 515 return val; 516} 517 518ArmISA::IntReg 519ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) 520{ 521 return getSyscallArg(tc, i); 522} 523 524 525void 526ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 527{ 528 assert(i < 6); 529 tc->setIntReg(ArgumentReg0 + i, val); 530} 531 532void 533ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 534{ 535 assert(i < 8); 536 tc->setIntReg(ArgumentReg0 + i, val); 537} 538 539void 540ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 541{ 542 543 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 544 // Decode return value 545 if (sysret.encodedValue() >= 0) 546 // FreeBSD checks the carry bit to determine if syscall is succeeded 547 tc->setCCReg(CCREG_C, 0); 548 else { 549 sysret = -sysret.encodedValue(); 550 } 551 } 552 553 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 554} 555 556void 557ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 558{ 559 560 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 561 // Decode return value 562 if (sysret.encodedValue() >= 0) 563 // FreeBSD checks the carry bit to determine if syscall is succeeded 564 tc->setCCReg(CCREG_C, 0); 565 else { 566 sysret = -sysret.encodedValue(); 567 } 568 } 569 570 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 571} 572