process.cc revision 13121:4741df518ab8
1/* 2 * Copyright (c) 2010, 2012, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 * Ali Saidi 42 */ 43 44#include "arch/arm/process.hh" 45 46#include "arch/arm/isa_traits.hh" 47#include "arch/arm/types.hh" 48#include "base/loader/elf_object.hh" 49#include "base/loader/object_file.hh" 50#include "base/logging.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Stack.hh" 53#include "mem/page_table.hh" 54#include "params/Process.hh" 55#include "sim/aux_vector.hh" 56#include "sim/byteswap.hh" 57#include "sim/process_impl.hh" 58#include "sim/syscall_return.hh" 59#include "sim/system.hh" 60 61using namespace std; 62using namespace ArmISA; 63 64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile, 65 ObjectFile::Arch _arch) 66 : Process(params, 67 new EmulationPageTable(params->name, params->pid, PageBytes), 68 objFile), 69 arch(_arch) 70{ 71 fatal_if(params->useArchPT, "Arch page tables not implemented."); 72} 73 74ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, 75 ObjectFile::Arch _arch) 76 : ArmProcess(params, objFile, _arch) 77{ 78 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 79 objFile->bssSize(), PageBytes); 80 Addr stack_base = 0xbf000000L; 81 Addr max_stack_size = 8 * 1024 * 1024; 82 Addr next_thread_stack_base = stack_base - max_stack_size; 83 Addr mmap_end = 0x40000000L; 84 85 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 86 next_thread_stack_base, mmap_end); 87} 88 89ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile, 90 ObjectFile::Arch _arch) 91 : ArmProcess(params, objFile, _arch) 92{ 93 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 94 objFile->bssSize(), PageBytes); 95 Addr stack_base = 0x7fffff0000L; 96 Addr max_stack_size = 8 * 1024 * 1024; 97 Addr next_thread_stack_base = stack_base - max_stack_size; 98 Addr mmap_end = 0x4000000000L; 99 100 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 101 next_thread_stack_base, mmap_end); 102} 103 104void 105ArmProcess32::initState() 106{ 107 Process::initState(); 108 argsInit<uint32_t>(PageBytes, INTREG_SP); 109 for (int i = 0; i < contextIds.size(); i++) { 110 ThreadContext * tc = system->getThreadContext(contextIds[i]); 111 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 112 // Enable the floating point coprocessors. 113 cpacr.cp10 = 0x3; 114 cpacr.cp11 = 0x3; 115 tc->setMiscReg(MISCREG_CPACR, cpacr); 116 // Generically enable floating point support. 117 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 118 fpexc.en = 1; 119 tc->setMiscReg(MISCREG_FPEXC, fpexc); 120 } 121} 122 123void 124ArmProcess64::initState() 125{ 126 Process::initState(); 127 argsInit<uint64_t>(PageBytes, INTREG_SP0); 128 for (int i = 0; i < contextIds.size(); i++) { 129 ThreadContext * tc = system->getThreadContext(contextIds[i]); 130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 131 cpsr.mode = MODE_EL0T; 132 tc->setMiscReg(MISCREG_CPSR, cpsr); 133 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 134 // Enable the floating point coprocessors. 135 cpacr.cp10 = 0x3; 136 cpacr.cp11 = 0x3; 137 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr); 138 // Generically enable floating point support. 139 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 140 fpexc.en = 1; 141 tc->setMiscReg(MISCREG_FPEXC, fpexc); 142 } 143} 144 145uint32_t 146ArmProcess32::armHwcapImpl() const 147{ 148 enum ArmCpuFeature { 149 Arm_Swp = 1 << 0, 150 Arm_Half = 1 << 1, 151 Arm_Thumb = 1 << 2, 152 Arm_26Bit = 1 << 3, 153 Arm_FastMult = 1 << 4, 154 Arm_Fpa = 1 << 5, 155 Arm_Vfp = 1 << 6, 156 Arm_Edsp = 1 << 7, 157 Arm_Java = 1 << 8, 158 Arm_Iwmmxt = 1 << 9, 159 Arm_Crunch = 1 << 10, 160 Arm_ThumbEE = 1 << 11, 161 Arm_Neon = 1 << 12, 162 Arm_Vfpv3 = 1 << 13, 163 Arm_Vfpv3d16 = 1 << 14 164 }; 165 166 return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult | 167 Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon | 168 Arm_Vfpv3 | Arm_Vfpv3d16; 169} 170 171uint32_t 172ArmProcess64::armHwcapImpl() const 173{ 174 // In order to know what these flags mean, please refer to Linux 175 // /Documentation/arm64/elf_hwcaps.txt text file. 176 enum ArmCpuFeature { 177 Arm_Fp = 1 << 0, 178 Arm_Asimd = 1 << 1, 179 Arm_Evtstrm = 1 << 2, 180 Arm_Aes = 1 << 3, 181 Arm_Pmull = 1 << 4, 182 Arm_Sha1 = 1 << 5, 183 Arm_Sha2 = 1 << 6, 184 Arm_Crc32 = 1 << 7, 185 Arm_Atomics = 1 << 8, 186 Arm_Fphp = 1 << 9, 187 Arm_Asimdhp = 1 << 10, 188 Arm_Cpuid = 1 << 11, 189 Arm_Asimdrdm = 1 << 12, 190 Arm_Jscvt = 1 << 13, 191 Arm_Fcma = 1 << 14, 192 Arm_Lrcpc = 1 << 15, 193 Arm_Dcpop = 1 << 16, 194 Arm_Sha3 = 1 << 17, 195 Arm_Sm3 = 1 << 18, 196 Arm_Sm4 = 1 << 19, 197 Arm_Asimddp = 1 << 20, 198 Arm_Sha512 = 1 << 21, 199 Arm_Sve = 1 << 22, 200 Arm_Asimdfhm = 1 << 23, 201 Arm_Dit = 1 << 24, 202 Arm_Uscat = 1 << 25, 203 Arm_Ilrcpc = 1 << 26, 204 Arm_Flagm = 1 << 27 205 }; 206 207 return Arm_Fp | Arm_Asimd | Arm_Evtstrm | Arm_Crc32; 208} 209 210template <class IntType> 211void 212ArmProcess::argsInit(int pageSize, IntRegIndex spIndex) 213{ 214 int intSize = sizeof(IntType); 215 216 typedef AuxVector<IntType> auxv_t; 217 std::vector<auxv_t> auxv; 218 219 string filename; 220 if (argv.size() < 1) 221 filename = ""; 222 else 223 filename = argv[0]; 224 225 //We want 16 byte alignment 226 uint64_t align = 16; 227 228 // Patch the ld_bias for dynamic executables. 229 updateBias(); 230 231 // load object file into target memory 232 objFile->loadSections(initVirtMem); 233 234 //Setup the auxilliary vectors. These will already have endian conversion. 235 //Auxilliary vectors are loaded only for elf formatted executables. 236 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 237 if (elfObject) { 238 239 if (objFile->getOpSys() == ObjectFile::Linux) { 240 IntType features = armHwcap<IntType>(); 241 242 //Bits which describe the system hardware capabilities 243 //XXX Figure out what these should be 244 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 245 //Frequency at which times() increments 246 auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 247 //Whether to enable "secure mode" in the executable 248 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 249 // Pointer to 16 bytes of random data 250 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 251 //The filename of the program 252 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 253 //The string "v71" -- ARM v7 architecture 254 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 255 } 256 257 //The system page size 258 auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes)); 259 // For statically linked executables, this is the virtual address of the 260 // program header tables if they appear in the executable image 261 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 262 // This is the size of a program header entry from the elf file. 263 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 264 // This is the number of program headers from the original elf file. 265 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 266 // This is the base address of the ELF interpreter; it should be 267 // zero for static executables or contain the base address for 268 // dynamic executables. 269 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 270 //XXX Figure out what this should be. 271 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 272 //The entry point to the program 273 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 274 //Different user and group IDs 275 auxv.push_back(auxv_t(M5_AT_UID, uid())); 276 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 277 auxv.push_back(auxv_t(M5_AT_GID, gid())); 278 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 279 } 280 281 //Figure out how big the initial stack nedes to be 282 283 // A sentry NULL void pointer at the top of the stack. 284 int sentry_size = intSize; 285 286 string platform = "v71"; 287 int platform_size = platform.size() + 1; 288 289 // Bytes for AT_RANDOM above, we'll just keep them 0 290 int aux_random_size = 16; // as per the specification 291 292 // The aux vectors are put on the stack in two groups. The first group are 293 // the vectors that are generated as the elf is loaded. The second group 294 // are the ones that were computed ahead of time and include the platform 295 // string. 296 int aux_data_size = filename.size() + 1; 297 298 int env_data_size = 0; 299 for (int i = 0; i < envp.size(); ++i) { 300 env_data_size += envp[i].size() + 1; 301 } 302 int arg_data_size = 0; 303 for (int i = 0; i < argv.size(); ++i) { 304 arg_data_size += argv[i].size() + 1; 305 } 306 307 int info_block_size = 308 sentry_size + env_data_size + arg_data_size + 309 aux_data_size + platform_size + aux_random_size; 310 311 //Each auxilliary vector is two 4 byte words 312 int aux_array_size = intSize * 2 * (auxv.size() + 1); 313 314 int envp_array_size = intSize * (envp.size() + 1); 315 int argv_array_size = intSize * (argv.size() + 1); 316 317 int argc_size = intSize; 318 319 //Figure out the size of the contents of the actual initial frame 320 int frame_size = 321 info_block_size + 322 aux_array_size + 323 envp_array_size + 324 argv_array_size + 325 argc_size; 326 327 //There needs to be padding after the auxiliary vector data so that the 328 //very bottom of the stack is aligned properly. 329 int partial_size = frame_size; 330 int aligned_partial_size = roundUp(partial_size, align); 331 int aux_padding = aligned_partial_size - partial_size; 332 333 int space_needed = frame_size + aux_padding; 334 335 memState->setStackMin(memState->getStackBase() - space_needed); 336 memState->setStackMin(roundDown(memState->getStackMin(), align)); 337 memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 338 339 // map memory 340 allocateMem(roundDown(memState->getStackMin(), pageSize), 341 roundUp(memState->getStackSize(), pageSize)); 342 343 // map out initial stack contents 344 IntType sentry_base = memState->getStackBase() - sentry_size; 345 IntType aux_data_base = sentry_base - aux_data_size; 346 IntType env_data_base = aux_data_base - env_data_size; 347 IntType arg_data_base = env_data_base - arg_data_size; 348 IntType platform_base = arg_data_base - platform_size; 349 IntType aux_random_base = platform_base - aux_random_size; 350 IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding; 351 IntType envp_array_base = auxv_array_base - envp_array_size; 352 IntType argv_array_base = envp_array_base - argv_array_size; 353 IntType argc_base = argv_array_base - argc_size; 354 355 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 356 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 357 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 358 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 359 DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 360 DPRINTF(Stack, "0x%x - platform base\n", platform_base); 361 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 362 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 363 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 364 DPRINTF(Stack, "0x%x - argc \n", argc_base); 365 DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin()); 366 367 // write contents to stack 368 369 // figure out argc 370 IntType argc = argv.size(); 371 IntType guestArgc = ArmISA::htog(argc); 372 373 //Write out the sentry void * 374 IntType sentry_NULL = 0; 375 initVirtMem.writeBlob(sentry_base, 376 (uint8_t*)&sentry_NULL, sentry_size); 377 378 //Fix up the aux vectors which point to other data 379 for (int i = auxv.size() - 1; i >= 0; i--) { 380 if (auxv[i].getHostAuxType() == M5_AT_PLATFORM) { 381 auxv[i].setAuxVal(platform_base); 382 initVirtMem.writeString(platform_base, platform.c_str()); 383 } else if (auxv[i].getHostAuxType() == M5_AT_EXECFN) { 384 auxv[i].setAuxVal(aux_data_base); 385 initVirtMem.writeString(aux_data_base, filename.c_str()); 386 } else if (auxv[i].getHostAuxType() == M5_AT_RANDOM) { 387 auxv[i].setAuxVal(aux_random_base); 388 // Just leave the value 0, we don't want randomness 389 } 390 } 391 392 //Copy the aux stuff 393 for (int x = 0; x < auxv.size(); x++) { 394 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 395 (uint8_t*)&(auxv[x].getAuxType()), 396 intSize); 397 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 398 (uint8_t*)&(auxv[x].getAuxVal()), 399 intSize); 400 } 401 //Write out the terminating zeroed auxilliary vector 402 const uint64_t zero = 0; 403 initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 404 (uint8_t*)&zero, 2 * intSize); 405 406 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 407 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 408 409 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 410 411 ThreadContext *tc = system->getThreadContext(contextIds[0]); 412 //Set the stack pointer register 413 tc->setIntReg(spIndex, memState->getStackMin()); 414 //A pointer to a function to run when the program exits. We'll set this 415 //to zero explicitly to make sure this isn't used. 416 tc->setIntReg(ArgumentReg0, 0); 417 //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 418 if (argv.size() > 0) { 419 tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 420 argv[argv.size() - 1].size() - 1); 421 } else { 422 tc->setIntReg(ArgumentReg1, 0); 423 } 424 if (envp.size() > 0) { 425 tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 426 envp[envp.size() - 1].size() - 1); 427 } else { 428 tc->setIntReg(ArgumentReg2, 0); 429 } 430 431 PCState pc; 432 pc.thumb(arch == ObjectFile::Thumb); 433 pc.nextThumb(pc.thumb()); 434 pc.aarch64(arch == ObjectFile::Arm64); 435 pc.nextAArch64(pc.aarch64()); 436 pc.set(getStartPC() & ~mask(1)); 437 tc->pcState(pc); 438 439 //Align the "stackMin" to a page boundary. 440 memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 441} 442 443ArmISA::IntReg 444ArmProcess32::getSyscallArg(ThreadContext *tc, int &i) 445{ 446 assert(i < 6); 447 return tc->readIntReg(ArgumentReg0 + i++); 448} 449 450ArmISA::IntReg 451ArmProcess64::getSyscallArg(ThreadContext *tc, int &i) 452{ 453 assert(i < 8); 454 return tc->readIntReg(ArgumentReg0 + i++); 455} 456 457ArmISA::IntReg 458ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) 459{ 460 assert(width == 32 || width == 64); 461 if (width == 32) 462 return getSyscallArg(tc, i); 463 464 // 64 bit arguments are passed starting in an even register 465 if (i % 2 != 0) 466 i++; 467 468 // Registers r0-r6 can be used 469 assert(i < 5); 470 uint64_t val; 471 val = tc->readIntReg(ArgumentReg0 + i++); 472 val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 473 return val; 474} 475 476ArmISA::IntReg 477ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) 478{ 479 return getSyscallArg(tc, i); 480} 481 482 483void 484ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 485{ 486 assert(i < 6); 487 tc->setIntReg(ArgumentReg0 + i, val); 488} 489 490void 491ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 492{ 493 assert(i < 8); 494 tc->setIntReg(ArgumentReg0 + i, val); 495} 496 497void 498ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 499{ 500 501 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 502 // Decode return value 503 if (sysret.encodedValue() >= 0) 504 // FreeBSD checks the carry bit to determine if syscall is succeeded 505 tc->setCCReg(CCREG_C, 0); 506 else { 507 sysret = -sysret.encodedValue(); 508 } 509 } 510 511 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 512} 513 514void 515ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 516{ 517 518 if (objFile->getOpSys() == ObjectFile::FreeBSD) { 519 // Decode return value 520 if (sysret.encodedValue() >= 0) 521 // FreeBSD checks the carry bit to determine if syscall is succeeded 522 tc->setCCReg(CCREG_C, 0); 523 else { 524 sysret = -sysret.encodedValue(); 525 } 526 } 527 528 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 529} 530