process.cc revision 13121
16019Shines@cs.fsu.edu/* 213121Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012, 2018 ARM Limited 37414SAli.Saidi@ARM.com * All rights reserved 47414SAli.Saidi@ARM.com * 57414SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67414SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77414SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87414SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97414SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107414SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117414SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127414SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137414SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Stephen Hines 417414SAli.Saidi@ARM.com * Ali Saidi 426019Shines@cs.fsu.edu */ 436019Shines@cs.fsu.edu 4411793Sbrandon.potter@amd.com#include "arch/arm/process.hh" 4511793Sbrandon.potter@amd.com 466019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh" 476019Shines@cs.fsu.edu#include "arch/arm/types.hh" 486019Shines@cs.fsu.edu#include "base/loader/elf_object.hh" 496019Shines@cs.fsu.edu#include "base/loader/object_file.hh" 5012334Sgabeblack@google.com#include "base/logging.hh" 516019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 528232Snate@binkert.org#include "debug/Stack.hh" 536019Shines@cs.fsu.edu#include "mem/page_table.hh" 5412431Sgabeblack@google.com#include "params/Process.hh" 5511854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 567678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 576019Shines@cs.fsu.edu#include "sim/process_impl.hh" 5811800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 596019Shines@cs.fsu.edu#include "sim/system.hh" 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.eduusing namespace std; 626019Shines@cs.fsu.eduusing namespace ArmISA; 636019Shines@cs.fsu.edu 6411851Sbrandon.potter@amd.comArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile, 6511851Sbrandon.potter@amd.com ObjectFile::Arch _arch) 6612448Sgabeblack@google.com : Process(params, 6712448Sgabeblack@google.com new EmulationPageTable(params->name, params->pid, PageBytes), 6812432Sgabeblack@google.com objFile), 6912448Sgabeblack@google.com arch(_arch) 706019Shines@cs.fsu.edu{ 7112441Sgabeblack@google.com fatal_if(params->useArchPT, "Arch page tables not implemented."); 7210037SARM gem5 Developers} 7310037SARM gem5 Developers 7411851Sbrandon.potter@amd.comArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile, 7511851Sbrandon.potter@amd.com ObjectFile::Arch _arch) 7611851Sbrandon.potter@amd.com : ArmProcess(params, objFile, _arch) 7710037SARM gem5 Developers{ 7811905SBrandon.Potter@amd.com Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 7911905SBrandon.Potter@amd.com objFile->bssSize(), PageBytes); 8011905SBrandon.Potter@amd.com Addr stack_base = 0xbf000000L; 8111905SBrandon.Potter@amd.com Addr max_stack_size = 8 * 1024 * 1024; 8211905SBrandon.Potter@amd.com Addr next_thread_stack_base = stack_base - max_stack_size; 8311905SBrandon.Potter@amd.com Addr mmap_end = 0x40000000L; 846019Shines@cs.fsu.edu 8511905SBrandon.Potter@amd.com memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 8611905SBrandon.Potter@amd.com next_thread_stack_base, mmap_end); 876019Shines@cs.fsu.edu} 886019Shines@cs.fsu.edu 8911851Sbrandon.potter@amd.comArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile, 9011851Sbrandon.potter@amd.com ObjectFile::Arch _arch) 9111851Sbrandon.potter@amd.com : ArmProcess(params, objFile, _arch) 9210037SARM gem5 Developers{ 9311905SBrandon.Potter@amd.com Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 9411905SBrandon.Potter@amd.com objFile->bssSize(), PageBytes); 9511905SBrandon.Potter@amd.com Addr stack_base = 0x7fffff0000L; 9611905SBrandon.Potter@amd.com Addr max_stack_size = 8 * 1024 * 1024; 9711905SBrandon.Potter@amd.com Addr next_thread_stack_base = stack_base - max_stack_size; 9811905SBrandon.Potter@amd.com Addr mmap_end = 0x4000000000L; 9910037SARM gem5 Developers 10011905SBrandon.Potter@amd.com memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 10111905SBrandon.Potter@amd.com next_thread_stack_base, mmap_end); 10210037SARM gem5 Developers} 10310037SARM gem5 Developers 1046019Shines@cs.fsu.eduvoid 10511851Sbrandon.potter@amd.comArmProcess32::initState() 1066019Shines@cs.fsu.edu{ 10711851Sbrandon.potter@amd.com Process::initState(); 10810318Sandreas.hansson@arm.com argsInit<uint32_t>(PageBytes, INTREG_SP); 1097640Sgblack@eecs.umich.edu for (int i = 0; i < contextIds.size(); i++) { 1107640Sgblack@eecs.umich.edu ThreadContext * tc = system->getThreadContext(contextIds[i]); 1117640Sgblack@eecs.umich.edu CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); 1127640Sgblack@eecs.umich.edu // Enable the floating point coprocessors. 1137640Sgblack@eecs.umich.edu cpacr.cp10 = 0x3; 1147640Sgblack@eecs.umich.edu cpacr.cp11 = 0x3; 1157640Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPACR, cpacr); 1167640Sgblack@eecs.umich.edu // Generically enable floating point support. 1177640Sgblack@eecs.umich.edu FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 1187640Sgblack@eecs.umich.edu fpexc.en = 1; 1197640Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_FPEXC, fpexc); 1207640Sgblack@eecs.umich.edu } 1216019Shines@cs.fsu.edu} 1226019Shines@cs.fsu.edu 1236019Shines@cs.fsu.eduvoid 12411851Sbrandon.potter@amd.comArmProcess64::initState() 1256019Shines@cs.fsu.edu{ 12611851Sbrandon.potter@amd.com Process::initState(); 12710318Sandreas.hansson@arm.com argsInit<uint64_t>(PageBytes, INTREG_SP0); 12810037SARM gem5 Developers for (int i = 0; i < contextIds.size(); i++) { 12910037SARM gem5 Developers ThreadContext * tc = system->getThreadContext(contextIds[i]); 13010037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 13110037SARM gem5 Developers cpsr.mode = MODE_EL0T; 13210037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 13310037SARM gem5 Developers CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 13410037SARM gem5 Developers // Enable the floating point coprocessors. 13510037SARM gem5 Developers cpacr.cp10 = 0x3; 13610037SARM gem5 Developers cpacr.cp11 = 0x3; 13710037SARM gem5 Developers tc->setMiscReg(MISCREG_CPACR_EL1, cpacr); 13810037SARM gem5 Developers // Generically enable floating point support. 13910037SARM gem5 Developers FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); 14010037SARM gem5 Developers fpexc.en = 1; 14110037SARM gem5 Developers tc->setMiscReg(MISCREG_FPEXC, fpexc); 14210037SARM gem5 Developers } 14310037SARM gem5 Developers} 14410037SARM gem5 Developers 14513121Sgiacomo.travaglini@arm.comuint32_t 14613121Sgiacomo.travaglini@arm.comArmProcess32::armHwcapImpl() const 14713121Sgiacomo.travaglini@arm.com{ 14813121Sgiacomo.travaglini@arm.com enum ArmCpuFeature { 14913121Sgiacomo.travaglini@arm.com Arm_Swp = 1 << 0, 15013121Sgiacomo.travaglini@arm.com Arm_Half = 1 << 1, 15113121Sgiacomo.travaglini@arm.com Arm_Thumb = 1 << 2, 15213121Sgiacomo.travaglini@arm.com Arm_26Bit = 1 << 3, 15313121Sgiacomo.travaglini@arm.com Arm_FastMult = 1 << 4, 15413121Sgiacomo.travaglini@arm.com Arm_Fpa = 1 << 5, 15513121Sgiacomo.travaglini@arm.com Arm_Vfp = 1 << 6, 15613121Sgiacomo.travaglini@arm.com Arm_Edsp = 1 << 7, 15713121Sgiacomo.travaglini@arm.com Arm_Java = 1 << 8, 15813121Sgiacomo.travaglini@arm.com Arm_Iwmmxt = 1 << 9, 15913121Sgiacomo.travaglini@arm.com Arm_Crunch = 1 << 10, 16013121Sgiacomo.travaglini@arm.com Arm_ThumbEE = 1 << 11, 16113121Sgiacomo.travaglini@arm.com Arm_Neon = 1 << 12, 16213121Sgiacomo.travaglini@arm.com Arm_Vfpv3 = 1 << 13, 16313121Sgiacomo.travaglini@arm.com Arm_Vfpv3d16 = 1 << 14 16413121Sgiacomo.travaglini@arm.com }; 16513121Sgiacomo.travaglini@arm.com 16613121Sgiacomo.travaglini@arm.com return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult | 16713121Sgiacomo.travaglini@arm.com Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon | 16813121Sgiacomo.travaglini@arm.com Arm_Vfpv3 | Arm_Vfpv3d16; 16913121Sgiacomo.travaglini@arm.com} 17013121Sgiacomo.travaglini@arm.com 17113121Sgiacomo.travaglini@arm.comuint32_t 17213121Sgiacomo.travaglini@arm.comArmProcess64::armHwcapImpl() const 17313121Sgiacomo.travaglini@arm.com{ 17413121Sgiacomo.travaglini@arm.com // In order to know what these flags mean, please refer to Linux 17513121Sgiacomo.travaglini@arm.com // /Documentation/arm64/elf_hwcaps.txt text file. 17613121Sgiacomo.travaglini@arm.com enum ArmCpuFeature { 17713121Sgiacomo.travaglini@arm.com Arm_Fp = 1 << 0, 17813121Sgiacomo.travaglini@arm.com Arm_Asimd = 1 << 1, 17913121Sgiacomo.travaglini@arm.com Arm_Evtstrm = 1 << 2, 18013121Sgiacomo.travaglini@arm.com Arm_Aes = 1 << 3, 18113121Sgiacomo.travaglini@arm.com Arm_Pmull = 1 << 4, 18213121Sgiacomo.travaglini@arm.com Arm_Sha1 = 1 << 5, 18313121Sgiacomo.travaglini@arm.com Arm_Sha2 = 1 << 6, 18413121Sgiacomo.travaglini@arm.com Arm_Crc32 = 1 << 7, 18513121Sgiacomo.travaglini@arm.com Arm_Atomics = 1 << 8, 18613121Sgiacomo.travaglini@arm.com Arm_Fphp = 1 << 9, 18713121Sgiacomo.travaglini@arm.com Arm_Asimdhp = 1 << 10, 18813121Sgiacomo.travaglini@arm.com Arm_Cpuid = 1 << 11, 18913121Sgiacomo.travaglini@arm.com Arm_Asimdrdm = 1 << 12, 19013121Sgiacomo.travaglini@arm.com Arm_Jscvt = 1 << 13, 19113121Sgiacomo.travaglini@arm.com Arm_Fcma = 1 << 14, 19213121Sgiacomo.travaglini@arm.com Arm_Lrcpc = 1 << 15, 19313121Sgiacomo.travaglini@arm.com Arm_Dcpop = 1 << 16, 19413121Sgiacomo.travaglini@arm.com Arm_Sha3 = 1 << 17, 19513121Sgiacomo.travaglini@arm.com Arm_Sm3 = 1 << 18, 19613121Sgiacomo.travaglini@arm.com Arm_Sm4 = 1 << 19, 19713121Sgiacomo.travaglini@arm.com Arm_Asimddp = 1 << 20, 19813121Sgiacomo.travaglini@arm.com Arm_Sha512 = 1 << 21, 19913121Sgiacomo.travaglini@arm.com Arm_Sve = 1 << 22, 20013121Sgiacomo.travaglini@arm.com Arm_Asimdfhm = 1 << 23, 20113121Sgiacomo.travaglini@arm.com Arm_Dit = 1 << 24, 20213121Sgiacomo.travaglini@arm.com Arm_Uscat = 1 << 25, 20313121Sgiacomo.travaglini@arm.com Arm_Ilrcpc = 1 << 26, 20413121Sgiacomo.travaglini@arm.com Arm_Flagm = 1 << 27 20513121Sgiacomo.travaglini@arm.com }; 20613121Sgiacomo.travaglini@arm.com 20713121Sgiacomo.travaglini@arm.com return Arm_Fp | Arm_Asimd | Arm_Evtstrm | Arm_Crc32; 20813121Sgiacomo.travaglini@arm.com} 20913121Sgiacomo.travaglini@arm.com 21010037SARM gem5 Developerstemplate <class IntType> 21110037SARM gem5 Developersvoid 21211851Sbrandon.potter@amd.comArmProcess::argsInit(int pageSize, IntRegIndex spIndex) 21310037SARM gem5 Developers{ 21410037SARM gem5 Developers int intSize = sizeof(IntType); 21510037SARM gem5 Developers 21610037SARM gem5 Developers typedef AuxVector<IntType> auxv_t; 2176400Sgblack@eecs.umich.edu std::vector<auxv_t> auxv; 2186400Sgblack@eecs.umich.edu 2196400Sgblack@eecs.umich.edu string filename; 2206400Sgblack@eecs.umich.edu if (argv.size() < 1) 2216400Sgblack@eecs.umich.edu filename = ""; 2226400Sgblack@eecs.umich.edu else 2236400Sgblack@eecs.umich.edu filename = argv[0]; 2246400Sgblack@eecs.umich.edu 2256400Sgblack@eecs.umich.edu //We want 16 byte alignment 2266400Sgblack@eecs.umich.edu uint64_t align = 16; 2276400Sgblack@eecs.umich.edu 22811389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 22911389Sbrandon.potter@amd.com updateBias(); 23011389Sbrandon.potter@amd.com 2316019Shines@cs.fsu.edu // load object file into target memory 2326019Shines@cs.fsu.edu objFile->loadSections(initVirtMem); 2336019Shines@cs.fsu.edu 2346400Sgblack@eecs.umich.edu //Setup the auxilliary vectors. These will already have endian conversion. 2356400Sgblack@eecs.umich.edu //Auxilliary vectors are loaded only for elf formatted executables. 2366400Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2376400Sgblack@eecs.umich.edu if (elfObject) { 2386400Sgblack@eecs.umich.edu 23910810Sbr@bsdpad.com if (objFile->getOpSys() == ObjectFile::Linux) { 24013121Sgiacomo.travaglini@arm.com IntType features = armHwcap<IntType>(); 24110810Sbr@bsdpad.com 24210810Sbr@bsdpad.com //Bits which describe the system hardware capabilities 24310810Sbr@bsdpad.com //XXX Figure out what these should be 24410810Sbr@bsdpad.com auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 24510810Sbr@bsdpad.com //Frequency at which times() increments 24610810Sbr@bsdpad.com auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); 24710810Sbr@bsdpad.com //Whether to enable "secure mode" in the executable 24810810Sbr@bsdpad.com auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 24910810Sbr@bsdpad.com // Pointer to 16 bytes of random data 25010810Sbr@bsdpad.com auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 25110810Sbr@bsdpad.com //The filename of the program 25210810Sbr@bsdpad.com auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 25310810Sbr@bsdpad.com //The string "v71" -- ARM v7 architecture 25410810Sbr@bsdpad.com auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 25510810Sbr@bsdpad.com } 25610810Sbr@bsdpad.com 2576400Sgblack@eecs.umich.edu //The system page size 25810318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes)); 2596400Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2606400Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2616400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2626400Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2636400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 2646400Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 2656400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 26611389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 26711389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 26811389Sbrandon.potter@amd.com // dynamic executables. 26911389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 2706400Sgblack@eecs.umich.edu //XXX Figure out what this should be. 2716400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2726400Sgblack@eecs.umich.edu //The entry point to the program 2736400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2746400Sgblack@eecs.umich.edu //Different user and group IDs 2756400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 2766400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 2776400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 2786400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2796400Sgblack@eecs.umich.edu } 2806400Sgblack@eecs.umich.edu 2816400Sgblack@eecs.umich.edu //Figure out how big the initial stack nedes to be 2826400Sgblack@eecs.umich.edu 2836400Sgblack@eecs.umich.edu // A sentry NULL void pointer at the top of the stack. 2846400Sgblack@eecs.umich.edu int sentry_size = intSize; 2856400Sgblack@eecs.umich.edu 2867414SAli.Saidi@ARM.com string platform = "v71"; 2876400Sgblack@eecs.umich.edu int platform_size = platform.size() + 1; 2886400Sgblack@eecs.umich.edu 2897414SAli.Saidi@ARM.com // Bytes for AT_RANDOM above, we'll just keep them 0 2907414SAli.Saidi@ARM.com int aux_random_size = 16; // as per the specification 2917414SAli.Saidi@ARM.com 2926400Sgblack@eecs.umich.edu // The aux vectors are put on the stack in two groups. The first group are 2936400Sgblack@eecs.umich.edu // the vectors that are generated as the elf is loaded. The second group 2946400Sgblack@eecs.umich.edu // are the ones that were computed ahead of time and include the platform 2956400Sgblack@eecs.umich.edu // string. 2966400Sgblack@eecs.umich.edu int aux_data_size = filename.size() + 1; 2976400Sgblack@eecs.umich.edu 2986400Sgblack@eecs.umich.edu int env_data_size = 0; 2996400Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 3006400Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 3016400Sgblack@eecs.umich.edu } 3026019Shines@cs.fsu.edu int arg_data_size = 0; 3036019Shines@cs.fsu.edu for (int i = 0; i < argv.size(); ++i) { 3046019Shines@cs.fsu.edu arg_data_size += argv[i].size() + 1; 3056019Shines@cs.fsu.edu } 3066400Sgblack@eecs.umich.edu 3076400Sgblack@eecs.umich.edu int info_block_size = 3086400Sgblack@eecs.umich.edu sentry_size + env_data_size + arg_data_size + 3097414SAli.Saidi@ARM.com aux_data_size + platform_size + aux_random_size; 3106400Sgblack@eecs.umich.edu 3116400Sgblack@eecs.umich.edu //Each auxilliary vector is two 4 byte words 3126400Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 3136400Sgblack@eecs.umich.edu 3146400Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 3156400Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 3166400Sgblack@eecs.umich.edu 3176400Sgblack@eecs.umich.edu int argc_size = intSize; 3186400Sgblack@eecs.umich.edu 3196400Sgblack@eecs.umich.edu //Figure out the size of the contents of the actual initial frame 3206400Sgblack@eecs.umich.edu int frame_size = 3216400Sgblack@eecs.umich.edu info_block_size + 3226400Sgblack@eecs.umich.edu aux_array_size + 3236400Sgblack@eecs.umich.edu envp_array_size + 3246400Sgblack@eecs.umich.edu argv_array_size + 3256400Sgblack@eecs.umich.edu argc_size; 3266400Sgblack@eecs.umich.edu 3276400Sgblack@eecs.umich.edu //There needs to be padding after the auxiliary vector data so that the 3286400Sgblack@eecs.umich.edu //very bottom of the stack is aligned properly. 3296400Sgblack@eecs.umich.edu int partial_size = frame_size; 3306400Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(partial_size, align); 3316400Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - partial_size; 3326400Sgblack@eecs.umich.edu 3336400Sgblack@eecs.umich.edu int space_needed = frame_size + aux_padding; 3346400Sgblack@eecs.umich.edu 33511905SBrandon.Potter@amd.com memState->setStackMin(memState->getStackBase() - space_needed); 33611905SBrandon.Potter@amd.com memState->setStackMin(roundDown(memState->getStackMin(), align)); 33711905SBrandon.Potter@amd.com memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 3386400Sgblack@eecs.umich.edu 3396400Sgblack@eecs.umich.edu // map memory 34011905SBrandon.Potter@amd.com allocateMem(roundDown(memState->getStackMin(), pageSize), 34111905SBrandon.Potter@amd.com roundUp(memState->getStackSize(), pageSize)); 3426400Sgblack@eecs.umich.edu 3436400Sgblack@eecs.umich.edu // map out initial stack contents 34411905SBrandon.Potter@amd.com IntType sentry_base = memState->getStackBase() - sentry_size; 34510037SARM gem5 Developers IntType aux_data_base = sentry_base - aux_data_size; 34610037SARM gem5 Developers IntType env_data_base = aux_data_base - env_data_size; 34710037SARM gem5 Developers IntType arg_data_base = env_data_base - arg_data_size; 34810037SARM gem5 Developers IntType platform_base = arg_data_base - platform_size; 34910037SARM gem5 Developers IntType aux_random_base = platform_base - aux_random_size; 35010037SARM gem5 Developers IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding; 35110037SARM gem5 Developers IntType envp_array_base = auxv_array_base - envp_array_size; 35210037SARM gem5 Developers IntType argv_array_base = envp_array_base - argv_array_size; 35310037SARM gem5 Developers IntType argc_base = argv_array_base - argc_size; 3546400Sgblack@eecs.umich.edu 3556400Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3566400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 3576400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - env data\n", env_data_base); 3586400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 3597414SAli.Saidi@ARM.com DPRINTF(Stack, "0x%x - random data\n", aux_random_base); 3606400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - platform base\n", platform_base); 3616400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 3626400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 3636400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 3646400Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argc \n", argc_base); 36511905SBrandon.Potter@amd.com DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin()); 3666400Sgblack@eecs.umich.edu 3676400Sgblack@eecs.umich.edu // write contents to stack 3686400Sgblack@eecs.umich.edu 3696400Sgblack@eecs.umich.edu // figure out argc 37010037SARM gem5 Developers IntType argc = argv.size(); 37110037SARM gem5 Developers IntType guestArgc = ArmISA::htog(argc); 3726400Sgblack@eecs.umich.edu 3736400Sgblack@eecs.umich.edu //Write out the sentry void * 37410037SARM gem5 Developers IntType sentry_NULL = 0; 3758852Sandreas.hansson@arm.com initVirtMem.writeBlob(sentry_base, 3766400Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3776400Sgblack@eecs.umich.edu 3786400Sgblack@eecs.umich.edu //Fix up the aux vectors which point to other data 3796400Sgblack@eecs.umich.edu for (int i = auxv.size() - 1; i >= 0; i--) { 38013028Sbrandon.potter@amd.com if (auxv[i].getHostAuxType() == M5_AT_PLATFORM) { 38113028Sbrandon.potter@amd.com auxv[i].setAuxVal(platform_base); 3828852Sandreas.hansson@arm.com initVirtMem.writeString(platform_base, platform.c_str()); 38313028Sbrandon.potter@amd.com } else if (auxv[i].getHostAuxType() == M5_AT_EXECFN) { 38413028Sbrandon.potter@amd.com auxv[i].setAuxVal(aux_data_base); 3858852Sandreas.hansson@arm.com initVirtMem.writeString(aux_data_base, filename.c_str()); 38613028Sbrandon.potter@amd.com } else if (auxv[i].getHostAuxType() == M5_AT_RANDOM) { 38713028Sbrandon.potter@amd.com auxv[i].setAuxVal(aux_random_base); 3887414SAli.Saidi@ARM.com // Just leave the value 0, we don't want randomness 3896400Sgblack@eecs.umich.edu } 3906019Shines@cs.fsu.edu } 3916019Shines@cs.fsu.edu 3926400Sgblack@eecs.umich.edu //Copy the aux stuff 39310037SARM gem5 Developers for (int x = 0; x < auxv.size(); x++) { 3948852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 39513028Sbrandon.potter@amd.com (uint8_t*)&(auxv[x].getAuxType()), 39613028Sbrandon.potter@amd.com intSize); 3978852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 39813028Sbrandon.potter@amd.com (uint8_t*)&(auxv[x].getAuxVal()), 39913028Sbrandon.potter@amd.com intSize); 4006400Sgblack@eecs.umich.edu } 4016400Sgblack@eecs.umich.edu //Write out the terminating zeroed auxilliary vector 4026400Sgblack@eecs.umich.edu const uint64_t zero = 0; 4038852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(), 4046400Sgblack@eecs.umich.edu (uint8_t*)&zero, 2 * intSize); 4056019Shines@cs.fsu.edu 4066400Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 4076400Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 4086019Shines@cs.fsu.edu 4098852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 4106019Shines@cs.fsu.edu 4116020Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 4126400Sgblack@eecs.umich.edu //Set the stack pointer register 41311905SBrandon.Potter@amd.com tc->setIntReg(spIndex, memState->getStackMin()); 4146400Sgblack@eecs.umich.edu //A pointer to a function to run when the program exits. We'll set this 4156400Sgblack@eecs.umich.edu //to zero explicitly to make sure this isn't used. 4166400Sgblack@eecs.umich.edu tc->setIntReg(ArgumentReg0, 0); 4176400Sgblack@eecs.umich.edu //Set argument regs 1 and 2 to argv[0] and envp[0] respectively 4186400Sgblack@eecs.umich.edu if (argv.size() > 0) { 4196400Sgblack@eecs.umich.edu tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - 4206400Sgblack@eecs.umich.edu argv[argv.size() - 1].size() - 1); 4216400Sgblack@eecs.umich.edu } else { 4226400Sgblack@eecs.umich.edu tc->setIntReg(ArgumentReg1, 0); 4236400Sgblack@eecs.umich.edu } 4246400Sgblack@eecs.umich.edu if (envp.size() > 0) { 4256400Sgblack@eecs.umich.edu tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - 4266400Sgblack@eecs.umich.edu envp[envp.size() - 1].size() - 1); 4276400Sgblack@eecs.umich.edu } else { 4286400Sgblack@eecs.umich.edu tc->setIntReg(ArgumentReg2, 0); 4296400Sgblack@eecs.umich.edu } 4306019Shines@cs.fsu.edu 4317720Sgblack@eecs.umich.edu PCState pc; 4327720Sgblack@eecs.umich.edu pc.thumb(arch == ObjectFile::Thumb); 4337720Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 43410037SARM gem5 Developers pc.aarch64(arch == ObjectFile::Arm64); 43510037SARM gem5 Developers pc.nextAArch64(pc.aarch64()); 43611389Sbrandon.potter@amd.com pc.set(getStartPC() & ~mask(1)); 4377720Sgblack@eecs.umich.edu tc->pcState(pc); 4386400Sgblack@eecs.umich.edu 43911886Sbrandon.potter@amd.com //Align the "stackMin" to a page boundary. 44011905SBrandon.Potter@amd.com memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 4416019Shines@cs.fsu.edu} 4426019Shines@cs.fsu.edu 4436020Sgblack@eecs.umich.eduArmISA::IntReg 44411851Sbrandon.potter@amd.comArmProcess32::getSyscallArg(ThreadContext *tc, int &i) 4456020Sgblack@eecs.umich.edu{ 4467441SAli.Saidi@ARM.com assert(i < 6); 4476701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg0 + i++); 4486020Sgblack@eecs.umich.edu} 4496020Sgblack@eecs.umich.edu 45010037SARM gem5 DevelopersArmISA::IntReg 45111851Sbrandon.potter@amd.comArmProcess64::getSyscallArg(ThreadContext *tc, int &i) 45210037SARM gem5 Developers{ 45310037SARM gem5 Developers assert(i < 8); 45410037SARM gem5 Developers return tc->readIntReg(ArgumentReg0 + i++); 45510037SARM gem5 Developers} 45610037SARM gem5 Developers 45710037SARM gem5 DevelopersArmISA::IntReg 45811851Sbrandon.potter@amd.comArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width) 4597441SAli.Saidi@ARM.com{ 4607441SAli.Saidi@ARM.com assert(width == 32 || width == 64); 4617441SAli.Saidi@ARM.com if (width == 32) 4627441SAli.Saidi@ARM.com return getSyscallArg(tc, i); 4637441SAli.Saidi@ARM.com 4647441SAli.Saidi@ARM.com // 64 bit arguments are passed starting in an even register 4657441SAli.Saidi@ARM.com if (i % 2 != 0) 4667441SAli.Saidi@ARM.com i++; 4677441SAli.Saidi@ARM.com 4687441SAli.Saidi@ARM.com // Registers r0-r6 can be used 4697441SAli.Saidi@ARM.com assert(i < 5); 4707441SAli.Saidi@ARM.com uint64_t val; 4717441SAli.Saidi@ARM.com val = tc->readIntReg(ArgumentReg0 + i++); 4727441SAli.Saidi@ARM.com val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); 4737441SAli.Saidi@ARM.com return val; 4747441SAli.Saidi@ARM.com} 4757441SAli.Saidi@ARM.com 47610037SARM gem5 DevelopersArmISA::IntReg 47711851Sbrandon.potter@amd.comArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width) 47810037SARM gem5 Developers{ 47910037SARM gem5 Developers return getSyscallArg(tc, i); 48010037SARM gem5 Developers} 48110037SARM gem5 Developers 4827441SAli.Saidi@ARM.com 4836020Sgblack@eecs.umich.eduvoid 48411851Sbrandon.potter@amd.comArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 4856020Sgblack@eecs.umich.edu{ 48610037SARM gem5 Developers assert(i < 6); 4876020Sgblack@eecs.umich.edu tc->setIntReg(ArgumentReg0 + i, val); 4886020Sgblack@eecs.umich.edu} 4896020Sgblack@eecs.umich.edu 4906020Sgblack@eecs.umich.eduvoid 49111851Sbrandon.potter@amd.comArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) 49210037SARM gem5 Developers{ 49310037SARM gem5 Developers assert(i < 8); 49410037SARM gem5 Developers tc->setIntReg(ArgumentReg0 + i, val); 49510037SARM gem5 Developers} 49610037SARM gem5 Developers 49710037SARM gem5 Developersvoid 49811851Sbrandon.potter@amd.comArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 4996020Sgblack@eecs.umich.edu{ 50010810Sbr@bsdpad.com 50110810Sbr@bsdpad.com if (objFile->getOpSys() == ObjectFile::FreeBSD) { 50210810Sbr@bsdpad.com // Decode return value 50310810Sbr@bsdpad.com if (sysret.encodedValue() >= 0) 50410810Sbr@bsdpad.com // FreeBSD checks the carry bit to determine if syscall is succeeded 50510810Sbr@bsdpad.com tc->setCCReg(CCREG_C, 0); 50610810Sbr@bsdpad.com else { 50710810Sbr@bsdpad.com sysret = -sysret.encodedValue(); 50810810Sbr@bsdpad.com } 50910810Sbr@bsdpad.com } 51010810Sbr@bsdpad.com 51110223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 5126020Sgblack@eecs.umich.edu} 51310037SARM gem5 Developers 51410037SARM gem5 Developersvoid 51511851Sbrandon.potter@amd.comArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 51610037SARM gem5 Developers{ 51710810Sbr@bsdpad.com 51810810Sbr@bsdpad.com if (objFile->getOpSys() == ObjectFile::FreeBSD) { 51910810Sbr@bsdpad.com // Decode return value 52010810Sbr@bsdpad.com if (sysret.encodedValue() >= 0) 52110810Sbr@bsdpad.com // FreeBSD checks the carry bit to determine if syscall is succeeded 52210810Sbr@bsdpad.com tc->setCCReg(CCREG_C, 0); 52310810Sbr@bsdpad.com else { 52410810Sbr@bsdpad.com sysret = -sysret.encodedValue(); 52510810Sbr@bsdpad.com } 52610810Sbr@bsdpad.com } 52710810Sbr@bsdpad.com 52810223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 52910037SARM gem5 Developers} 530