nativetrace.cc revision 8303
14776SN/A/* 27414SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37414SAli.Saidi@ARM.com * All rights reserved 47414SAli.Saidi@ARM.com * 57414SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67414SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77414SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87414SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97414SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107414SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117414SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127414SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137414SAli.Saidi@ARM.com * 146365SN/A * Copyright (c) 2006 The Regents of The University of Michigan 154776SN/A * All rights reserved. 164776SN/A * 174776SN/A * Redistribution and use in source and binary forms, with or without 184776SN/A * modification, are permitted provided that the following conditions are 194776SN/A * met: redistributions of source code must retain the above copyright 204776SN/A * notice, this list of conditions and the following disclaimer; 214776SN/A * redistributions in binary form must reproduce the above copyright 224776SN/A * notice, this list of conditions and the following disclaimer in the 234776SN/A * documentation and/or other materials provided with the distribution; 244776SN/A * neither the name of the copyright holders nor the names of its 254776SN/A * contributors may be used to endorse or promote products derived from 264776SN/A * this software without specific prior written permission. 274776SN/A * 284776SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294776SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304776SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314776SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324776SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334776SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344776SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354776SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364776SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374776SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384776SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394776SN/A * 406365SN/A * Authors: Gabe Black 414776SN/A */ 424776SN/A 436397Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 446397Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 456397Sgblack@eecs.umich.edu#include "arch/arm/nativetrace.hh" 464776SN/A#include "cpu/thread_context.hh" 478232Snate@binkert.org#include "debug/ExecRegDelta.hh" 486397Sgblack@eecs.umich.edu#include "params/ArmNativeTrace.hh" 497678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 504776SN/A 514776SN/Anamespace Trace { 524776SN/A 536398Sgblack@eecs.umich.edu#if TRACING_ON 546397Sgblack@eecs.umich.edustatic const char *regNames[] = { 556397Sgblack@eecs.umich.edu "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 566397Sgblack@eecs.umich.edu "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 578271SAli.Saidi@ARM.com "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6", 588271SAli.Saidi@ARM.com "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", 598271SAli.Saidi@ARM.com "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", 608271SAli.Saidi@ARM.com "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", 618271SAli.Saidi@ARM.com "f31", "fpscr" 626365SN/A}; 636398Sgblack@eecs.umich.edu#endif 646398Sgblack@eecs.umich.edu 656398Sgblack@eecs.umich.eduvoid 666398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) 676398Sgblack@eecs.umich.edu{ 686398Sgblack@eecs.umich.edu oldState = state[current]; 696398Sgblack@eecs.umich.edu current = (current + 1) % 2; 706398Sgblack@eecs.umich.edu newState = state[current]; 716398Sgblack@eecs.umich.edu 726411Sgblack@eecs.umich.edu memcpy(newState, oldState, sizeof(state[0])); 736411Sgblack@eecs.umich.edu 748271SAli.Saidi@ARM.com uint64_t diffVector; 756411Sgblack@eecs.umich.edu parent->read(&diffVector, sizeof(diffVector)); 766411Sgblack@eecs.umich.edu diffVector = ArmISA::gtoh(diffVector); 776411Sgblack@eecs.umich.edu 786411Sgblack@eecs.umich.edu int changes = 0; 796398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 806411Sgblack@eecs.umich.edu if (diffVector & 0x1) { 816411Sgblack@eecs.umich.edu changed[i] = true; 826411Sgblack@eecs.umich.edu changes++; 836411Sgblack@eecs.umich.edu } else { 846411Sgblack@eecs.umich.edu changed[i] = false; 856411Sgblack@eecs.umich.edu } 866411Sgblack@eecs.umich.edu diffVector >>= 1; 876411Sgblack@eecs.umich.edu } 886411Sgblack@eecs.umich.edu 898271SAli.Saidi@ARM.com uint64_t values[changes]; 906411Sgblack@eecs.umich.edu parent->read(values, sizeof(values)); 916411Sgblack@eecs.umich.edu int pos = 0; 926411Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 936411Sgblack@eecs.umich.edu if (changed[i]) { 946411Sgblack@eecs.umich.edu newState[i] = ArmISA::gtoh(values[pos++]); 956411Sgblack@eecs.umich.edu changed[i] = (newState[i] != oldState[i]); 966411Sgblack@eecs.umich.edu } 976398Sgblack@eecs.umich.edu } 986398Sgblack@eecs.umich.edu} 996398Sgblack@eecs.umich.edu 1006398Sgblack@eecs.umich.eduvoid 1016398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 1026398Sgblack@eecs.umich.edu{ 1036398Sgblack@eecs.umich.edu oldState = state[current]; 1046398Sgblack@eecs.umich.edu current = (current + 1) % 2; 1056398Sgblack@eecs.umich.edu newState = state[current]; 1066398Sgblack@eecs.umich.edu 1076398Sgblack@eecs.umich.edu // Regular int regs 1086398Sgblack@eecs.umich.edu for (int i = 0; i < 15; i++) { 1096398Sgblack@eecs.umich.edu newState[i] = tc->readIntReg(i); 1106398Sgblack@eecs.umich.edu changed[i] = (oldState[i] != newState[i]); 1116398Sgblack@eecs.umich.edu } 1126398Sgblack@eecs.umich.edu 1136398Sgblack@eecs.umich.edu //R15, aliased with the PC 1147720Sgblack@eecs.umich.edu newState[STATE_PC] = tc->pcState().npc(); 1156398Sgblack@eecs.umich.edu changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); 1166398Sgblack@eecs.umich.edu 1176398Sgblack@eecs.umich.edu //CPSR 1188303SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1198303SAli.Saidi@ARM.com cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ); 1208303SAli.Saidi@ARM.com cpsr.c = tc->readIntReg(INTREG_CONDCODES_C); 1218303SAli.Saidi@ARM.com cpsr.v = tc->readIntReg(INTREG_CONDCODES_V); 1228303SAli.Saidi@ARM.com cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE); 1238303SAli.Saidi@ARM.com 1248303SAli.Saidi@ARM.com newState[STATE_CPSR] = cpsr; 1256398Sgblack@eecs.umich.edu changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); 1268271SAli.Saidi@ARM.com 1278271SAli.Saidi@ARM.com for (int i = 0; i < NumFloatArchRegs; i += 2) { 1288271SAli.Saidi@ARM.com newState[STATE_F0 + (i >> 1)] = 1298271SAli.Saidi@ARM.com static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 | 1308271SAli.Saidi@ARM.com tc->readFloatRegBits(i); 1318271SAli.Saidi@ARM.com } 1328271SAli.Saidi@ARM.com newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) | 1338271SAli.Saidi@ARM.com tc->readIntReg(INTREG_FPCONDCODES); 1346398Sgblack@eecs.umich.edu} 1356365SN/A 1366365SN/Avoid 1376397Sgblack@eecs.umich.eduTrace::ArmNativeTrace::check(NativeTraceRecord *record) 1384776SN/A{ 1396417Sgblack@eecs.umich.edu ThreadContext *tc = record->getThread(); 1406417Sgblack@eecs.umich.edu // This area is read only on the target. It can't stop there to tell us 1416417Sgblack@eecs.umich.edu // what's going on, so we should skip over anything there also. 1427720Sgblack@eecs.umich.edu if (tc->nextInstAddr() > 0xffff0000) 1436417Sgblack@eecs.umich.edu return; 1446398Sgblack@eecs.umich.edu nState.update(this); 1456417Sgblack@eecs.umich.edu mState.update(tc); 1465523SN/A 1477414SAli.Saidi@ARM.com // If a syscall just happened native trace needs another tick 1487414SAli.Saidi@ARM.com if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) && 1497414SAli.Saidi@ARM.com (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) { 1507414SAli.Saidi@ARM.com DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n"); 1517414SAli.Saidi@ARM.com nState.update(this); 1527414SAli.Saidi@ARM.com 1537414SAli.Saidi@ARM.com } 1547414SAli.Saidi@ARM.com 1556409Sgblack@eecs.umich.edu bool errorFound = false; 1566397Sgblack@eecs.umich.edu // Regular int regs 1576398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 1586398Sgblack@eecs.umich.edu if (nState.changed[i] || mState.changed[i]) { 1596398Sgblack@eecs.umich.edu const char *vergence = " "; 1606410Sgblack@eecs.umich.edu bool oldMatch = (mState.oldState[i] == nState.oldState[i]); 1616410Sgblack@eecs.umich.edu bool newMatch = (mState.newState[i] == nState.newState[i]); 1626410Sgblack@eecs.umich.edu if (oldMatch && newMatch) { 1636410Sgblack@eecs.umich.edu // The more things change, the more they stay the same. 1646410Sgblack@eecs.umich.edu continue; 1656410Sgblack@eecs.umich.edu } else if (oldMatch && !newMatch) { 1666398Sgblack@eecs.umich.edu vergence = "<>"; 1676410Sgblack@eecs.umich.edu } else if (!oldMatch && newMatch) { 1686398Sgblack@eecs.umich.edu vergence = "><"; 1696398Sgblack@eecs.umich.edu } 1706410Sgblack@eecs.umich.edu errorFound = true; 1716398Sgblack@eecs.umich.edu if (!nState.changed[i]) { 1726398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1736398Sgblack@eecs.umich.edu "Native: %#010x "\ 1746398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1756398Sgblack@eecs.umich.edu vergence, regNames[i], 1766398Sgblack@eecs.umich.edu nState.newState[i], 1776398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1786398Sgblack@eecs.umich.edu } else if (!mState.changed[i]) { 1796398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1806398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1816398Sgblack@eecs.umich.edu "M5: %#010x \n", 1826398Sgblack@eecs.umich.edu vergence, regNames[i], 1836398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1846398Sgblack@eecs.umich.edu mState.newState[i]); 1856410Sgblack@eecs.umich.edu } else { 1866398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1876398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1886398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1896398Sgblack@eecs.umich.edu vergence, regNames[i], 1906398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1916398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1926398Sgblack@eecs.umich.edu } 1936398Sgblack@eecs.umich.edu } 1944776SN/A } 1956409Sgblack@eecs.umich.edu if (errorFound) { 1966409Sgblack@eecs.umich.edu StaticInstPtr inst = record->getStaticInst(); 1976409Sgblack@eecs.umich.edu assert(inst); 1986409Sgblack@eecs.umich.edu bool ran = true; 1996409Sgblack@eecs.umich.edu if (inst->isMicroop()) { 2006409Sgblack@eecs.umich.edu ran = false; 2016409Sgblack@eecs.umich.edu inst = record->getMacroStaticInst(); 2026409Sgblack@eecs.umich.edu } 2036409Sgblack@eecs.umich.edu assert(inst); 2046409Sgblack@eecs.umich.edu record->traceInst(inst, ran); 2056419Sgblack@eecs.umich.edu 2066419Sgblack@eecs.umich.edu bool pcError = (mState.newState[STATE_PC] != 2076419Sgblack@eecs.umich.edu nState.newState[STATE_PC]); 2086419Sgblack@eecs.umich.edu if (stopOnPCError && pcError) 2096419Sgblack@eecs.umich.edu panic("Native trace detected an error in control flow!"); 2106409Sgblack@eecs.umich.edu } 2114776SN/A} 2124776SN/A 2137811Ssteve.reinhardt@amd.com} // namespace Trace 2144776SN/A 2154776SN/A//////////////////////////////////////////////////////////////////////// 2164776SN/A// 2174776SN/A// ExeTracer Simulation Object 2184776SN/A// 2196397Sgblack@eecs.umich.eduTrace::ArmNativeTrace * 2206397Sgblack@eecs.umich.eduArmNativeTraceParams::create() 2214776SN/A{ 2226397Sgblack@eecs.umich.edu return new Trace::ArmNativeTrace(this); 2234776SN/A}; 224