nativetrace.cc revision 8303 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/arm/isa_traits.hh"
44#include "arch/arm/miscregs.hh"
45#include "arch/arm/nativetrace.hh"
46#include "cpu/thread_context.hh"
47#include "debug/ExecRegDelta.hh"
48#include "params/ArmNativeTrace.hh"
49#include "sim/byteswap.hh"
50
51namespace Trace {
52
53#if TRACING_ON
54static const char *regNames[] = {
55    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
56    "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
57    "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
58    "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
59    "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
60    "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
61    "f31", "fpscr"
62};
63#endif
64
65void
66Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
67{
68    oldState = state[current];
69    current = (current + 1) % 2;
70    newState = state[current];
71
72    memcpy(newState, oldState, sizeof(state[0]));
73
74    uint64_t diffVector;
75    parent->read(&diffVector, sizeof(diffVector));
76    diffVector = ArmISA::gtoh(diffVector);
77
78    int changes = 0;
79    for (int i = 0; i < STATE_NUMVALS; i++) {
80        if (diffVector & 0x1) {
81            changed[i] = true;
82            changes++;
83        } else {
84            changed[i] = false;
85        }
86        diffVector >>= 1;
87    }
88
89    uint64_t values[changes];
90    parent->read(values, sizeof(values));
91    int pos = 0;
92    for (int i = 0; i < STATE_NUMVALS; i++) {
93        if (changed[i]) {
94            newState[i] = ArmISA::gtoh(values[pos++]);
95            changed[i] = (newState[i] != oldState[i]);
96        }
97    }
98}
99
100void
101Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
102{
103    oldState = state[current];
104    current = (current + 1) % 2;
105    newState = state[current];
106
107    // Regular int regs
108    for (int i = 0; i < 15; i++) {
109        newState[i] = tc->readIntReg(i);
110        changed[i] = (oldState[i] != newState[i]);
111    }
112
113    //R15, aliased with the PC
114    newState[STATE_PC] = tc->pcState().npc();
115    changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
116
117    //CPSR
118    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
119    cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
120    cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
121    cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
122    cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
123
124    newState[STATE_CPSR] = cpsr;
125    changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
126
127    for (int i = 0; i < NumFloatArchRegs; i += 2) {
128        newState[STATE_F0 + (i >> 1)] =
129            static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 |
130            tc->readFloatRegBits(i);
131    }
132    newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
133                            tc->readIntReg(INTREG_FPCONDCODES);
134}
135
136void
137Trace::ArmNativeTrace::check(NativeTraceRecord *record)
138{
139    ThreadContext *tc = record->getThread();
140    // This area is read only on the target. It can't stop there to tell us
141    // what's going on, so we should skip over anything there also.
142    if (tc->nextInstAddr() > 0xffff0000)
143        return;
144    nState.update(this);
145    mState.update(tc);
146
147    // If a syscall just happened native trace needs another tick
148    if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
149            (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
150            DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
151            nState.update(this);
152
153    }
154
155    bool errorFound = false;
156    // Regular int regs
157    for (int i = 0; i < STATE_NUMVALS; i++) {
158        if (nState.changed[i] || mState.changed[i]) {
159            const char *vergence = "  ";
160            bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
161            bool newMatch = (mState.newState[i] == nState.newState[i]);
162            if (oldMatch && newMatch) {
163                // The more things change, the more they stay the same.
164                continue;
165            } else if (oldMatch && !newMatch) {
166                vergence = "<>";
167            } else if (!oldMatch && newMatch) {
168                vergence = "><";
169            }
170            errorFound = true;
171            if (!nState.changed[i]) {
172                DPRINTF(ExecRegDelta, "%s [%5s] "\
173                                      "Native:         %#010x         "\
174                                      "M5:     %#010x => %#010x\n",
175                                      vergence, regNames[i],
176                                      nState.newState[i],
177                                      mState.oldState[i], mState.newState[i]);
178            } else if (!mState.changed[i]) {
179                DPRINTF(ExecRegDelta, "%s [%5s] "\
180                                      "Native: %#010x => %#010x "\
181                                      "M5:             %#010x        \n",
182                                      vergence, regNames[i],
183                                      nState.oldState[i], nState.newState[i],
184                                      mState.newState[i]);
185            } else {
186                DPRINTF(ExecRegDelta, "%s [%5s] "\
187                                      "Native: %#010x => %#010x "\
188                                      "M5:     %#010x => %#010x\n",
189                                      vergence, regNames[i],
190                                      nState.oldState[i], nState.newState[i],
191                                      mState.oldState[i], mState.newState[i]);
192            }
193        }
194    }
195    if (errorFound) {
196        StaticInstPtr inst = record->getStaticInst();
197        assert(inst);
198        bool ran = true;
199        if (inst->isMicroop()) {
200            ran = false;
201            inst = record->getMacroStaticInst();
202        }
203        assert(inst);
204        record->traceInst(inst, ran);
205
206        bool pcError = (mState.newState[STATE_PC] !=
207                        nState.newState[STATE_PC]);
208        if (stopOnPCError && pcError)
209            panic("Native trace detected an error in control flow!");
210    }
211}
212
213} // namespace Trace
214
215////////////////////////////////////////////////////////////////////////
216//
217//  ExeTracer Simulation Object
218//
219Trace::ArmNativeTrace *
220ArmNativeTraceParams::create()
221{
222    return new Trace::ArmNativeTrace(this);
223};
224