locked_mem.hh revision 10030
16019Shines@cs.fsu.edu/* 210030SAli.Saidi@ARM.com * Copyright (c) 2012-2013 ARM Limited 39383SAli.Saidi@ARM.com * All rights reserved 49383SAli.Saidi@ARM.com * 59383SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69383SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79383SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89383SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99383SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109383SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119383SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129383SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139383SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 418209SAli.Saidi@ARM.com * Authors: Ali Saidi 428209SAli.Saidi@ARM.com * Steve Reinhardt 436019Shines@cs.fsu.edu * Stephen Hines 446019Shines@cs.fsu.edu */ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu#ifndef __ARCH_ARM_LOCKED_MEM_HH__ 476019Shines@cs.fsu.edu#define __ARCH_ARM_LOCKED_MEM_HH__ 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.edu/** 506019Shines@cs.fsu.edu * @file 516019Shines@cs.fsu.edu * 526019Shines@cs.fsu.edu * ISA-specific helper functions for locked memory accesses. 536019Shines@cs.fsu.edu */ 546019Shines@cs.fsu.edu 558209SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 569383SAli.Saidi@ARM.com#include "mem/packet.hh" 576019Shines@cs.fsu.edu#include "mem/request.hh" 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 616019Shines@cs.fsu.edutemplate <class XC> 626019Shines@cs.fsu.eduinline void 639383SAli.Saidi@ARM.comhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 649383SAli.Saidi@ARM.com{ 659383SAli.Saidi@ARM.com if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 669383SAli.Saidi@ARM.com return; 679383SAli.Saidi@ARM.com 689383SAli.Saidi@ARM.com Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 6910030SAli.Saidi@ARM.com Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 709383SAli.Saidi@ARM.com 719383SAli.Saidi@ARM.com if (locked_addr == snoop_addr) 729383SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 739383SAli.Saidi@ARM.com} 749383SAli.Saidi@ARM.com 759383SAli.Saidi@ARM.comtemplate <class XC> 769383SAli.Saidi@ARM.cominline void 7710030SAli.Saidi@ARM.comhandleLockedSnoopHit(XC *xc) 7810030SAli.Saidi@ARM.com{ 7910030SAli.Saidi@ARM.com} 8010030SAli.Saidi@ARM.com 8110030SAli.Saidi@ARM.comtemplate <class XC> 8210030SAli.Saidi@ARM.cominline void 836019Shines@cs.fsu.eduhandleLockedRead(XC *xc, Request *req) 846019Shines@cs.fsu.edu{ 8510030SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr()); 868209SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, true); 876019Shines@cs.fsu.edu} 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu 906019Shines@cs.fsu.edutemplate <class XC> 916019Shines@cs.fsu.eduinline bool 9210030SAli.Saidi@ARM.comhandleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) 936019Shines@cs.fsu.edu{ 948209SAli.Saidi@ARM.com if (req->isSwap()) 958209SAli.Saidi@ARM.com return true; 968209SAli.Saidi@ARM.com 978209SAli.Saidi@ARM.com // Verify that the lock flag is still set and the address 988209SAli.Saidi@ARM.com // is correct 998209SAli.Saidi@ARM.com bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 10010030SAli.Saidi@ARM.com Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 10110030SAli.Saidi@ARM.com if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) { 1028209SAli.Saidi@ARM.com // Lock flag not set or addr mismatch in CPU; 1038209SAli.Saidi@ARM.com // don't even bother sending to memory system 1048209SAli.Saidi@ARM.com req->setExtraData(0); 1058209SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 1068209SAli.Saidi@ARM.com // the rest of this code is not architectural; 1078209SAli.Saidi@ARM.com // it's just a debugging aid to help detect 1088209SAli.Saidi@ARM.com // livelock by warning on long sequences of failed 1098209SAli.Saidi@ARM.com // store conditionals 1108209SAli.Saidi@ARM.com int stCondFailures = xc->readStCondFailures(); 1118209SAli.Saidi@ARM.com stCondFailures++; 1128209SAli.Saidi@ARM.com xc->setStCondFailures(stCondFailures); 1138209SAli.Saidi@ARM.com if (stCondFailures % 100000 == 0) { 1148209SAli.Saidi@ARM.com warn("context %d: %d consecutive " 1158209SAli.Saidi@ARM.com "store conditional failures\n", 1168209SAli.Saidi@ARM.com xc->contextId(), stCondFailures); 1178209SAli.Saidi@ARM.com } 1188209SAli.Saidi@ARM.com 1198209SAli.Saidi@ARM.com // store conditional failed already, so don't issue it to mem 1208209SAli.Saidi@ARM.com return false; 1218209SAli.Saidi@ARM.com } 1226019Shines@cs.fsu.edu return true; 1236019Shines@cs.fsu.edu} 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edu 1266019Shines@cs.fsu.edu} // namespace ArmISA 1276019Shines@cs.fsu.edu 1286019Shines@cs.fsu.edu#endif 129