locked_mem.hh revision 10030 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Steve Reinhardt
43 *          Stephen Hines
44 */
45
46#ifndef __ARCH_ARM_LOCKED_MEM_HH__
47#define __ARCH_ARM_LOCKED_MEM_HH__
48
49/**
50 * @file
51 *
52 * ISA-specific helper functions for locked memory accesses.
53 */
54
55#include "arch/arm/miscregs.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58
59namespace ArmISA
60{
61template <class XC>
62inline void
63handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
64{
65    if (!xc->readMiscReg(MISCREG_LOCKFLAG))
66        return;
67
68    Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
69    Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
70
71    if (locked_addr == snoop_addr)
72        xc->setMiscReg(MISCREG_LOCKFLAG, false);
73}
74
75template <class XC>
76inline void
77handleLockedSnoopHit(XC *xc)
78{
79}
80
81template <class XC>
82inline void
83handleLockedRead(XC *xc, Request *req)
84{
85    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
86    xc->setMiscReg(MISCREG_LOCKFLAG, true);
87}
88
89
90template <class XC>
91inline bool
92handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
93{
94    if (req->isSwap())
95        return true;
96
97    // Verify that the lock flag is still set and the address
98    // is correct
99    bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
100    Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
101    if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
102        // Lock flag not set or addr mismatch in CPU;
103        // don't even bother sending to memory system
104        req->setExtraData(0);
105        xc->setMiscReg(MISCREG_LOCKFLAG, false);
106        // the rest of this code is not architectural;
107        // it's just a debugging aid to help detect
108        // livelock by warning on long sequences of failed
109        // store conditionals
110        int stCondFailures = xc->readStCondFailures();
111        stCondFailures++;
112        xc->setStCondFailures(stCondFailures);
113        if (stCondFailures % 100000 == 0) {
114            warn("context %d: %d consecutive "
115                 "store conditional failures\n",
116                 xc->contextId(), stCondFailures);
117        }
118
119        // store conditional failed already, so don't issue it to mem
120        return false;
121    }
122    return true;
123}
124
125
126} // namespace ArmISA
127
128#endif
129