system.hh revision 9649
15369Ssaidi@eecs.umich.edu/* 23005Sstever@eecs.umich.edu * Copyright (c) 2010-2012 ARM Limited 33005Sstever@eecs.umich.edu * All rights reserved 43005Sstever@eecs.umich.edu * 53005Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 63005Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 73005Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 83005Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 93005Sstever@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 103005Sstever@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 113005Sstever@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 123005Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 133005Sstever@eecs.umich.edu * 143005Sstever@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 153005Sstever@eecs.umich.edu * All rights reserved. 163005Sstever@eecs.umich.edu * 173005Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 183005Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 193005Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 203005Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 213005Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 223005Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 233005Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 243005Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 253005Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 263005Sstever@eecs.umich.edu * this software without specific prior written permission. 273005Sstever@eecs.umich.edu * 283005Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292710SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302710SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313005Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322889SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336654Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346654Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356654Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366654Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376654Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382667SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396654Snate@binkert.org * 406654Snate@binkert.org * Authors: Ali Saidi 416654Snate@binkert.org */ 425457Ssaidi@eecs.umich.edu 436654Snate@binkert.org#ifndef __ARCH_ARM_LINUX_SYSTEM_HH__ 446654Snate@binkert.org#define __ARCH_ARM_LINUX_SYSTEM_HH__ 455457Ssaidi@eecs.umich.edu 466654Snate@binkert.org#include <cstdio> 476654Snate@binkert.org#include <map> 483395Shsul@eecs.umich.edu#include <string> 496981SLisa.Hsu@amd.com#include <vector> 503448Shsul@eecs.umich.edu 515369Ssaidi@eecs.umich.edu#include "arch/arm/system.hh" 523394Shsul@eecs.umich.edu#include "base/output.hh" 533444Sktlim@umich.edu#include "kern/linux/events.hh" 543444Sktlim@umich.edu#include "params/LinuxArmSystem.hh" 553444Sktlim@umich.edu#include "sim/core.hh" 563444Sktlim@umich.edu 572424SN/Aclass DumpStatsPCEvent; 582957SN/A 592957SN/Aclass LinuxArmSystem : public ArmSystem 603323Shsul@eecs.umich.edu{ 613005Sstever@eecs.umich.edu protected: 627787SAli.Saidi@ARM.com DumpStatsPCEvent *dumpStatsPCEvent; 637787SAli.Saidi@ARM.com 645514SMichael.Adler@intel.com public: 652957SN/A /** Boilerplate params code */ 665514SMichael.Adler@intel.com typedef LinuxArmSystemParams Params; 675514SMichael.Adler@intel.com const Params * 685514SMichael.Adler@intel.com params() const 695514SMichael.Adler@intel.com { 703323Shsul@eecs.umich.edu return dynamic_cast<const Params *>(_params); 713444Sktlim@umich.edu } 722957SN/A 732957SN/A /** When enabled, dump stats/task info on context switches for 742957SN/A * Streamline and per-thread cache occupancy studies, etc. */ 752957SN/A bool enableContextSwitchStatsDump; 762957SN/A 772957SN/A /** This map stores a mapping of OS process IDs to internal Task IDs. The 782957SN/A * mapping is done because the stats system doesn't tend to like vectors 795369Ssaidi@eecs.umich.edu * that are much greater than 1000 items and the entire process space is 805369Ssaidi@eecs.umich.edu * 65K. */ 816654Snate@binkert.org std::map<uint32_t, uint32_t> taskMap; 825369Ssaidi@eecs.umich.edu 835369Ssaidi@eecs.umich.edu /** This is a file that is placed in the run directory that prints out 845369Ssaidi@eecs.umich.edu * mappings between taskIds and OS process IDs */ 855369Ssaidi@eecs.umich.edu std::ostream* taskFile; 865369Ssaidi@eecs.umich.edu 875369Ssaidi@eecs.umich.edu LinuxArmSystem(Params *p); 885369Ssaidi@eecs.umich.edu ~LinuxArmSystem(); 895369Ssaidi@eecs.umich.edu 905369Ssaidi@eecs.umich.edu void initState(); 915369Ssaidi@eecs.umich.edu 925369Ssaidi@eecs.umich.edu bool adderBootUncacheable(Addr a); 935369Ssaidi@eecs.umich.edu 945369Ssaidi@eecs.umich.edu void startup(); 952801SN/A 962801SN/A /** This function creates a new task Id for the given pid. 975514SMichael.Adler@intel.com * @param tc thread context that is currentyl executing */ 985514SMichael.Adler@intel.com void mapPid(ThreadContext* tc, uint32_t pid); 995514SMichael.Adler@intel.com 1005514SMichael.Adler@intel.com private: 1012418SN/A /** Event to halt the simulator if the kernel calls panic() */ 1026391Sksewell@umich.edu PCEvent *kernelPanicEvent; 1036391Sksewell@umich.edu 1046391Sksewell@umich.edu /** Event to halt the simulator if the kernel calls oopses */ 1056642Sksewell@umich.edu PCEvent *kernelOopsEvent; 1066391Sksewell@umich.edu 1076642Sksewell@umich.edu /** 1082833SN/A * PC based event to skip udelay(<time>) calls and quiesce the 1092833SN/A * processor for the appropriate amount of time. This is not functionally 1102833SN/A * required but does speed up simulation. 1112833SN/A */ 1122833SN/A Linux::UDelayEvent *uDelaySkipEvent; 1132833SN/A 1145514SMichael.Adler@intel.com /** Another PC based skip event for const_udelay(). Similar to the udelay 1155514SMichael.Adler@intel.com * skip, but this function precomputes the first multiply that is done 1162833SN/A * in the generic case since the parameter is known at compile time. 1172833SN/A * Thus we need to do some division to get back to us. 1182833SN/A */ 1195514SMichael.Adler@intel.com Linux::UDelayEvent *constUDelaySkipEvent; 1205514SMichael.Adler@intel.com 1215514SMichael.Adler@intel.com /** These variables store addresses of important data structures 1225514SMichael.Adler@intel.com * that are normaly kept coherent at boot with cache mainetence operations. 1232833SN/A * Since these operations aren't supported in gem5, we keep them coherent 1242833SN/A * by making them uncacheable until all processors in the system boot. 1252833SN/A */ 1263005Sstever@eecs.umich.edu Addr secDataPtrAddr; 1272833SN/A Addr secDataAddr; 1282833SN/A Addr penReleaseAddr; 1292833SN/A}; 1305514SMichael.Adler@intel.com 1315514SMichael.Adler@intel.comclass DumpStatsPCEvent : public PCEvent 1325514SMichael.Adler@intel.com{ 1335514SMichael.Adler@intel.com public: 1342833SN/A DumpStatsPCEvent(PCEventQueue *q, const std::string &desc, Addr addr) 1352833SN/A : PCEvent(q, desc, addr) 1366642Sksewell@umich.edu {} 1376642Sksewell@umich.edu 1383481Shsul@eecs.umich.edu virtual void process(ThreadContext* tc); 1392957SN/A}; 1403395Shsul@eecs.umich.edu 1416642Sksewell@umich.edu 1423005Sstever@eecs.umich.edu#endif // __ARCH_ARM_LINUX_SYSTEM_HH__ 1433395Shsul@eecs.umich.edu 1443395Shsul@eecs.umich.edu