base_cpu.cc revision 10860:cba0f26038b4
1/* 2 * Copyright (c) 2012, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 */ 39 40#include "arch/arm/kvm/base_cpu.hh" 41 42#include <linux/kvm.h> 43 44#include "debug/KvmInt.hh" 45#include "params/BaseArmKvmCPU.hh" 46 47 48#define INTERRUPT_ID(type, vcpu, irq) ( \ 49 ((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \ 50 ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \ 51 ((irq) << KVM_ARM_IRQ_NUM_SHIFT)) 52 53#define INTERRUPT_VCPU_IRQ(vcpu) \ 54 INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ) 55 56#define INTERRUPT_VCPU_FIQ(vcpu) \ 57 INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ) 58 59 60BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams *params) 61 : BaseKvmCPU(params), 62 irqAsserted(false), fiqAsserted(false) 63{ 64} 65 66BaseArmKvmCPU::~BaseArmKvmCPU() 67{ 68} 69 70void 71BaseArmKvmCPU::startup() 72{ 73 BaseKvmCPU::startup(); 74 75 /* TODO: This needs to be moved when we start to support VMs with 76 * multiple threads since kvmArmVCpuInit requires that all CPUs in 77 * the VM have been created. 78 */ 79 struct kvm_vcpu_init target_config; 80 memset(&target_config, 0, sizeof(target_config)); 81 82 vm.kvmArmPreferredTarget(target_config); 83 kvmArmVCpuInit(target_config); 84} 85 86Tick 87BaseArmKvmCPU::kvmRun(Tick ticks) 88{ 89 bool simFIQ(interrupts->checkRaw(INT_FIQ)); 90 bool simIRQ(interrupts->checkRaw(INT_IRQ)); 91 92 if (fiqAsserted != simFIQ) { 93 fiqAsserted = simFIQ; 94 DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ); 95 vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ); 96 } 97 if (irqAsserted != simIRQ) { 98 irqAsserted = simIRQ; 99 DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ); 100 vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ); 101 } 102 103 return BaseKvmCPU::kvmRun(ticks); 104} 105 106const BaseArmKvmCPU::RegIndexVector & 107BaseArmKvmCPU::getRegList() const 108{ 109 // Do we need to request a list of registers from the kernel? 110 if (_regIndexList.size() == 0) { 111 // Start by probing for the size of the list. We do this 112 // calling the ioctl with a struct size of 0. The kernel will 113 // return the number of elements required to hold the list. 114 kvm_reg_list regs_probe; 115 regs_probe.n = 0; 116 getRegList(regs_probe); 117 118 // Request the actual register list now that we know how many 119 // register we need to allocate space for. 120 std::unique_ptr<struct kvm_reg_list> regs; 121 const size_t size(sizeof(struct kvm_reg_list) + 122 regs_probe.n * sizeof(uint64_t)); 123 regs.reset((struct kvm_reg_list *)operator new(size)); 124 regs->n = regs_probe.n; 125 if (!getRegList(*regs)) 126 panic("Failed to determine register list size.\n"); 127 128 _regIndexList.assign(regs->reg, regs->reg + regs->n); 129 } 130 131 return _regIndexList; 132} 133 134void 135BaseArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init &init) 136{ 137 if (ioctl(KVM_ARM_VCPU_INIT, (void *)&init) == -1) 138 panic("KVM: Failed to initialize vCPU\n"); 139} 140 141bool 142BaseArmKvmCPU::getRegList(struct kvm_reg_list ®s) const 143{ 144 if (ioctl(KVM_GET_REG_LIST, (void *)®s) == -1) { 145 if (errno == E2BIG) { 146 return false; 147 } else { 148 panic("KVM: Failed to get vCPU register list (errno: %i)\n", 149 errno); 150 } 151 } else { 152 return true; 153 } 154} 155