mem.isa revision 7639
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.edudef template SwapExecute {{ 457205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 477205Sgblack@eecs.umich.edu { 487205Sgblack@eecs.umich.edu Addr EA; 497205Sgblack@eecs.umich.edu Fault fault = NoFault; 507205Sgblack@eecs.umich.edu 517205Sgblack@eecs.umich.edu %(op_decl)s; 527205Sgblack@eecs.umich.edu uint64_t memData = 0; 537205Sgblack@eecs.umich.edu %(op_rd)s; 547205Sgblack@eecs.umich.edu %(ea_code)s; 557205Sgblack@eecs.umich.edu 567205Sgblack@eecs.umich.edu if (%(predicate_test)s) 577205Sgblack@eecs.umich.edu { 587205Sgblack@eecs.umich.edu %(preacc_code)s; 597205Sgblack@eecs.umich.edu 607205Sgblack@eecs.umich.edu if (fault == NoFault) { 617205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 627205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 637205Sgblack@eecs.umich.edu } 647205Sgblack@eecs.umich.edu 657205Sgblack@eecs.umich.edu if (fault == NoFault) { 667205Sgblack@eecs.umich.edu %(postacc_code)s; 677205Sgblack@eecs.umich.edu } 687205Sgblack@eecs.umich.edu 697205Sgblack@eecs.umich.edu if (fault == NoFault) { 707205Sgblack@eecs.umich.edu %(op_wb)s; 717205Sgblack@eecs.umich.edu } 727597Sminkyu.jeong@arm.com } else { 737597Sminkyu.jeong@arm.com xc->setPredicate(false); 747205Sgblack@eecs.umich.edu } 757205Sgblack@eecs.umich.edu 767408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 777408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 787408Sgblack@eecs.umich.edu } 797408Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu return fault; 817205Sgblack@eecs.umich.edu } 827205Sgblack@eecs.umich.edu}}; 837205Sgblack@eecs.umich.edu 847205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 857205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 867205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 877205Sgblack@eecs.umich.edu { 887205Sgblack@eecs.umich.edu Addr EA; 897205Sgblack@eecs.umich.edu Fault fault = NoFault; 907205Sgblack@eecs.umich.edu 917205Sgblack@eecs.umich.edu %(op_decl)s; 927205Sgblack@eecs.umich.edu uint64_t memData = 0; 937205Sgblack@eecs.umich.edu %(op_rd)s; 947205Sgblack@eecs.umich.edu %(ea_code)s; 957205Sgblack@eecs.umich.edu 967205Sgblack@eecs.umich.edu if (%(predicate_test)s) 977205Sgblack@eecs.umich.edu { 987205Sgblack@eecs.umich.edu %(preacc_code)s; 997205Sgblack@eecs.umich.edu 1007205Sgblack@eecs.umich.edu if (fault == NoFault) { 1017205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1027205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057205Sgblack@eecs.umich.edu if (fault == NoFault) { 1067205Sgblack@eecs.umich.edu %(op_wb)s; 1077205Sgblack@eecs.umich.edu } 1087597Sminkyu.jeong@arm.com } else { 1097597Sminkyu.jeong@arm.com xc->setPredicate(false); 1107205Sgblack@eecs.umich.edu } 1117205Sgblack@eecs.umich.edu 1127408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1137408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1147408Sgblack@eecs.umich.edu } 1157408Sgblack@eecs.umich.edu 1167205Sgblack@eecs.umich.edu return fault; 1177205Sgblack@eecs.umich.edu } 1187205Sgblack@eecs.umich.edu}}; 1197205Sgblack@eecs.umich.edu 1207205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1217205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1227205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1237205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1247205Sgblack@eecs.umich.edu { 1257205Sgblack@eecs.umich.edu Fault fault = NoFault; 1267205Sgblack@eecs.umich.edu 1277205Sgblack@eecs.umich.edu %(op_decl)s; 1287205Sgblack@eecs.umich.edu %(op_rd)s; 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1317205Sgblack@eecs.umich.edu { 1327205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1337205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1347205Sgblack@eecs.umich.edu 1357205Sgblack@eecs.umich.edu %(postacc_code)s; 1367205Sgblack@eecs.umich.edu 1377205Sgblack@eecs.umich.edu if (fault == NoFault) { 1387205Sgblack@eecs.umich.edu %(op_wb)s; 1397205Sgblack@eecs.umich.edu } 1407205Sgblack@eecs.umich.edu } 1417205Sgblack@eecs.umich.edu 1427408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1437408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1447408Sgblack@eecs.umich.edu } 1457408Sgblack@eecs.umich.edu 1467205Sgblack@eecs.umich.edu return fault; 1477205Sgblack@eecs.umich.edu } 1487205Sgblack@eecs.umich.edu}}; 1497205Sgblack@eecs.umich.edu 1507119Sgblack@eecs.umich.edudef template LoadExecute {{ 1517119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1527119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1537119Sgblack@eecs.umich.edu { 1547119Sgblack@eecs.umich.edu Addr EA; 1557119Sgblack@eecs.umich.edu Fault fault = NoFault; 1567119Sgblack@eecs.umich.edu 1577119Sgblack@eecs.umich.edu %(op_decl)s; 1587119Sgblack@eecs.umich.edu %(op_rd)s; 1597119Sgblack@eecs.umich.edu %(ea_code)s; 1607119Sgblack@eecs.umich.edu 1617119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1627119Sgblack@eecs.umich.edu { 1637119Sgblack@eecs.umich.edu if (fault == NoFault) { 1647119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1657119Sgblack@eecs.umich.edu %(memacc_code)s; 1667119Sgblack@eecs.umich.edu } 1677119Sgblack@eecs.umich.edu 1687119Sgblack@eecs.umich.edu if (fault == NoFault) { 1697119Sgblack@eecs.umich.edu %(op_wb)s; 1707119Sgblack@eecs.umich.edu } 1717597Sminkyu.jeong@arm.com } else { 1727597Sminkyu.jeong@arm.com xc->setPredicate(false); 1737119Sgblack@eecs.umich.edu } 1747119Sgblack@eecs.umich.edu 1757408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1767408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1777408Sgblack@eecs.umich.edu } 1787408Sgblack@eecs.umich.edu 1797119Sgblack@eecs.umich.edu return fault; 1807119Sgblack@eecs.umich.edu } 1817119Sgblack@eecs.umich.edu}}; 1827119Sgblack@eecs.umich.edu 1837639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1847639Sgblack@eecs.umich.edu template <class Element> 1857639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 1867639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1877639Sgblack@eecs.umich.edu { 1887639Sgblack@eecs.umich.edu Addr EA; 1897639Sgblack@eecs.umich.edu Fault fault = NoFault; 1907639Sgblack@eecs.umich.edu 1917639Sgblack@eecs.umich.edu %(op_decl)s; 1927639Sgblack@eecs.umich.edu %(mem_decl)s; 1937639Sgblack@eecs.umich.edu %(op_rd)s; 1947639Sgblack@eecs.umich.edu %(ea_code)s; 1957639Sgblack@eecs.umich.edu 1967639Sgblack@eecs.umich.edu MemUnion memUnion; 1977639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 1987639Sgblack@eecs.umich.edu 1997639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2007639Sgblack@eecs.umich.edu { 2017639Sgblack@eecs.umich.edu if (fault == NoFault) { 2027639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 2037639Sgblack@eecs.umich.edu %(memacc_code)s; 2047639Sgblack@eecs.umich.edu } 2057639Sgblack@eecs.umich.edu 2067639Sgblack@eecs.umich.edu if (fault == NoFault) { 2077639Sgblack@eecs.umich.edu %(op_wb)s; 2087639Sgblack@eecs.umich.edu } 2097639Sgblack@eecs.umich.edu } 2107639Sgblack@eecs.umich.edu 2117639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2127639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2137639Sgblack@eecs.umich.edu } 2147639Sgblack@eecs.umich.edu 2157639Sgblack@eecs.umich.edu return fault; 2167639Sgblack@eecs.umich.edu } 2177639Sgblack@eecs.umich.edu}}; 2187639Sgblack@eecs.umich.edu 2197120Sgblack@eecs.umich.edudef template StoreExecute {{ 2207120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2217120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2227120Sgblack@eecs.umich.edu { 2237120Sgblack@eecs.umich.edu Addr EA; 2247120Sgblack@eecs.umich.edu Fault fault = NoFault; 2257120Sgblack@eecs.umich.edu 2267120Sgblack@eecs.umich.edu %(op_decl)s; 2277120Sgblack@eecs.umich.edu %(op_rd)s; 2287120Sgblack@eecs.umich.edu %(ea_code)s; 2297120Sgblack@eecs.umich.edu 2307120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2317120Sgblack@eecs.umich.edu { 2327120Sgblack@eecs.umich.edu if (fault == NoFault) { 2337120Sgblack@eecs.umich.edu %(memacc_code)s; 2347120Sgblack@eecs.umich.edu } 2357120Sgblack@eecs.umich.edu 2367120Sgblack@eecs.umich.edu if (fault == NoFault) { 2377120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2387120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2397120Sgblack@eecs.umich.edu } 2407120Sgblack@eecs.umich.edu 2417120Sgblack@eecs.umich.edu if (fault == NoFault) { 2427120Sgblack@eecs.umich.edu %(op_wb)s; 2437120Sgblack@eecs.umich.edu } 2447597Sminkyu.jeong@arm.com } else { 2457597Sminkyu.jeong@arm.com xc->setPredicate(false); 2467120Sgblack@eecs.umich.edu } 2477120Sgblack@eecs.umich.edu 2487408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2497408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2507408Sgblack@eecs.umich.edu } 2517408Sgblack@eecs.umich.edu 2527120Sgblack@eecs.umich.edu return fault; 2537120Sgblack@eecs.umich.edu } 2547120Sgblack@eecs.umich.edu}}; 2557120Sgblack@eecs.umich.edu 2567639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2577639Sgblack@eecs.umich.edu template <class Element> 2587639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2597639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2607639Sgblack@eecs.umich.edu { 2617639Sgblack@eecs.umich.edu Addr EA; 2627639Sgblack@eecs.umich.edu Fault fault = NoFault; 2637639Sgblack@eecs.umich.edu 2647639Sgblack@eecs.umich.edu %(op_decl)s; 2657639Sgblack@eecs.umich.edu %(mem_decl)s; 2667639Sgblack@eecs.umich.edu %(op_rd)s; 2677639Sgblack@eecs.umich.edu %(ea_code)s; 2687639Sgblack@eecs.umich.edu 2697639Sgblack@eecs.umich.edu MemUnion memUnion; 2707639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2717639Sgblack@eecs.umich.edu 2727639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2737639Sgblack@eecs.umich.edu { 2747639Sgblack@eecs.umich.edu if (fault == NoFault) { 2757639Sgblack@eecs.umich.edu %(memacc_code)s; 2767639Sgblack@eecs.umich.edu } 2777639Sgblack@eecs.umich.edu 2787639Sgblack@eecs.umich.edu if (fault == NoFault) { 2797639Sgblack@eecs.umich.edu fault = xc->writeBytes(dataPtr, %(size)d, EA, 2807639Sgblack@eecs.umich.edu memAccessFlags, NULL); 2817639Sgblack@eecs.umich.edu } 2827639Sgblack@eecs.umich.edu 2837639Sgblack@eecs.umich.edu if (fault == NoFault) { 2847639Sgblack@eecs.umich.edu %(op_wb)s; 2857639Sgblack@eecs.umich.edu } 2867639Sgblack@eecs.umich.edu } 2877639Sgblack@eecs.umich.edu 2887639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2897639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2907639Sgblack@eecs.umich.edu } 2917639Sgblack@eecs.umich.edu 2927639Sgblack@eecs.umich.edu return fault; 2937639Sgblack@eecs.umich.edu } 2947639Sgblack@eecs.umich.edu}}; 2957639Sgblack@eecs.umich.edu 2967303Sgblack@eecs.umich.edudef template StoreExExecute {{ 2977303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2987303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2997303Sgblack@eecs.umich.edu { 3007303Sgblack@eecs.umich.edu Addr EA; 3017303Sgblack@eecs.umich.edu Fault fault = NoFault; 3027303Sgblack@eecs.umich.edu 3037303Sgblack@eecs.umich.edu %(op_decl)s; 3047303Sgblack@eecs.umich.edu %(op_rd)s; 3057303Sgblack@eecs.umich.edu %(ea_code)s; 3067303Sgblack@eecs.umich.edu 3077303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3087303Sgblack@eecs.umich.edu { 3097303Sgblack@eecs.umich.edu if (fault == NoFault) { 3107303Sgblack@eecs.umich.edu %(memacc_code)s; 3117303Sgblack@eecs.umich.edu } 3127303Sgblack@eecs.umich.edu 3137303Sgblack@eecs.umich.edu uint64_t writeResult; 3147303Sgblack@eecs.umich.edu 3157303Sgblack@eecs.umich.edu if (fault == NoFault) { 3167303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3177303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 3187303Sgblack@eecs.umich.edu } 3197303Sgblack@eecs.umich.edu 3207303Sgblack@eecs.umich.edu if (fault == NoFault) { 3217303Sgblack@eecs.umich.edu %(postacc_code)s; 3227303Sgblack@eecs.umich.edu } 3237303Sgblack@eecs.umich.edu 3247303Sgblack@eecs.umich.edu if (fault == NoFault) { 3257303Sgblack@eecs.umich.edu %(op_wb)s; 3267303Sgblack@eecs.umich.edu } 3277597Sminkyu.jeong@arm.com } else { 3287597Sminkyu.jeong@arm.com xc->setPredicate(false); 3297303Sgblack@eecs.umich.edu } 3307303Sgblack@eecs.umich.edu 3317408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 3327408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3337408Sgblack@eecs.umich.edu } 3347408Sgblack@eecs.umich.edu 3357303Sgblack@eecs.umich.edu return fault; 3367303Sgblack@eecs.umich.edu } 3377303Sgblack@eecs.umich.edu}}; 3387303Sgblack@eecs.umich.edu 3397303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3407303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3417303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3427303Sgblack@eecs.umich.edu { 3437303Sgblack@eecs.umich.edu Addr EA; 3447303Sgblack@eecs.umich.edu Fault fault = NoFault; 3457303Sgblack@eecs.umich.edu 3467303Sgblack@eecs.umich.edu %(op_decl)s; 3477303Sgblack@eecs.umich.edu %(op_rd)s; 3487303Sgblack@eecs.umich.edu %(ea_code)s; 3497303Sgblack@eecs.umich.edu 3507303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3517303Sgblack@eecs.umich.edu { 3527303Sgblack@eecs.umich.edu if (fault == NoFault) { 3537303Sgblack@eecs.umich.edu %(memacc_code)s; 3547303Sgblack@eecs.umich.edu } 3557303Sgblack@eecs.umich.edu 3567303Sgblack@eecs.umich.edu if (fault == NoFault) { 3577303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3587303Sgblack@eecs.umich.edu memAccessFlags, NULL); 3597303Sgblack@eecs.umich.edu } 3607303Sgblack@eecs.umich.edu 3617303Sgblack@eecs.umich.edu // Need to write back any potential address register update 3627303Sgblack@eecs.umich.edu if (fault == NoFault) { 3637303Sgblack@eecs.umich.edu %(op_wb)s; 3647303Sgblack@eecs.umich.edu } 3657597Sminkyu.jeong@arm.com } else { 3667597Sminkyu.jeong@arm.com xc->setPredicate(false); 3677303Sgblack@eecs.umich.edu } 3687303Sgblack@eecs.umich.edu 3697408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 3707408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3717408Sgblack@eecs.umich.edu } 3727408Sgblack@eecs.umich.edu 3737303Sgblack@eecs.umich.edu return fault; 3747303Sgblack@eecs.umich.edu } 3757303Sgblack@eecs.umich.edu}}; 3767303Sgblack@eecs.umich.edu 3777120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3787120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3797120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3807120Sgblack@eecs.umich.edu { 3817120Sgblack@eecs.umich.edu Addr EA; 3827120Sgblack@eecs.umich.edu Fault fault = NoFault; 3837120Sgblack@eecs.umich.edu 3847120Sgblack@eecs.umich.edu %(op_decl)s; 3857120Sgblack@eecs.umich.edu %(op_rd)s; 3867120Sgblack@eecs.umich.edu %(ea_code)s; 3877120Sgblack@eecs.umich.edu 3887120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3897120Sgblack@eecs.umich.edu { 3907120Sgblack@eecs.umich.edu if (fault == NoFault) { 3917120Sgblack@eecs.umich.edu %(memacc_code)s; 3927120Sgblack@eecs.umich.edu } 3937120Sgblack@eecs.umich.edu 3947120Sgblack@eecs.umich.edu if (fault == NoFault) { 3957120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3967120Sgblack@eecs.umich.edu memAccessFlags, NULL); 3977120Sgblack@eecs.umich.edu } 3987120Sgblack@eecs.umich.edu 3997120Sgblack@eecs.umich.edu // Need to write back any potential address register update 4007120Sgblack@eecs.umich.edu if (fault == NoFault) { 4017120Sgblack@eecs.umich.edu %(op_wb)s; 4027120Sgblack@eecs.umich.edu } 4037597Sminkyu.jeong@arm.com } else { 4047597Sminkyu.jeong@arm.com xc->setPredicate(false); 4057120Sgblack@eecs.umich.edu } 4067120Sgblack@eecs.umich.edu 4077408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 4087408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4097408Sgblack@eecs.umich.edu } 4107408Sgblack@eecs.umich.edu 4117120Sgblack@eecs.umich.edu return fault; 4127120Sgblack@eecs.umich.edu } 4137120Sgblack@eecs.umich.edu}}; 4147120Sgblack@eecs.umich.edu 4157639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 4167639Sgblack@eecs.umich.edu template <class Element> 4177639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4187639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4197639Sgblack@eecs.umich.edu { 4207639Sgblack@eecs.umich.edu Addr EA; 4217639Sgblack@eecs.umich.edu Fault fault = NoFault; 4227639Sgblack@eecs.umich.edu 4237639Sgblack@eecs.umich.edu %(op_decl)s; 4247639Sgblack@eecs.umich.edu %(mem_decl)s; 4257639Sgblack@eecs.umich.edu %(op_rd)s; 4267639Sgblack@eecs.umich.edu %(ea_code)s; 4277639Sgblack@eecs.umich.edu 4287639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4297639Sgblack@eecs.umich.edu { 4307639Sgblack@eecs.umich.edu MemUnion memUnion; 4317639Sgblack@eecs.umich.edu if (fault == NoFault) { 4327639Sgblack@eecs.umich.edu %(memacc_code)s; 4337639Sgblack@eecs.umich.edu } 4347639Sgblack@eecs.umich.edu 4357639Sgblack@eecs.umich.edu if (fault == NoFault) { 4367639Sgblack@eecs.umich.edu fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 4377639Sgblack@eecs.umich.edu memAccessFlags, NULL); 4387639Sgblack@eecs.umich.edu } 4397639Sgblack@eecs.umich.edu 4407639Sgblack@eecs.umich.edu // Need to write back any potential address register update 4417639Sgblack@eecs.umich.edu if (fault == NoFault) { 4427639Sgblack@eecs.umich.edu %(op_wb)s; 4437639Sgblack@eecs.umich.edu } 4447639Sgblack@eecs.umich.edu } 4457639Sgblack@eecs.umich.edu 4467639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 4477639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4487639Sgblack@eecs.umich.edu } 4497639Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edu return fault; 4517639Sgblack@eecs.umich.edu } 4527639Sgblack@eecs.umich.edu}}; 4537639Sgblack@eecs.umich.edu 4547119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4557119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4567119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4577119Sgblack@eecs.umich.edu { 4587119Sgblack@eecs.umich.edu Addr EA; 4597119Sgblack@eecs.umich.edu Fault fault = NoFault; 4607119Sgblack@eecs.umich.edu 4617119Sgblack@eecs.umich.edu %(op_src_decl)s; 4627119Sgblack@eecs.umich.edu %(op_rd)s; 4637119Sgblack@eecs.umich.edu %(ea_code)s; 4647119Sgblack@eecs.umich.edu 4657119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4667119Sgblack@eecs.umich.edu { 4677119Sgblack@eecs.umich.edu if (fault == NoFault) { 4687119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 4697119Sgblack@eecs.umich.edu } 4707597Sminkyu.jeong@arm.com } else { 4717597Sminkyu.jeong@arm.com xc->setPredicate(false); 4727597Sminkyu.jeong@arm.com if (fault == NoFault && machInst.itstateMask != 0) { 4737597Sminkyu.jeong@arm.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4747597Sminkyu.jeong@arm.com } 4757119Sgblack@eecs.umich.edu } 4767119Sgblack@eecs.umich.edu 4777119Sgblack@eecs.umich.edu return fault; 4787119Sgblack@eecs.umich.edu } 4797119Sgblack@eecs.umich.edu}}; 4807119Sgblack@eecs.umich.edu 4817639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4827639Sgblack@eecs.umich.edu template <class Element> 4837639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4847639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4857639Sgblack@eecs.umich.edu { 4867639Sgblack@eecs.umich.edu Addr EA; 4877639Sgblack@eecs.umich.edu Fault fault = NoFault; 4887639Sgblack@eecs.umich.edu 4897639Sgblack@eecs.umich.edu %(op_src_decl)s; 4907639Sgblack@eecs.umich.edu %(op_rd)s; 4917639Sgblack@eecs.umich.edu %(ea_code)s; 4927639Sgblack@eecs.umich.edu 4937639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4947639Sgblack@eecs.umich.edu { 4957639Sgblack@eecs.umich.edu if (fault == NoFault) { 4967639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 4977639Sgblack@eecs.umich.edu } 4987639Sgblack@eecs.umich.edu } else if (fault == NoFault && machInst.itstateMask != 0) { 4997639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5007639Sgblack@eecs.umich.edu } 5017639Sgblack@eecs.umich.edu 5027639Sgblack@eecs.umich.edu return fault; 5037639Sgblack@eecs.umich.edu } 5047639Sgblack@eecs.umich.edu}}; 5057639Sgblack@eecs.umich.edu 5067119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 5077119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5087119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5097119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5107119Sgblack@eecs.umich.edu { 5117119Sgblack@eecs.umich.edu Fault fault = NoFault; 5127119Sgblack@eecs.umich.edu 5137119Sgblack@eecs.umich.edu %(op_decl)s; 5147119Sgblack@eecs.umich.edu %(op_rd)s; 5157119Sgblack@eecs.umich.edu 5167119Sgblack@eecs.umich.edu if (%(predicate_test)s) 5177119Sgblack@eecs.umich.edu { 5187119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5197119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 5207119Sgblack@eecs.umich.edu 5217119Sgblack@eecs.umich.edu if (fault == NoFault) { 5227119Sgblack@eecs.umich.edu %(memacc_code)s; 5237119Sgblack@eecs.umich.edu } 5247119Sgblack@eecs.umich.edu 5257119Sgblack@eecs.umich.edu if (fault == NoFault) { 5267119Sgblack@eecs.umich.edu %(op_wb)s; 5277119Sgblack@eecs.umich.edu } 5287119Sgblack@eecs.umich.edu } 5297119Sgblack@eecs.umich.edu 5307408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5317408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5327408Sgblack@eecs.umich.edu } 5337408Sgblack@eecs.umich.edu 5347119Sgblack@eecs.umich.edu return fault; 5357119Sgblack@eecs.umich.edu } 5367119Sgblack@eecs.umich.edu}}; 5377119Sgblack@eecs.umich.edu 5387639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5397639Sgblack@eecs.umich.edu template <class Element> 5407639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5417639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5427639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5437639Sgblack@eecs.umich.edu { 5447639Sgblack@eecs.umich.edu Fault fault = NoFault; 5457639Sgblack@eecs.umich.edu 5467639Sgblack@eecs.umich.edu %(mem_decl)s; 5477639Sgblack@eecs.umich.edu %(op_decl)s; 5487639Sgblack@eecs.umich.edu %(op_rd)s; 5497639Sgblack@eecs.umich.edu 5507639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5517639Sgblack@eecs.umich.edu { 5527639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5537639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5547639Sgblack@eecs.umich.edu 5557639Sgblack@eecs.umich.edu if (fault == NoFault) { 5567639Sgblack@eecs.umich.edu %(memacc_code)s; 5577639Sgblack@eecs.umich.edu } 5587639Sgblack@eecs.umich.edu 5597639Sgblack@eecs.umich.edu if (fault == NoFault) { 5607639Sgblack@eecs.umich.edu %(op_wb)s; 5617639Sgblack@eecs.umich.edu } 5627639Sgblack@eecs.umich.edu } 5637639Sgblack@eecs.umich.edu 5647639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5657639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5667639Sgblack@eecs.umich.edu } 5677639Sgblack@eecs.umich.edu 5687639Sgblack@eecs.umich.edu return fault; 5697639Sgblack@eecs.umich.edu } 5707639Sgblack@eecs.umich.edu}}; 5717639Sgblack@eecs.umich.edu 5727120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5737120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5747120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5757120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5767120Sgblack@eecs.umich.edu { 5777120Sgblack@eecs.umich.edu Fault fault = NoFault; 5787120Sgblack@eecs.umich.edu 5797120Sgblack@eecs.umich.edu %(op_decl)s; 5807120Sgblack@eecs.umich.edu %(op_rd)s; 5817120Sgblack@eecs.umich.edu 5827120Sgblack@eecs.umich.edu if (%(predicate_test)s) 5837120Sgblack@eecs.umich.edu { 5847120Sgblack@eecs.umich.edu if (fault == NoFault) { 5857120Sgblack@eecs.umich.edu %(op_wb)s; 5867120Sgblack@eecs.umich.edu } 5877120Sgblack@eecs.umich.edu } 5887120Sgblack@eecs.umich.edu 5897408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5907408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5917408Sgblack@eecs.umich.edu } 5927408Sgblack@eecs.umich.edu 5937120Sgblack@eecs.umich.edu return fault; 5947120Sgblack@eecs.umich.edu } 5957120Sgblack@eecs.umich.edu}}; 5967120Sgblack@eecs.umich.edu 5977639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5987639Sgblack@eecs.umich.edu template <class Element> 5997639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 6007639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 6017639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6027639Sgblack@eecs.umich.edu { 6037639Sgblack@eecs.umich.edu Fault fault = NoFault; 6047639Sgblack@eecs.umich.edu 6057639Sgblack@eecs.umich.edu %(op_decl)s; 6067639Sgblack@eecs.umich.edu %(op_rd)s; 6077639Sgblack@eecs.umich.edu 6087639Sgblack@eecs.umich.edu if (%(predicate_test)s) 6097639Sgblack@eecs.umich.edu { 6107639Sgblack@eecs.umich.edu if (fault == NoFault) { 6117639Sgblack@eecs.umich.edu %(op_wb)s; 6127639Sgblack@eecs.umich.edu } 6137639Sgblack@eecs.umich.edu } 6147639Sgblack@eecs.umich.edu 6157639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6167639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6177639Sgblack@eecs.umich.edu } 6187639Sgblack@eecs.umich.edu 6197639Sgblack@eecs.umich.edu return fault; 6207639Sgblack@eecs.umich.edu } 6217639Sgblack@eecs.umich.edu}}; 6227639Sgblack@eecs.umich.edu 6237303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 6247303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6257303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 6267303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6277303Sgblack@eecs.umich.edu { 6287303Sgblack@eecs.umich.edu Fault fault = NoFault; 6297303Sgblack@eecs.umich.edu 6307303Sgblack@eecs.umich.edu %(op_decl)s; 6317303Sgblack@eecs.umich.edu %(op_rd)s; 6327303Sgblack@eecs.umich.edu 6337303Sgblack@eecs.umich.edu if (%(predicate_test)s) 6347303Sgblack@eecs.umich.edu { 6357303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 6367303Sgblack@eecs.umich.edu %(postacc_code)s; 6377303Sgblack@eecs.umich.edu 6387303Sgblack@eecs.umich.edu if (fault == NoFault) { 6397303Sgblack@eecs.umich.edu %(op_wb)s; 6407303Sgblack@eecs.umich.edu } 6417303Sgblack@eecs.umich.edu } 6427303Sgblack@eecs.umich.edu 6437408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6447408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6457408Sgblack@eecs.umich.edu } 6467408Sgblack@eecs.umich.edu 6477303Sgblack@eecs.umich.edu return fault; 6487303Sgblack@eecs.umich.edu } 6497303Sgblack@eecs.umich.edu}}; 6507303Sgblack@eecs.umich.edu 6517291Sgblack@eecs.umich.edudef template RfeDeclare {{ 6527291Sgblack@eecs.umich.edu /** 6537291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6547291Sgblack@eecs.umich.edu */ 6557291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6567291Sgblack@eecs.umich.edu { 6577291Sgblack@eecs.umich.edu public: 6587291Sgblack@eecs.umich.edu 6597291Sgblack@eecs.umich.edu /// Constructor. 6607291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6617291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 6627291Sgblack@eecs.umich.edu 6637291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6647291Sgblack@eecs.umich.edu 6657291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6667291Sgblack@eecs.umich.edu 6677291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6687291Sgblack@eecs.umich.edu }; 6697291Sgblack@eecs.umich.edu}}; 6707291Sgblack@eecs.umich.edu 6717312Sgblack@eecs.umich.edudef template SrsDeclare {{ 6727312Sgblack@eecs.umich.edu /** 6737312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6747312Sgblack@eecs.umich.edu */ 6757312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6767312Sgblack@eecs.umich.edu { 6777312Sgblack@eecs.umich.edu public: 6787312Sgblack@eecs.umich.edu 6797312Sgblack@eecs.umich.edu /// Constructor. 6807312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6817312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6827312Sgblack@eecs.umich.edu 6837312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6847312Sgblack@eecs.umich.edu 6857312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6867312Sgblack@eecs.umich.edu 6877312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6887312Sgblack@eecs.umich.edu }; 6897312Sgblack@eecs.umich.edu}}; 6907312Sgblack@eecs.umich.edu 6917205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6927205Sgblack@eecs.umich.edu /** 6937205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6947205Sgblack@eecs.umich.edu */ 6957205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6967205Sgblack@eecs.umich.edu { 6977205Sgblack@eecs.umich.edu public: 6987205Sgblack@eecs.umich.edu 6997205Sgblack@eecs.umich.edu /// Constructor. 7007205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7017205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 7027205Sgblack@eecs.umich.edu 7037205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7047205Sgblack@eecs.umich.edu 7057205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7067205Sgblack@eecs.umich.edu 7077205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7087205Sgblack@eecs.umich.edu }; 7097205Sgblack@eecs.umich.edu}}; 7107205Sgblack@eecs.umich.edu 7117279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 7127279Sgblack@eecs.umich.edu /** 7137279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7147279Sgblack@eecs.umich.edu */ 7157279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7167279Sgblack@eecs.umich.edu { 7177279Sgblack@eecs.umich.edu public: 7187279Sgblack@eecs.umich.edu 7197279Sgblack@eecs.umich.edu /// Constructor. 7207279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7217279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7227279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7237279Sgblack@eecs.umich.edu 7247279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7257279Sgblack@eecs.umich.edu 7267279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7277279Sgblack@eecs.umich.edu 7287279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7297279Sgblack@eecs.umich.edu }; 7307279Sgblack@eecs.umich.edu}}; 7317279Sgblack@eecs.umich.edu 7327303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 7337303Sgblack@eecs.umich.edu /** 7347303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7357303Sgblack@eecs.umich.edu */ 7367303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7377303Sgblack@eecs.umich.edu { 7387303Sgblack@eecs.umich.edu public: 7397303Sgblack@eecs.umich.edu 7407303Sgblack@eecs.umich.edu /// Constructor. 7417303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7427303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 7437303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7447303Sgblack@eecs.umich.edu 7457303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7467303Sgblack@eecs.umich.edu 7477303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7487303Sgblack@eecs.umich.edu 7497303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7507303Sgblack@eecs.umich.edu }; 7517303Sgblack@eecs.umich.edu}}; 7527303Sgblack@eecs.umich.edu 7537119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 7547119Sgblack@eecs.umich.edu /** 7557119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7567119Sgblack@eecs.umich.edu */ 7577119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7587119Sgblack@eecs.umich.edu { 7597119Sgblack@eecs.umich.edu public: 7607119Sgblack@eecs.umich.edu 7617119Sgblack@eecs.umich.edu /// Constructor. 7627119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7637119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 7647119Sgblack@eecs.umich.edu 7657119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7667119Sgblack@eecs.umich.edu 7677119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7687119Sgblack@eecs.umich.edu 7697119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7707119Sgblack@eecs.umich.edu }; 7717119Sgblack@eecs.umich.edu}}; 7727119Sgblack@eecs.umich.edu 7737303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7747303Sgblack@eecs.umich.edu /** 7757303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7767303Sgblack@eecs.umich.edu */ 7777303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7787303Sgblack@eecs.umich.edu { 7797303Sgblack@eecs.umich.edu public: 7807303Sgblack@eecs.umich.edu 7817303Sgblack@eecs.umich.edu /// Constructor. 7827303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7837303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7847303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7857303Sgblack@eecs.umich.edu 7867303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7877303Sgblack@eecs.umich.edu 7887303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7897303Sgblack@eecs.umich.edu 7907303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7917303Sgblack@eecs.umich.edu }; 7927303Sgblack@eecs.umich.edu}}; 7937303Sgblack@eecs.umich.edu 7947279Sgblack@eecs.umich.edudef template LoadStoreDRegDeclare {{ 7957279Sgblack@eecs.umich.edu /** 7967279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7977279Sgblack@eecs.umich.edu */ 7987279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7997279Sgblack@eecs.umich.edu { 8007279Sgblack@eecs.umich.edu public: 8017279Sgblack@eecs.umich.edu 8027279Sgblack@eecs.umich.edu /// Constructor. 8037279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8047279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 8057279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 8067279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8077279Sgblack@eecs.umich.edu uint32_t _index); 8087279Sgblack@eecs.umich.edu 8097279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8107279Sgblack@eecs.umich.edu 8117279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8127279Sgblack@eecs.umich.edu 8137279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8147279Sgblack@eecs.umich.edu }; 8157279Sgblack@eecs.umich.edu}}; 8167279Sgblack@eecs.umich.edu 8177119Sgblack@eecs.umich.edudef template LoadStoreRegDeclare {{ 8187119Sgblack@eecs.umich.edu /** 8197119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8207119Sgblack@eecs.umich.edu */ 8217119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8227119Sgblack@eecs.umich.edu { 8237119Sgblack@eecs.umich.edu public: 8247119Sgblack@eecs.umich.edu 8257119Sgblack@eecs.umich.edu /// Constructor. 8267119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8277119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 8287119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8297119Sgblack@eecs.umich.edu uint32_t _index); 8307119Sgblack@eecs.umich.edu 8317119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8327119Sgblack@eecs.umich.edu 8337119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8347119Sgblack@eecs.umich.edu 8357119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8367119Sgblack@eecs.umich.edu }; 8377119Sgblack@eecs.umich.edu}}; 8387119Sgblack@eecs.umich.edu 8397119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 8407119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8417119Sgblack@eecs.umich.edu}}; 8427119Sgblack@eecs.umich.edu 8437119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 8447119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 8457119Sgblack@eecs.umich.edu}}; 8467119Sgblack@eecs.umich.edu 8477291Sgblack@eecs.umich.edudef template RfeConstructor {{ 8487291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8497291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 8507291Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8517291Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 8527291Sgblack@eecs.umich.edu { 8537291Sgblack@eecs.umich.edu %(constructor)s; 8547291Sgblack@eecs.umich.edu } 8557291Sgblack@eecs.umich.edu}}; 8567291Sgblack@eecs.umich.edu 8577312Sgblack@eecs.umich.edudef template SrsConstructor {{ 8587312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8597312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8607312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8617312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8627312Sgblack@eecs.umich.edu { 8637312Sgblack@eecs.umich.edu %(constructor)s; 8647312Sgblack@eecs.umich.edu } 8657312Sgblack@eecs.umich.edu}}; 8667312Sgblack@eecs.umich.edu 8677205Sgblack@eecs.umich.edudef template SwapConstructor {{ 8687205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8697205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 8707205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8717205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 8727205Sgblack@eecs.umich.edu { 8737205Sgblack@eecs.umich.edu %(constructor)s; 8747205Sgblack@eecs.umich.edu } 8757205Sgblack@eecs.umich.edu}}; 8767205Sgblack@eecs.umich.edu 8777279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 8787279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8797279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 8807279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 8817279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8827279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 8837279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 8847279Sgblack@eecs.umich.edu { 8857279Sgblack@eecs.umich.edu %(constructor)s; 8867279Sgblack@eecs.umich.edu } 8877279Sgblack@eecs.umich.edu}}; 8887279Sgblack@eecs.umich.edu 8897303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 8907303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8917303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 8927303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 8937303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8947303Sgblack@eecs.umich.edu (IntRegIndex)_result, 8957303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 8967303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 8977303Sgblack@eecs.umich.edu { 8987303Sgblack@eecs.umich.edu %(constructor)s; 8997303Sgblack@eecs.umich.edu } 9007303Sgblack@eecs.umich.edu}}; 9017303Sgblack@eecs.umich.edu 9027119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 9037119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9047119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9057119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9067119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9077119Sgblack@eecs.umich.edu { 9087119Sgblack@eecs.umich.edu %(constructor)s; 9097119Sgblack@eecs.umich.edu } 9107119Sgblack@eecs.umich.edu}}; 9117119Sgblack@eecs.umich.edu 9127303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 9137303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9147303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 9157303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 9167303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9177303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 9187303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9197303Sgblack@eecs.umich.edu { 9207303Sgblack@eecs.umich.edu %(constructor)s; 9217303Sgblack@eecs.umich.edu } 9227303Sgblack@eecs.umich.edu}}; 9237303Sgblack@eecs.umich.edu 9247279Sgblack@eecs.umich.edudef template LoadStoreDRegConstructor {{ 9257279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9267279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 9277279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 9287279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9297279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9307279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 9317279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 9327279Sgblack@eecs.umich.edu (IntRegIndex)_index) 9337279Sgblack@eecs.umich.edu { 9347279Sgblack@eecs.umich.edu %(constructor)s; 9357279Sgblack@eecs.umich.edu } 9367279Sgblack@eecs.umich.edu}}; 9377279Sgblack@eecs.umich.edu 9387119Sgblack@eecs.umich.edudef template LoadStoreRegConstructor {{ 9397119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9407119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 9417119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 9427119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9437119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 9447119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 9457119Sgblack@eecs.umich.edu (IntRegIndex)_index) 9467119Sgblack@eecs.umich.edu { 9477119Sgblack@eecs.umich.edu %(constructor)s; 9487119Sgblack@eecs.umich.edu } 9497119Sgblack@eecs.umich.edu}}; 950