mem.isa revision 7639
17860SN/A// -*- mode:c++ -*- 27860SN/A 37860SN/A// Copyright (c) 2010 ARM Limited 49988Snilay@cs.wisc.edu// All rights reserved 58825Snilay@cs.wisc.edu// 69988Snilay@cs.wisc.edu// The license below extends only to copyright in the software and shall 77935SN/A// not be construed as granting a license to any other intellectual 87935SN/A// property including but not limited to intellectual property relating 97935SN/A// to a hardware implementation of the functionality of the software 107860SN/A// licensed hereunder. You may use the software subject to the license 117860SN/A// terms below provided that you ensure that this notice is replicated 127860SN/A// unmodified and in its entirety in all distributions of the software, 1310315Snilay@cs.wisc.edu// modified or unmodified, in source code or in binary form. 148825Snilay@cs.wisc.edu// 159885Sstever@gmail.com// Copyright (c) 2007-2008 The Florida State University 169885Sstever@gmail.com// All rights reserved. 179988Snilay@cs.wisc.edu// 188825Snilay@cs.wisc.edu// Redistribution and use in source and binary forms, with or without 198825Snilay@cs.wisc.edu// modification, are permitted provided that the following conditions are 2010315Snilay@cs.wisc.edu// met: redistributions of source code must retain the above copyright 218825Snilay@cs.wisc.edu// notice, this list of conditions and the following disclaimer; 2210038SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 239449SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 249449SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution; 258464SN/A// neither the name of the copyright holders nor the names of its 2610798Ssteve.reinhardt@amd.com// contributors may be used to endorse or promote products derived from 278660SN/A// this software without specific prior written permission. 288825Snilay@cs.wisc.edu// 298825Snilay@cs.wisc.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307935SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317935SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327935SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337935SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347935SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357935SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367935SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378893Ssaidi@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387860SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399885Sstever@gmail.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409885Sstever@gmail.com// 419885Sstever@gmail.com// Authors: Stephen Hines 4210315Snilay@cs.wisc.edu 439988Snilay@cs.wisc.edu 4410315Snilay@cs.wisc.edudef template SwapExecute {{ 459885Sstever@gmail.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 469885Sstever@gmail.com Trace::InstRecord *traceData) const 477860SN/A { 487860SN/A Addr EA; 4910038SAli.Saidi@ARM.com Fault fault = NoFault; 507860SN/A 5110451Snilay@cs.wisc.edu %(op_decl)s; 528210SN/A uint64_t memData = 0; 5310451Snilay@cs.wisc.edu %(op_rd)s; 5410451Snilay@cs.wisc.edu %(ea_code)s; 557860SN/A 567860SN/A if (%(predicate_test)s) 577860SN/A { 589481Snilay@cs.wisc.edu %(preacc_code)s; 597860SN/A 607860SN/A if (fault == NoFault) { 619885Sstever@gmail.com fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 627860SN/A EA, memAccessFlags, &memData); 637860SN/A } 647860SN/A 657860SN/A if (fault == NoFault) { 667860SN/A %(postacc_code)s; 677860SN/A } 687860SN/A 6910451Snilay@cs.wisc.edu if (fault == NoFault) { 7010451Snilay@cs.wisc.edu %(op_wb)s; 7110451Snilay@cs.wisc.edu } 727860SN/A } else { 738825Snilay@cs.wisc.edu xc->setPredicate(false); 747860SN/A } 7510038SAli.Saidi@ARM.com 767860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 779988Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 7810451Snilay@cs.wisc.edu } 7910451Snilay@cs.wisc.edu 8010451Snilay@cs.wisc.edu return fault; 817860SN/A } 8210451Snilay@cs.wisc.edu}}; 837860SN/A 847860SN/Adef template SwapInitiateAcc {{ 857860SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 867860SN/A Trace::InstRecord *traceData) const 877860SN/A { 887860SN/A Addr EA; 897860SN/A Fault fault = NoFault; 907860SN/A 918825Snilay@cs.wisc.edu %(op_decl)s; 929449SAli.Saidi@ARM.com uint64_t memData = 0; 937860SN/A %(op_rd)s; 947860SN/A %(ea_code)s; 9510038SAli.Saidi@ARM.com 967860SN/A if (%(predicate_test)s) 977860SN/A { 987860SN/A %(preacc_code)s; 997860SN/A 1007860SN/A if (fault == NoFault) { 1018825Snilay@cs.wisc.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 10210451Snilay@cs.wisc.edu memAccessFlags, &memData); 10310451Snilay@cs.wisc.edu } 10410451Snilay@cs.wisc.edu 10510451Snilay@cs.wisc.edu if (fault == NoFault) { 10610451Snilay@cs.wisc.edu %(op_wb)s; 1077860SN/A } 1087860SN/A } else { 1098825Snilay@cs.wisc.edu xc->setPredicate(false); 1107860SN/A } 1117860SN/A 1127860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 11310451Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1147860SN/A } 11510451Snilay@cs.wisc.edu 1169885Sstever@gmail.com return fault; 1177860SN/A } 1187860SN/A}}; 1197860SN/A 1207860SN/Adef template SwapCompleteAcc {{ 1217860SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 1227860SN/A %(CPU_exec_context)s *xc, 1237860SN/A Trace::InstRecord *traceData) const 1247860SN/A { 1257860SN/A Fault fault = NoFault; 12610242Ssteve.reinhardt@amd.com 1277860SN/A %(op_decl)s; 1288521SN/A %(op_rd)s; 1299449SAli.Saidi@ARM.com 1307860SN/A if (%(predicate_test)s) 1317860SN/A { 1327860SN/A // ARM instructions will not have a pkt if the predicate is false 1337860SN/A uint64_t memData = pkt->get<typeof(Mem)>(); 1347860SN/A 1357860SN/A %(postacc_code)s; 1367860SN/A 1377860SN/A if (fault == NoFault) { 1389481Snilay@cs.wisc.edu %(op_wb)s; 13910798Ssteve.reinhardt@amd.com } 14010451Snilay@cs.wisc.edu } 14110451Snilay@cs.wisc.edu 1429481Snilay@cs.wisc.edu if (fault == NoFault && machInst.itstateMask != 0) { 1439481Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1449481Snilay@cs.wisc.edu } 1459988Snilay@cs.wisc.edu 1469481Snilay@cs.wisc.edu return fault; 1479481Snilay@cs.wisc.edu } 1489481Snilay@cs.wisc.edu}}; 1499481Snilay@cs.wisc.edu 1509481Snilay@cs.wisc.edudef template LoadExecute {{ 1517860SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1527860SN/A Trace::InstRecord *traceData) const 1539885Sstever@gmail.com { 1548893Ssaidi@eecs.umich.edu Addr EA; 1557860SN/A Fault fault = NoFault; 1569885Sstever@gmail.com 15710636Snilay@cs.wisc.edu %(op_decl)s; 1589988Snilay@cs.wisc.edu %(op_rd)s; 1597860SN/A %(ea_code)s; 1609348SAli.Saidi@ARM.com 16110900Snilay@cs.wisc.edu if (%(predicate_test)s) 1627860SN/A { 16310451Snilay@cs.wisc.edu if (fault == NoFault) { 1647860SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1658835SAli.Saidi@ARM.com %(memacc_code)s; 1669348SAli.Saidi@ARM.com } 16710036SAli.Saidi@ARM.com 16810451Snilay@cs.wisc.edu if (fault == NoFault) { 1698835SAli.Saidi@ARM.com %(op_wb)s; 1709885Sstever@gmail.com } 17110451Snilay@cs.wisc.edu } else { 17210451Snilay@cs.wisc.edu xc->setPredicate(false); 1737860SN/A } 1748893Ssaidi@eecs.umich.edu 1757860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 1769885Sstever@gmail.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1779885Sstever@gmail.com } 1789885Sstever@gmail.com 1799885Sstever@gmail.com return fault; 1809885Sstever@gmail.com } 1819988Snilay@cs.wisc.edu}}; 1829885Sstever@gmail.com 18310036SAli.Saidi@ARM.comdef template NeonLoadExecute {{ 18410451Snilay@cs.wisc.edu template <class Element> 1859885Sstever@gmail.com Fault %(class_name)s<Element>::execute( 18610038SAli.Saidi@ARM.com %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 18710038SAli.Saidi@ARM.com { 18810038SAli.Saidi@ARM.com Addr EA; 18910038SAli.Saidi@ARM.com Fault fault = NoFault; 19010038SAli.Saidi@ARM.com 19110798Ssteve.reinhardt@amd.com %(op_decl)s; 19210038SAli.Saidi@ARM.com %(mem_decl)s; 19310038SAli.Saidi@ARM.com %(op_rd)s; 19410038SAli.Saidi@ARM.com %(ea_code)s; 19510038SAli.Saidi@ARM.com 19610038SAli.Saidi@ARM.com MemUnion memUnion; 19710038SAli.Saidi@ARM.com uint8_t *dataPtr = memUnion.bytes; 19810038SAli.Saidi@ARM.com 19910038SAli.Saidi@ARM.com if (%(predicate_test)s) 20010038SAli.Saidi@ARM.com { 20110038SAli.Saidi@ARM.com if (fault == NoFault) { 20210038SAli.Saidi@ARM.com fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 20310038SAli.Saidi@ARM.com %(memacc_code)s; 20410038SAli.Saidi@ARM.com } 20510038SAli.Saidi@ARM.com 20610038SAli.Saidi@ARM.com if (fault == NoFault) { 20710038SAli.Saidi@ARM.com %(op_wb)s; 20810038SAli.Saidi@ARM.com } 20910038SAli.Saidi@ARM.com } 2107860SN/A 2117860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 2128825Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2139988Snilay@cs.wisc.edu } 21410038SAli.Saidi@ARM.com 2157860SN/A return fault; 2168825Snilay@cs.wisc.edu } 2178825Snilay@cs.wisc.edu}}; 2188825Snilay@cs.wisc.edu 2198825Snilay@cs.wisc.edudef template StoreExecute {{ 2209885Sstever@gmail.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2219988Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 22210038SAli.Saidi@ARM.com { 2239265SAli.Saidi@ARM.com Addr EA; 2248825Snilay@cs.wisc.edu Fault fault = NoFault; 2258893Ssaidi@eecs.umich.edu 2267860SN/A %(op_decl)s; 2277860SN/A %(op_rd)s; 2287860SN/A %(ea_code)s; 22910451Snilay@cs.wisc.edu 23010451Snilay@cs.wisc.edu if (%(predicate_test)s) 2319988Snilay@cs.wisc.edu { 2327860SN/A if (fault == NoFault) { 2337860SN/A %(memacc_code)s; 2347860SN/A } 2357860SN/A 23610451Snilay@cs.wisc.edu if (fault == NoFault) { 2379988Snilay@cs.wisc.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2387860SN/A memAccessFlags, NULL); 2397860SN/A } 2407860SN/A 2417860SN/A if (fault == NoFault) { 2429988Snilay@cs.wisc.edu %(op_wb)s; 2437860SN/A } 2447860SN/A } else { 24510900Snilay@cs.wisc.edu xc->setPredicate(false); 2467860SN/A } 2477860SN/A 2487860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 24910451Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 25010451Snilay@cs.wisc.edu } 2519988Snilay@cs.wisc.edu 25210451Snilay@cs.wisc.edu return fault; 2537860SN/A } 2547860SN/A}}; 2557860SN/A 2569988Snilay@cs.wisc.edudef template NeonStoreExecute {{ 2577860SN/A template <class Element> 2587860SN/A Fault %(class_name)s<Element>::execute( 25910900Snilay@cs.wisc.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2607860SN/A { 2617860SN/A Addr EA; 2627860SN/A Fault fault = NoFault; 2639988Snilay@cs.wisc.edu 2647860SN/A %(op_decl)s; 26510451Snilay@cs.wisc.edu %(mem_decl)s; 26610900Snilay@cs.wisc.edu %(op_rd)s; 26710451Snilay@cs.wisc.edu %(ea_code)s; 26810451Snilay@cs.wisc.edu 26910451Snilay@cs.wisc.edu MemUnion memUnion; 27010451Snilay@cs.wisc.edu uint8_t *dataPtr = memUnion.bytes; 27110451Snilay@cs.wisc.edu 27210451Snilay@cs.wisc.edu if (%(predicate_test)s) 27310900Snilay@cs.wisc.edu { 2747860SN/A if (fault == NoFault) { 2757860SN/A %(memacc_code)s; 2767860SN/A } 27710451Snilay@cs.wisc.edu 27810451Snilay@cs.wisc.edu if (fault == NoFault) { 2799988Snilay@cs.wisc.edu fault = xc->writeBytes(dataPtr, %(size)d, EA, 28010451Snilay@cs.wisc.edu memAccessFlags, NULL); 2817860SN/A } 28210451Snilay@cs.wisc.edu 2837860SN/A if (fault == NoFault) { 2849988Snilay@cs.wisc.edu %(op_wb)s; 28510451Snilay@cs.wisc.edu } 2867860SN/A } 28710900Snilay@cs.wisc.edu 2887860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 2897860SN/A xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2907860SN/A } 29110451Snilay@cs.wisc.edu 29210451Snilay@cs.wisc.edu return fault; 2939988Snilay@cs.wisc.edu } 29410451Snilay@cs.wisc.edu}}; 2957860SN/A 29610451Snilay@cs.wisc.edudef template StoreExExecute {{ 2977860SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2989988Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 29910451Snilay@cs.wisc.edu { 30010451Snilay@cs.wisc.edu Addr EA; 30110900Snilay@cs.wisc.edu Fault fault = NoFault; 3027860SN/A 3037860SN/A %(op_decl)s; 3047860SN/A %(op_rd)s; 30510451Snilay@cs.wisc.edu %(ea_code)s; 30610451Snilay@cs.wisc.edu 3079988Snilay@cs.wisc.edu if (%(predicate_test)s) 30810451Snilay@cs.wisc.edu { 3097860SN/A if (fault == NoFault) { 31010451Snilay@cs.wisc.edu %(memacc_code)s; 3117860SN/A } 3129988Snilay@cs.wisc.edu 3137860SN/A uint64_t writeResult; 31410451Snilay@cs.wisc.edu 31510900Snilay@cs.wisc.edu if (fault == NoFault) { 3167860SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 31710451Snilay@cs.wisc.edu memAccessFlags, &writeResult); 3187860SN/A } 3199988Snilay@cs.wisc.edu 3207860SN/A if (fault == NoFault) { 32110451Snilay@cs.wisc.edu %(postacc_code)s; 32210900Snilay@cs.wisc.edu } 3237860SN/A 32410451Snilay@cs.wisc.edu if (fault == NoFault) { 3257860SN/A %(op_wb)s; 3269988Snilay@cs.wisc.edu } 3277860SN/A } else { 32810451Snilay@cs.wisc.edu xc->setPredicate(false); 32910900Snilay@cs.wisc.edu } 3307860SN/A 33110451Snilay@cs.wisc.edu if (fault == NoFault && machInst.itstateMask != 0) { 3327860SN/A xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3339988Snilay@cs.wisc.edu } 3347860SN/A 33510451Snilay@cs.wisc.edu return fault; 33610900Snilay@cs.wisc.edu } 3377860SN/A}}; 33810451Snilay@cs.wisc.edu 3397860SN/Adef template StoreExInitiateAcc {{ 3409988Snilay@cs.wisc.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3417860SN/A Trace::InstRecord *traceData) const 34210451Snilay@cs.wisc.edu { 34310900Snilay@cs.wisc.edu Addr EA; 3447860SN/A Fault fault = NoFault; 34510451Snilay@cs.wisc.edu 3467860SN/A %(op_decl)s; 3479988Snilay@cs.wisc.edu %(op_rd)s; 3487860SN/A %(ea_code)s; 34910451Snilay@cs.wisc.edu 35010900Snilay@cs.wisc.edu if (%(predicate_test)s) 3517860SN/A { 35210451Snilay@cs.wisc.edu if (fault == NoFault) { 3537860SN/A %(memacc_code)s; 3549988Snilay@cs.wisc.edu } 3557860SN/A 35610451Snilay@cs.wisc.edu if (fault == NoFault) { 35710900Snilay@cs.wisc.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3587860SN/A memAccessFlags, NULL); 35910451Snilay@cs.wisc.edu } 3607860SN/A 3619988Snilay@cs.wisc.edu // Need to write back any potential address register update 3627860SN/A if (fault == NoFault) { 36310451Snilay@cs.wisc.edu %(op_wb)s; 36410900Snilay@cs.wisc.edu } 3657860SN/A } else { 36610451Snilay@cs.wisc.edu xc->setPredicate(false); 3677860SN/A } 3689988Snilay@cs.wisc.edu 3697860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 37010451Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 37110900Snilay@cs.wisc.edu } 3727860SN/A 37310451Snilay@cs.wisc.edu return fault; 3747860SN/A } 3759988Snilay@cs.wisc.edu}}; 3767860SN/A 37710451Snilay@cs.wisc.edudef template StoreInitiateAcc {{ 37810900Snilay@cs.wisc.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3797860SN/A Trace::InstRecord *traceData) const 38010451Snilay@cs.wisc.edu { 3817860SN/A Addr EA; 3829988Snilay@cs.wisc.edu Fault fault = NoFault; 3837860SN/A 38410451Snilay@cs.wisc.edu %(op_decl)s; 38510900Snilay@cs.wisc.edu %(op_rd)s; 3867860SN/A %(ea_code)s; 38710451Snilay@cs.wisc.edu 3887860SN/A if (%(predicate_test)s) 3899988Snilay@cs.wisc.edu { 3907860SN/A if (fault == NoFault) { 39110451Snilay@cs.wisc.edu %(memacc_code)s; 39210900Snilay@cs.wisc.edu } 3937860SN/A 39410451Snilay@cs.wisc.edu if (fault == NoFault) { 3957860SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3969988Snilay@cs.wisc.edu memAccessFlags, NULL); 3977860SN/A } 39810451Snilay@cs.wisc.edu 39910900Snilay@cs.wisc.edu // Need to write back any potential address register update 4007860SN/A if (fault == NoFault) { 40110451Snilay@cs.wisc.edu %(op_wb)s; 4027860SN/A } 4039988Snilay@cs.wisc.edu } else { 4047860SN/A xc->setPredicate(false); 40510451Snilay@cs.wisc.edu } 40610900Snilay@cs.wisc.edu 4077860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 40810451Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4097860SN/A } 4109988Snilay@cs.wisc.edu 4117860SN/A return fault; 41210451Snilay@cs.wisc.edu } 41310900Snilay@cs.wisc.edu}}; 4147860SN/A 41510451Snilay@cs.wisc.edudef template NeonStoreInitiateAcc {{ 4167860SN/A template <class Element> 4179988Snilay@cs.wisc.edu Fault %(class_name)s<Element>::initiateAcc( 4187860SN/A %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 41910451Snilay@cs.wisc.edu { 42010900Snilay@cs.wisc.edu Addr EA; 4217860SN/A Fault fault = NoFault; 42210451Snilay@cs.wisc.edu 4237860SN/A %(op_decl)s; 4249988Snilay@cs.wisc.edu %(mem_decl)s; 4257860SN/A %(op_rd)s; 42610451Snilay@cs.wisc.edu %(ea_code)s; 42710900Snilay@cs.wisc.edu 4287860SN/A if (%(predicate_test)s) 42910451Snilay@cs.wisc.edu { 4307860SN/A MemUnion memUnion; 4319988Snilay@cs.wisc.edu if (fault == NoFault) { 4327860SN/A %(memacc_code)s; 43310451Snilay@cs.wisc.edu } 43410900Snilay@cs.wisc.edu 4357860SN/A if (fault == NoFault) { 43610451Snilay@cs.wisc.edu fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 4377860SN/A memAccessFlags, NULL); 4389988Snilay@cs.wisc.edu } 4397860SN/A 4407860SN/A // Need to write back any potential address register update 44110900Snilay@cs.wisc.edu if (fault == NoFault) { 4427860SN/A %(op_wb)s; 44310451Snilay@cs.wisc.edu } 4447860SN/A } 4459988Snilay@cs.wisc.edu 4467860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 44710451Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 44810900Snilay@cs.wisc.edu } 4497860SN/A 45010451Snilay@cs.wisc.edu return fault; 4517860SN/A } 4529988Snilay@cs.wisc.edu}}; 45310451Snilay@cs.wisc.edu 45410451Snilay@cs.wisc.edudef template LoadInitiateAcc {{ 45510900Snilay@cs.wisc.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4567860SN/A Trace::InstRecord *traceData) const 45710451Snilay@cs.wisc.edu { 4587860SN/A Addr EA; 4599988Snilay@cs.wisc.edu Fault fault = NoFault; 46010451Snilay@cs.wisc.edu 46110451Snilay@cs.wisc.edu %(op_src_decl)s; 46210900Snilay@cs.wisc.edu %(op_rd)s; 4637860SN/A %(ea_code)s; 46410451Snilay@cs.wisc.edu 4657860SN/A if (%(predicate_test)s) 4669988Snilay@cs.wisc.edu { 46710451Snilay@cs.wisc.edu if (fault == NoFault) { 46810451Snilay@cs.wisc.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 46910900Snilay@cs.wisc.edu } 4707860SN/A } else { 47110451Snilay@cs.wisc.edu xc->setPredicate(false); 4727860SN/A if (fault == NoFault && machInst.itstateMask != 0) { 4739988Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 47410451Snilay@cs.wisc.edu } 47510451Snilay@cs.wisc.edu } 47610900Snilay@cs.wisc.edu 47710451Snilay@cs.wisc.edu return fault; 47810451Snilay@cs.wisc.edu } 47910451Snilay@cs.wisc.edu}}; 48010451Snilay@cs.wisc.edu 48110451Snilay@cs.wisc.edudef template NeonLoadInitiateAcc {{ 48210451Snilay@cs.wisc.edu template <class Element> 48310900Snilay@cs.wisc.edu Fault %(class_name)s<Element>::initiateAcc( 48410451Snilay@cs.wisc.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 48510451Snilay@cs.wisc.edu { 48610451Snilay@cs.wisc.edu Addr EA; 48710451Snilay@cs.wisc.edu Fault fault = NoFault; 48810451Snilay@cs.wisc.edu 48910451Snilay@cs.wisc.edu %(op_src_decl)s; 49010900Snilay@cs.wisc.edu %(op_rd)s; 4917860SN/A %(ea_code)s; 4927860SN/A 4937860SN/A if (%(predicate_test)s) 4949885Sstever@gmail.com { 4958893Ssaidi@eecs.umich.edu if (fault == NoFault) { 4967860SN/A fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 4979885Sstever@gmail.com } 49810636Snilay@cs.wisc.edu } else if (fault == NoFault && machInst.itstateMask != 0) { 4999988Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 50010798Ssteve.reinhardt@amd.com } 50110451Snilay@cs.wisc.edu 50210900Snilay@cs.wisc.edu return fault; 5037860SN/A } 50410451Snilay@cs.wisc.edu}}; 5057860SN/A 5068835SAli.Saidi@ARM.comdef template LoadCompleteAcc {{ 50710451Snilay@cs.wisc.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 50810036SAli.Saidi@ARM.com %(CPU_exec_context)s *xc, 50910451Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 5108835SAli.Saidi@ARM.com { 5119885Sstever@gmail.com Fault fault = NoFault; 51210451Snilay@cs.wisc.edu 5137860SN/A %(op_decl)s; 5147860SN/A %(op_rd)s; 5158893Ssaidi@eecs.umich.edu 5167860SN/A if (%(predicate_test)s) 5179885Sstever@gmail.com { 5189885Sstever@gmail.com // ARM instructions will not have a pkt if the predicate is false 5199885Sstever@gmail.com Mem = pkt->get<typeof(Mem)>(); 5209885Sstever@gmail.com 5219885Sstever@gmail.com if (fault == NoFault) { 5229988Snilay@cs.wisc.edu %(memacc_code)s; 52310451Snilay@cs.wisc.edu } 52410036SAli.Saidi@ARM.com 52510451Snilay@cs.wisc.edu if (fault == NoFault) { 5269885Sstever@gmail.com %(op_wb)s; 5278825Snilay@cs.wisc.edu } 5288825Snilay@cs.wisc.edu } 5299988Snilay@cs.wisc.edu 5308825Snilay@cs.wisc.edu if (fault == NoFault && machInst.itstateMask != 0) { 5319449SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5329449SAli.Saidi@ARM.com } 5339988Snilay@cs.wisc.edu 5349449SAli.Saidi@ARM.com return fault; 53510038SAli.Saidi@ARM.com } 53610038SAli.Saidi@ARM.com}}; 53710038SAli.Saidi@ARM.com 53810038SAli.Saidi@ARM.comdef template NeonLoadCompleteAcc {{ 53910038SAli.Saidi@ARM.com template <class Element> 54010038SAli.Saidi@ARM.com Fault %(class_name)s<Element>::completeAcc( 54110038SAli.Saidi@ARM.com PacketPtr pkt, %(CPU_exec_context)s *xc, 54210038SAli.Saidi@ARM.com Trace::InstRecord *traceData) const 54310038SAli.Saidi@ARM.com { 54410038SAli.Saidi@ARM.com Fault fault = NoFault; 5459449SAli.Saidi@ARM.com 5469449SAli.Saidi@ARM.com %(mem_decl)s; 5479449SAli.Saidi@ARM.com %(op_decl)s; 5489449SAli.Saidi@ARM.com %(op_rd)s; 5499449SAli.Saidi@ARM.com 5509449SAli.Saidi@ARM.com if (%(predicate_test)s) 55110038SAli.Saidi@ARM.com { 5529449SAli.Saidi@ARM.com // ARM instructions will not have a pkt if the predicate is false 5539449SAli.Saidi@ARM.com MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 55410038SAli.Saidi@ARM.com 5559449SAli.Saidi@ARM.com if (fault == NoFault) { 55610038SAli.Saidi@ARM.com %(memacc_code)s; 55710038SAli.Saidi@ARM.com } 55810636Snilay@cs.wisc.edu 55910038SAli.Saidi@ARM.com if (fault == NoFault) { 56010038SAli.Saidi@ARM.com %(op_wb)s; 56110038SAli.Saidi@ARM.com } 56210038SAli.Saidi@ARM.com } 56310038SAli.Saidi@ARM.com 56410038SAli.Saidi@ARM.com if (fault == NoFault && machInst.itstateMask != 0) { 56510038SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 56610798Ssteve.reinhardt@amd.com } 56710038SAli.Saidi@ARM.com 56810038SAli.Saidi@ARM.com return fault; 56910038SAli.Saidi@ARM.com } 57010038SAli.Saidi@ARM.com}}; 57110038SAli.Saidi@ARM.com 57210038SAli.Saidi@ARM.comdef template StoreCompleteAcc {{ 57310038SAli.Saidi@ARM.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 57410038SAli.Saidi@ARM.com %(CPU_exec_context)s *xc, 57510038SAli.Saidi@ARM.com Trace::InstRecord *traceData) const 57610038SAli.Saidi@ARM.com { 57710038SAli.Saidi@ARM.com Fault fault = NoFault; 57810038SAli.Saidi@ARM.com 57910038SAli.Saidi@ARM.com %(op_decl)s; 58010038SAli.Saidi@ARM.com %(op_rd)s; 58110038SAli.Saidi@ARM.com 58210038SAli.Saidi@ARM.com if (%(predicate_test)s) 58310038SAli.Saidi@ARM.com { 5849449SAli.Saidi@ARM.com if (fault == NoFault) { 5857860SN/A %(op_wb)s; 5867860SN/A } 5878825Snilay@cs.wisc.edu } 5889988Snilay@cs.wisc.edu 58910038SAli.Saidi@ARM.com if (fault == NoFault && machInst.itstateMask != 0) { 5907860SN/A xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5918825Snilay@cs.wisc.edu } 5928825Snilay@cs.wisc.edu 5938825Snilay@cs.wisc.edu return fault; 5948825Snilay@cs.wisc.edu } 5959885Sstever@gmail.com}}; 5969988Snilay@cs.wisc.edu 59710038SAli.Saidi@ARM.comdef template NeonStoreCompleteAcc {{ 5989265SAli.Saidi@ARM.com template <class Element> 5998825Snilay@cs.wisc.edu Fault %(class_name)s<Element>::completeAcc( 6008893Ssaidi@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 6017860SN/A Trace::InstRecord *traceData) const 6027860SN/A { 6037860SN/A Fault fault = NoFault; 60410451Snilay@cs.wisc.edu 6058893Ssaidi@eecs.umich.edu %(op_decl)s; 60610451Snilay@cs.wisc.edu %(op_rd)s; 6079885Sstever@gmail.com 60810636Snilay@cs.wisc.edu if (%(predicate_test)s) 6099988Snilay@cs.wisc.edu { 6107860SN/A if (fault == NoFault) { 61110451Snilay@cs.wisc.edu %(op_wb)s; 61210900Snilay@cs.wisc.edu } 6137860SN/A } 61410451Snilay@cs.wisc.edu 61510451Snilay@cs.wisc.edu if (fault == NoFault && machInst.itstateMask != 0) { 61610451Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 61710451Snilay@cs.wisc.edu } 61810036SAli.Saidi@ARM.com 61910451Snilay@cs.wisc.edu return fault; 6208835SAli.Saidi@ARM.com } 6219885Sstever@gmail.com}}; 62210451Snilay@cs.wisc.edu 6237860SN/Adef template StoreExCompleteAcc {{ 6248893Ssaidi@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6258893Ssaidi@eecs.umich.edu %(CPU_exec_context)s *xc, 6267860SN/A Trace::InstRecord *traceData) const 62710451Snilay@cs.wisc.edu { 62810451Snilay@cs.wisc.edu Fault fault = NoFault; 62910636Snilay@cs.wisc.edu 63010451Snilay@cs.wisc.edu %(op_decl)s; 63110451Snilay@cs.wisc.edu %(op_rd)s; 63210451Snilay@cs.wisc.edu 63310451Snilay@cs.wisc.edu if (%(predicate_test)s) 63410636Snilay@cs.wisc.edu { 63510636Snilay@cs.wisc.edu uint64_t writeResult = pkt->req->getExtraData(); 63610636Snilay@cs.wisc.edu %(postacc_code)s; 63710636Snilay@cs.wisc.edu 63810636Snilay@cs.wisc.edu if (fault == NoFault) { 63910636Snilay@cs.wisc.edu %(op_wb)s; 64010636Snilay@cs.wisc.edu } 64110636Snilay@cs.wisc.edu } 64210636Snilay@cs.wisc.edu 64310636Snilay@cs.wisc.edu if (fault == NoFault && machInst.itstateMask != 0) { 64410636Snilay@cs.wisc.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 64510451Snilay@cs.wisc.edu } 64610636Snilay@cs.wisc.edu 64710636Snilay@cs.wisc.edu return fault; 64810636Snilay@cs.wisc.edu } 64910636Snilay@cs.wisc.edu}}; 65010451Snilay@cs.wisc.edu 65110451Snilay@cs.wisc.edudef template RfeDeclare {{ 6529885Sstever@gmail.com /** 65310451Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 65410451Snilay@cs.wisc.edu */ 6559885Sstever@gmail.com class %(class_name)s : public %(base_class)s 6569885Sstever@gmail.com { 6579988Snilay@cs.wisc.edu public: 65810451Snilay@cs.wisc.edu 65910036SAli.Saidi@ARM.com /// Constructor. 66010451Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 6619885Sstever@gmail.com uint32_t _base, int _mode, bool _wb); 6627860SN/A 66310451Snilay@cs.wisc.edu %(BasicExecDeclare)s 6649885Sstever@gmail.com 6659988Snilay@cs.wisc.edu %(InitiateAccDeclare)s 66610798Ssteve.reinhardt@amd.com 66710798Ssteve.reinhardt@amd.com %(CompleteAccDeclare)s 66810798Ssteve.reinhardt@amd.com }; 66910451Snilay@cs.wisc.edu}}; 67010798Ssteve.reinhardt@amd.com 6719536SAli.Saidi@ARM.comdef template SrsDeclare {{ 6727860SN/A /** 6739348SAli.Saidi@ARM.com * Static instruction class for "%(mnemonic)s". 6748893Ssaidi@eecs.umich.edu */ 67510798Ssteve.reinhardt@amd.com class %(class_name)s : public %(base_class)s 6767860SN/A { 6777860SN/A public: 6787860SN/A 6799988Snilay@cs.wisc.edu /// Constructor. 6807860SN/A %(class_name)s(ExtMachInst machInst, 6817860SN/A uint32_t _regMode, int _mode, bool _wb); 6827860SN/A 6837860SN/A %(BasicExecDeclare)s 6849134Ssaidi@eecs.umich.edu 68510636Snilay@cs.wisc.edu %(InitiateAccDeclare)s 6867860SN/A 6877860SN/A %(CompleteAccDeclare)s 6887860SN/A }; 6897860SN/A}}; 6909988Snilay@cs.wisc.edu 69110798Ssteve.reinhardt@amd.comdef template SwapDeclare {{ 6927860SN/A /** 69310798Ssteve.reinhardt@amd.com * Static instruction class for "%(mnemonic)s". 69410636Snilay@cs.wisc.edu */ 6957860SN/A class %(class_name)s : public %(base_class)s 6967860SN/A { 6977860SN/A public: 6987860SN/A 6997860SN/A /// Constructor. 7007860SN/A %(class_name)s(ExtMachInst machInst, 7017860SN/A uint32_t _dest, uint32_t _op1, uint32_t _base); 70210451Snilay@cs.wisc.edu 7037860SN/A %(BasicExecDeclare)s 7049885Sstever@gmail.com 7059885Sstever@gmail.com %(InitiateAccDeclare)s 7069885Sstever@gmail.com 70710315Snilay@cs.wisc.edu %(CompleteAccDeclare)s 7089988Snilay@cs.wisc.edu }; 70910315Snilay@cs.wisc.edu}}; 7109885Sstever@gmail.com 7119885Sstever@gmail.comdef template LoadStoreDImmDeclare {{ 71210315Snilay@cs.wisc.edu /** 71310315Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 71410315Snilay@cs.wisc.edu */ 71510315Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 71610315Snilay@cs.wisc.edu { 71710315Snilay@cs.wisc.edu public: 71810315Snilay@cs.wisc.edu 71910315Snilay@cs.wisc.edu /// Constructor. 7207860SN/A %(class_name)s(ExtMachInst machInst, 72110451Snilay@cs.wisc.edu uint32_t _dest, uint32_t _dest2, 7229885Sstever@gmail.com uint32_t _base, bool _add, int32_t _imm); 7239988Snilay@cs.wisc.edu 72410798Ssteve.reinhardt@amd.com %(BasicExecDeclare)s 72510798Ssteve.reinhardt@amd.com 72610798Ssteve.reinhardt@amd.com %(InitiateAccDeclare)s 72710451Snilay@cs.wisc.edu 72810798Ssteve.reinhardt@amd.com %(CompleteAccDeclare)s 7299536SAli.Saidi@ARM.com }; 7307860SN/A}}; 73110798Ssteve.reinhardt@amd.com 7329134Ssaidi@eecs.umich.edudef template StoreExDImmDeclare {{ 7338893Ssaidi@eecs.umich.edu /** 7347860SN/A * Static instruction class for "%(mnemonic)s". 7357860SN/A */ 73610242Ssteve.reinhardt@amd.com class %(class_name)s : public %(base_class)s 73710451Snilay@cs.wisc.edu { 73810451Snilay@cs.wisc.edu public: 73910451Snilay@cs.wisc.edu 74010451Snilay@cs.wisc.edu /// Constructor. 74110451Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 74210451Snilay@cs.wisc.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 74310451Snilay@cs.wisc.edu uint32_t _base, bool _add, int32_t _imm); 74410451Snilay@cs.wisc.edu 74510451Snilay@cs.wisc.edu %(BasicExecDeclare)s 74610451Snilay@cs.wisc.edu 74710451Snilay@cs.wisc.edu %(InitiateAccDeclare)s 74810451Snilay@cs.wisc.edu 74910451Snilay@cs.wisc.edu %(CompleteAccDeclare)s 75010451Snilay@cs.wisc.edu }; 75110451Snilay@cs.wisc.edu}}; 75210451Snilay@cs.wisc.edu 75310451Snilay@cs.wisc.edudef template LoadStoreImmDeclare {{ 75410451Snilay@cs.wisc.edu /** 75510451Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 75610451Snilay@cs.wisc.edu */ 75710451Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 75810451Snilay@cs.wisc.edu { 75910451Snilay@cs.wisc.edu public: 76010451Snilay@cs.wisc.edu 7619536SAli.Saidi@ARM.com /// Constructor. 76210798Ssteve.reinhardt@amd.com %(class_name)s(ExtMachInst machInst, 76310451Snilay@cs.wisc.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 7649348SAli.Saidi@ARM.com 7659885Sstever@gmail.com %(BasicExecDeclare)s 7669575Ssaidi@eecs.umich.edu 7679885Sstever@gmail.com %(InitiateAccDeclare)s 7689885Sstever@gmail.com 7699885Sstever@gmail.com %(CompleteAccDeclare)s 7709885Sstever@gmail.com }; 77110636Snilay@cs.wisc.edu}}; 7729885Sstever@gmail.com 77310451Snilay@cs.wisc.edudef template StoreExImmDeclare {{ 7749988Snilay@cs.wisc.edu /** 7758983Snate@binkert.org * Static instruction class for "%(mnemonic)s". 77610242Ssteve.reinhardt@amd.com */ 7779536SAli.Saidi@ARM.com class %(class_name)s : public %(base_class)s 77810242Ssteve.reinhardt@amd.com { 7797860SN/A public: 78010242Ssteve.reinhardt@amd.com 7817860SN/A /// Constructor. 7829348SAli.Saidi@ARM.com %(class_name)s(ExtMachInst machInst, 7839348SAli.Saidi@ARM.com uint32_t _result, uint32_t _dest, uint32_t _base, 7849885Sstever@gmail.com bool _add, int32_t _imm); 7859885Sstever@gmail.com 7869536SAli.Saidi@ARM.com %(BasicExecDeclare)s 78710451Snilay@cs.wisc.edu 78810242Ssteve.reinhardt@amd.com %(InitiateAccDeclare)s 7899536SAli.Saidi@ARM.com 79010451Snilay@cs.wisc.edu %(CompleteAccDeclare)s 7919988Snilay@cs.wisc.edu }; 7929536SAli.Saidi@ARM.com}}; 7939348SAli.Saidi@ARM.com 79410242Ssteve.reinhardt@amd.comdef template LoadStoreDRegDeclare {{ 7959536SAli.Saidi@ARM.com /** 79610242Ssteve.reinhardt@amd.com * Static instruction class for "%(mnemonic)s". 79710451Snilay@cs.wisc.edu */ 79810242Ssteve.reinhardt@amd.com class %(class_name)s : public %(base_class)s 79910242Ssteve.reinhardt@amd.com { 80010242Ssteve.reinhardt@amd.com public: 8019536SAli.Saidi@ARM.com 80210242Ssteve.reinhardt@amd.com /// Constructor. 80310451Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 80410451Snilay@cs.wisc.edu uint32_t _dest, uint32_t _dest2, 80510451Snilay@cs.wisc.edu uint32_t _base, bool _add, 80610451Snilay@cs.wisc.edu int32_t _shiftAmt, uint32_t _shiftType, 80710242Ssteve.reinhardt@amd.com uint32_t _index); 80810242Ssteve.reinhardt@amd.com 80910242Ssteve.reinhardt@amd.com %(BasicExecDeclare)s 8108893Ssaidi@eecs.umich.edu 8117860SN/A %(InitiateAccDeclare)s 8129885Sstever@gmail.com 8139885Sstever@gmail.com %(CompleteAccDeclare)s 8149988Snilay@cs.wisc.edu }; 8159885Sstever@gmail.com}}; 8169885Sstever@gmail.com 817def template LoadStoreRegDeclare {{ 818 /** 819 * Static instruction class for "%(mnemonic)s". 820 */ 821 class %(class_name)s : public %(base_class)s 822 { 823 public: 824 825 /// Constructor. 826 %(class_name)s(ExtMachInst machInst, 827 uint32_t _dest, uint32_t _base, bool _add, 828 int32_t _shiftAmt, uint32_t _shiftType, 829 uint32_t _index); 830 831 %(BasicExecDeclare)s 832 833 %(InitiateAccDeclare)s 834 835 %(CompleteAccDeclare)s 836 }; 837}}; 838 839def template InitiateAccDeclare {{ 840 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 841}}; 842 843def template CompleteAccDeclare {{ 844 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 845}}; 846 847def template RfeConstructor {{ 848 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 849 uint32_t _base, int _mode, bool _wb) 850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 851 (IntRegIndex)_base, (AddrMode)_mode, _wb) 852 { 853 %(constructor)s; 854 } 855}}; 856 857def template SrsConstructor {{ 858 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 859 uint32_t _regMode, int _mode, bool _wb) 860 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 861 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 862 { 863 %(constructor)s; 864 } 865}}; 866 867def template SwapConstructor {{ 868 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 869 uint32_t _dest, uint32_t _op1, uint32_t _base) 870 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 871 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 872 { 873 %(constructor)s; 874 } 875}}; 876 877def template LoadStoreDImmConstructor {{ 878 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 879 uint32_t _dest, uint32_t _dest2, 880 uint32_t _base, bool _add, int32_t _imm) 881 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 882 (IntRegIndex)_dest, (IntRegIndex)_dest2, 883 (IntRegIndex)_base, _add, _imm) 884 { 885 %(constructor)s; 886 } 887}}; 888 889def template StoreExDImmConstructor {{ 890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 891 uint32_t _result, uint32_t _dest, uint32_t _dest2, 892 uint32_t _base, bool _add, int32_t _imm) 893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 894 (IntRegIndex)_result, 895 (IntRegIndex)_dest, (IntRegIndex)_dest2, 896 (IntRegIndex)_base, _add, _imm) 897 { 898 %(constructor)s; 899 } 900}}; 901 902def template LoadStoreImmConstructor {{ 903 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 904 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 905 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 906 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 907 { 908 %(constructor)s; 909 } 910}}; 911 912def template StoreExImmConstructor {{ 913 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 914 uint32_t _result, uint32_t _dest, uint32_t _base, 915 bool _add, int32_t _imm) 916 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 917 (IntRegIndex)_result, (IntRegIndex)_dest, 918 (IntRegIndex)_base, _add, _imm) 919 { 920 %(constructor)s; 921 } 922}}; 923 924def template LoadStoreDRegConstructor {{ 925 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 926 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 927 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 928 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 929 (IntRegIndex)_dest, (IntRegIndex)_dest2, 930 (IntRegIndex)_base, _add, 931 _shiftAmt, (ArmShiftType)_shiftType, 932 (IntRegIndex)_index) 933 { 934 %(constructor)s; 935 } 936}}; 937 938def template LoadStoreRegConstructor {{ 939 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 940 uint32_t _dest, uint32_t _base, bool _add, 941 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 942 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 943 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 944 _shiftAmt, (ArmShiftType)_shiftType, 945 (IntRegIndex)_index) 946 { 947 %(constructor)s; 948 } 949}}; 950