misc64.isa revision 10474:799c8ee4ecba 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2013 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41    svcCode = '''
42    fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5));
43    '''
44
45    svcIop = InstObjParams("svc", "Svc64", "ArmStaticInst",
46                           svcCode, ["IsSyscall", "IsNonSpeculative",
47                                     "IsSerializeAfter"])
48    header_output = BasicDeclare.subst(svcIop)
49    decoder_output = BasicConstructor64.subst(svcIop)
50    exec_output = BasicExecute.subst(svcIop)
51
52    # @todo: extend to take into account Virtualization.
53    smcCode = '''
54    SCR scr = Scr64;
55    CPSR cpsr = Cpsr;
56
57    if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) {
58        fault = disabledFault();
59    } else {
60        fault = std::make_shared<SecureMonitorCall>(machInst);
61    }
62    '''
63
64    smcIop = InstObjParams("smc", "Smc64", "ArmStaticInst",
65                           smcCode, ["IsNonSpeculative", "IsSerializeAfter"])
66    header_output += BasicDeclare.subst(smcIop)
67    decoder_output += BasicConstructor64.subst(smcIop)
68    exec_output += BasicExecute.subst(smcIop)
69
70    def subst(templateBase, iop):
71        global header_output, decoder_output, exec_output
72        header_output += eval(templateBase + "Declare").subst(iop)
73        decoder_output += eval(templateBase + "Constructor").subst(iop)
74        exec_output += BasicExecute.subst(iop)
75
76    bfmMaskCode = '''
77    uint64_t bitMask;
78    int diff = imm2 - imm1;
79    if (imm1 <= imm2) {
80        bitMask = mask(diff + 1);
81    } else {
82        bitMask = mask(imm2 + 1);
83        bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1));
84        diff += intWidth;
85    }
86    uint64_t topBits M5_VAR_USED = ~mask(diff+1);
87    uint64_t result = (Op164 >> imm1) | (Op164 << (intWidth - imm1));
88    result &= bitMask;
89    '''
90
91    bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);'
92    bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode);
93    subst("RegRegImmImmOp64", bfmIop)
94
95    ubfmCode = bfmMaskCode + 'Dest64 = result;'
96    ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode);
97    subst("RegRegImmImmOp64", ubfmIop)
98
99    sbfmCode = bfmMaskCode + \
100        'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);'
101    sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode);
102    subst("RegRegImmImmOp64", sbfmIop)
103
104    extrCode = '''
105        if (imm == 0) {
106            Dest64 = Op264;
107        } else {
108            Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm);
109        }
110    '''
111    extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode);
112    subst("RegRegRegImmOp64", extrIop);
113
114    unknownCode = '''
115            return std::make_shared<UndefinedInstruction>(machInst, true);
116    '''
117    unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64",
118                                 unknownCode)
119    header_output += BasicDeclare.subst(unknown64Iop)
120    decoder_output += BasicConstructor64.subst(unknown64Iop)
121    exec_output += BasicExecute.subst(unknown64Iop)
122
123    isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst",
124                           "fault = std::make_shared<FlushPipe>();",
125                           ['IsSerializeAfter'])
126    header_output += BasicDeclare.subst(isbIop)
127    decoder_output += BasicConstructor64.subst(isbIop)
128    exec_output += BasicExecute.subst(isbIop)
129
130    dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst",
131                           "fault = std::make_shared<FlushPipe>();",
132                           ['IsMemBarrier', 'IsSerializeAfter'])
133    header_output += BasicDeclare.subst(dsbIop)
134    decoder_output += BasicConstructor64.subst(dsbIop)
135    exec_output += BasicExecute.subst(dsbIop)
136
137    dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
138                           ['IsMemBarrier'])
139    header_output += BasicDeclare.subst(dmbIop)
140    decoder_output += BasicConstructor64.subst(dmbIop)
141    exec_output += BasicExecute.subst(dmbIop)
142
143    clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst",
144                             "LLSCLock = 0;")
145    header_output += BasicDeclare.subst(clrexIop)
146    decoder_output += BasicConstructor64.subst(clrexIop)
147    exec_output += BasicExecute.subst(clrexIop)
148}};
149