macromem.isa revision 7174
16019SN/A// -*- mode:c++ -*- 26019SN/A 37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 497134Sgblack@eecs.umich.edulet {{ 507134Sgblack@eecs.umich.edu predicateTest = 'testPredicate(CondCodes, condCode)' 516309SN/A}}; 526309SN/A 536309SN/Alet {{ 546309SN/A microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 556309SN/A 'MicroMemOp', 566309SN/A {'memacc_code': 'Ra = Mem;', 577134Sgblack@eecs.umich.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 586309SN/A 'predicate_test': predicateTest}, 596309SN/A ['IsMicroop']) 606309SN/A 617174Sgblack@eecs.umich.edu microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 627174Sgblack@eecs.umich.edu 'MicroMemOp', 637174Sgblack@eecs.umich.edu {'memacc_code': 'Fa = Mem;', 647174Sgblack@eecs.umich.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 657174Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 667174Sgblack@eecs.umich.edu ['IsMicroop']) 677174Sgblack@eecs.umich.edu 686754SN/A microLdrRetUopCode = ''' 696754SN/A Ra = Mem; 707134Sgblack@eecs.umich.edu uint32_t newCpsr = 717134Sgblack@eecs.umich.edu cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true); 727134Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 737134Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 746754SN/A ''' 756754SN/A microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 766754SN/A 'MicroMemOp', 776754SN/A {'memacc_code': microLdrRetUopCode, 786754SN/A 'ea_code': 797134Sgblack@eecs.umich.edu 'EA = Rb + (up ? imm : -imm);', 806754SN/A 'predicate_test': predicateTest}, 816754SN/A ['IsMicroop']) 826754SN/A 836309SN/A microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 846309SN/A 'MicroMemOp', 856309SN/A {'memacc_code': 'Mem = Ra;', 867134Sgblack@eecs.umich.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 876309SN/A 'predicate_test': predicateTest}, 886309SN/A ['IsMicroop']) 896309SN/A 907174Sgblack@eecs.umich.edu microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', 917174Sgblack@eecs.umich.edu 'MicroMemOp', 927174Sgblack@eecs.umich.edu {'memacc_code': 'Mem = Fa;', 937174Sgblack@eecs.umich.edu 'ea_code': 'EA = Rb + (up ? imm : -imm);', 947174Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 957174Sgblack@eecs.umich.edu ['IsMicroop']) 967174Sgblack@eecs.umich.edu 977174Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = '' 987174Sgblack@eecs.umich.edu 997174Sgblack@eecs.umich.edu loadIops = (microLdrUopIop, microLdrFpUopIop, microLdrRetUopIop) 1007174Sgblack@eecs.umich.edu storeIops = (microStrUopIop, microStrFpUopIop) 1017174Sgblack@eecs.umich.edu for iop in loadIops + storeIops: 1027174Sgblack@eecs.umich.edu header_output += MicroMemDeclare.subst(iop) 1037174Sgblack@eecs.umich.edu decoder_output += MicroMemConstructor.subst(iop) 1047174Sgblack@eecs.umich.edu for iop in loadIops: 1057174Sgblack@eecs.umich.edu exec_output += LoadExecute.subst(iop) + \ 1067174Sgblack@eecs.umich.edu LoadInitiateAcc.subst(iop) + \ 1077174Sgblack@eecs.umich.edu LoadCompleteAcc.subst(iop) 1087174Sgblack@eecs.umich.edu for iop in storeIops: 1097174Sgblack@eecs.umich.edu exec_output += StoreExecute.subst(iop) + \ 1107174Sgblack@eecs.umich.edu StoreInitiateAcc.subst(iop) + \ 1117174Sgblack@eecs.umich.edu StoreCompleteAcc.subst(iop) 1126309SN/A}}; 1136308SN/A 1146308SN/A//////////////////////////////////////////////////////////////////// 1156308SN/A// 1166308SN/A// Integer = Integer op Immediate microops 1176308SN/A// 1186308SN/A 1196308SN/Alet {{ 1206308SN/A microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 1216308SN/A 'MicroIntOp', 1226308SN/A {'code': 'Ra = Rb + imm;', 1236308SN/A 'predicate_test': predicateTest}, 1246308SN/A ['IsMicroop']) 1256308SN/A 1266308SN/A microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 1276308SN/A 'MicroIntOp', 1286308SN/A {'code': 'Ra = Rb - imm;', 1296308SN/A 'predicate_test': predicateTest}, 1306308SN/A ['IsMicroop']) 1316308SN/A 1326308SN/A header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 1336308SN/A MicroIntDeclare.subst(microSubiUopIop) 1347134Sgblack@eecs.umich.edu decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \ 1357134Sgblack@eecs.umich.edu MicroIntConstructor.subst(microSubiUopIop) 1366308SN/A exec_output = PredOpExecute.subst(microAddiUopIop) + \ 1376308SN/A PredOpExecute.subst(microSubiUopIop) 1386308SN/A}}; 1396019SN/A 1407134Sgblack@eecs.umich.edulet {{ 1417170Sgblack@eecs.umich.edu iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) 1427134Sgblack@eecs.umich.edu header_output = MacroMemDeclare.subst(iop) 1437134Sgblack@eecs.umich.edu decoder_output = MacroMemConstructor.subst(iop) 1446019SN/A}}; 145