macromem.isa revision 7174 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42//          Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49let {{
50    predicateTest = 'testPredicate(CondCodes, condCode)'
51}};
52
53let {{
54    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
55                                   'MicroMemOp',
56                                   {'memacc_code': 'Ra = Mem;',
57                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
58                                    'predicate_test': predicateTest},
59                                   ['IsMicroop'])
60
61    microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
62                                     'MicroMemOp',
63                                     {'memacc_code': 'Fa = Mem;',
64                                      'ea_code': 'EA = Rb + (up ? imm : -imm);',
65                                      'predicate_test': predicateTest},
66                                     ['IsMicroop'])
67
68    microLdrRetUopCode = '''
69        Ra = Mem;
70        uint32_t newCpsr =
71            cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
72        Cpsr = ~CondCodesMask & newCpsr;
73        CondCodes = CondCodesMask & newCpsr;
74    '''
75    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
76                                      'MicroMemOp',
77                                      {'memacc_code': microLdrRetUopCode,
78                                       'ea_code':
79                                          'EA = Rb + (up ? imm : -imm);',
80                                       'predicate_test': predicateTest},
81                                      ['IsMicroop'])
82
83    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
84                                   'MicroMemOp',
85                                   {'memacc_code': 'Mem = Ra;',
86                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
87                                    'predicate_test': predicateTest},
88                                   ['IsMicroop'])
89
90    microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
91                                     'MicroMemOp',
92                                     {'memacc_code': 'Mem = Fa;',
93                                      'ea_code': 'EA = Rb + (up ? imm : -imm);',
94                                      'predicate_test': predicateTest},
95                                     ['IsMicroop'])
96
97    header_output = decoder_output = exec_output = ''
98
99    loadIops = (microLdrUopIop, microLdrFpUopIop, microLdrRetUopIop)
100    storeIops = (microStrUopIop, microStrFpUopIop)
101    for iop in loadIops + storeIops:
102        header_output += MicroMemDeclare.subst(iop)
103        decoder_output += MicroMemConstructor.subst(iop)
104    for iop in loadIops:
105        exec_output += LoadExecute.subst(iop) + \
106                       LoadInitiateAcc.subst(iop) + \
107                       LoadCompleteAcc.subst(iop)
108    for iop in storeIops:
109        exec_output += StoreExecute.subst(iop) + \
110                       StoreInitiateAcc.subst(iop) + \
111                       StoreCompleteAcc.subst(iop)
112}};
113
114////////////////////////////////////////////////////////////////////
115//
116// Integer = Integer op Immediate microops
117//
118
119let {{
120    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
121                                    'MicroIntOp',
122                                    {'code': 'Ra = Rb + imm;',
123                                     'predicate_test': predicateTest},
124                                    ['IsMicroop'])
125
126    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
127                                    'MicroIntOp',
128                                    {'code': 'Ra = Rb - imm;',
129                                     'predicate_test': predicateTest},
130                                    ['IsMicroop'])
131
132    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
133                    MicroIntDeclare.subst(microSubiUopIop)
134    decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
135                     MicroIntConstructor.subst(microSubiUopIop)
136    exec_output = PredOpExecute.subst(microAddiUopIop) + \
137                  PredOpExecute.subst(microSubiUopIop)
138}};
139
140let {{
141    iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
142    header_output = MacroMemDeclare.subst(iop)
143    decoder_output = MacroMemConstructor.subst(iop)
144}};
145