1// -*- mode:c++ -*-
2//
3// Copyright (c) 2018 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Matt Horsnell
39//          Prakash Ramrakhyani
40//          Giacomo Travaglini
41
42let {{
43    header_output = ""
44    decoder_output = ""
45    exec_output = ""
46
47    cryptoEnabledCheckCode = '''
48        auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
49        if (!(crypto_reg & %(mask)d)) {
50            return std::make_shared<UndefinedInstruction>(machInst, true);
51        }
52    '''
53    cryptoRegRegRegPrefix = '''
54        Crypto crypto;
55        RegVect srcReg1, srcReg2, destReg;
56        // Read source and destination registers.
57    '''
58    for reg in range(4):
59        cryptoRegRegRegPrefix += '''
60            srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
61            srcReg2.regs[%(reg)d] = htog(AA64FpOp2P%(reg)d_uw);
62            destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
63        ''' % { "reg" : reg }
64    cryptoRegRegRegPrefix += '''
65        unsigned char *output = (unsigned char *)(&destReg.regs[0]);
66        unsigned char *input  = (unsigned char *)(&srcReg1.regs[0]);
67        unsigned char *input2 = (unsigned char *)(&srcReg2.regs[0]);
68    '''
69
70    cryptoSuffix = ""
71    for reg in range(4):
72        cryptoSuffix += '''
73            AA64FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
74        ''' % { "reg" : reg }
75
76    cryptoRegRegPrefix = '''
77        Crypto crypto;
78        RegVect srcReg1, destReg;
79        // Read source and destination registers.
80    '''
81    for reg in range(4):
82        cryptoRegRegPrefix += '''
83            srcReg1.regs[%(reg)d] = htog(AA64FpOp1P%(reg)d_uw);
84            destReg.regs[%(reg)d] = htog(AA64FpDestP%(reg)d_uw);
85        ''' % { "reg" : reg }
86
87    cryptoRegRegPrefix += '''
88        // cast into format passed to aes encrypt method.
89        unsigned char *output = (unsigned char *)(&destReg.regs[0]);
90        unsigned char *input  = (unsigned char *)(&srcReg1.regs[0]);
91    '''
92
93    def cryptoRegRegRegInst(name, Name, opClass, enable_check, crypto_func):
94        global header_output, decoder_output, exec_output
95
96        crypto_prefix = enable_check + cryptoRegRegRegPrefix
97        cryptocode = crypto_prefix + crypto_func + cryptoSuffix
98
99        cryptoiop = InstObjParams(name, Name, "RegRegRegOp",
100                                { "code": cryptocode,
101                                  "r_count": 4,
102                                  "predicate_test": predicateTest,
103                                  "op_class": opClass}, [])
104        header_output += RegRegRegOpDeclare.subst(cryptoiop)
105        decoder_output += RegRegRegOpConstructor.subst(cryptoiop)
106        exec_output += CryptoPredOpExecute.subst(cryptoiop)
107
108    def cryptoRegRegInst(name, Name, opClass, enable_check, crypto_func):
109        global header_output, decoder_output, exec_output
110
111        crypto_prefix = enable_check + cryptoRegRegPrefix
112        cryptocode = crypto_prefix + crypto_func + cryptoSuffix
113
114        cryptoiop = InstObjParams(name, Name, "RegRegOp",
115                                { "code": cryptocode,
116                                  "r_count": 4,
117                                  "predicate_test": predicateTest,
118                                  "op_class": opClass}, [])
119        header_output += RegRegOpDeclare.subst(cryptoiop)
120        decoder_output += RegRegOpConstructor.subst(cryptoiop)
121        exec_output += CryptoPredOpExecute.subst(cryptoiop)
122
123    aeseCode = "crypto.aesEncrypt(output, input, input2);"
124    aesdCode = "crypto.aesDecrypt(output, input, input2);"
125    aesmcCode = "crypto.aesMixColumns(output, input);"
126    aesimcCode = "crypto.aesInvMixColumns(output, input);"
127
128    sha1_cCode = "crypto.sha1C(output, input, input2);"
129    sha1_pCode = "crypto.sha1P(output, input, input2);"
130    sha1_mCode = "crypto.sha1M(output, input, input2);"
131    sha1_hCode = "crypto.sha1H(output, input);"
132    sha1_su0Code = "crypto.sha1Su0(output, input, input2);"
133    sha1_su1Code = "crypto.sha1Su1(output, input);"
134
135    sha256_hCode = "crypto.sha256H(output, input, input2);"
136    sha256_h2Code = "crypto.sha256H2(output, input, input2);"
137    sha256_su0Code = "crypto.sha256Su0(output, input);"
138    sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
139
140    aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 }
141    cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp",
142                        aes_enabled, aeseCode)
143    cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp",
144                        aes_enabled, aesdCode)
145    cryptoRegRegInst("aesmc", "AESMC64", "SimdAesMixOp",
146                     aes_enabled, aesmcCode)
147    cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp",
148                     aes_enabled, aesimcCode)
149
150    sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
151    cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp",
152                        sha1_enabled, sha1_cCode)
153    cryptoRegRegRegInst("sha1p", "SHA1P64", "SimdSha1HashOp",
154                        sha1_enabled, sha1_pCode)
155    cryptoRegRegRegInst("sha1m", "SHA1M64", "SimdSha1HashOp",
156                        sha1_enabled, sha1_mCode)
157    cryptoRegRegInst("sha1h", "SHA1H64", "SimdSha1Hash2Op",
158                     sha1_enabled, sha1_hCode)
159    cryptoRegRegRegInst("sha1su0", "SHA1SU064", "SimdShaSigma3Op",
160                        sha1_enabled, sha1_su0Code)
161    cryptoRegRegInst("sha1su1", "SHA1SU164", "SimdShaSigma2Op",
162                     sha1_enabled, sha1_su1Code)
163
164    sha2_enabled = cryptoEnabledCheckCode % { "mask" : 0xF000 }
165    cryptoRegRegRegInst("sha256h", "SHA256H64", "SimdSha256HashOp",
166                        sha2_enabled, sha256_hCode)
167    cryptoRegRegRegInst("sha256h2", "SHA256H264", "SimdSha256Hash2Op",
168                        sha2_enabled, sha256_h2Code)
169    cryptoRegRegInst("sha256su0", "SHA256SU064", "SimdShaSigma2Op",
170                     sha2_enabled, sha256_su0Code)
171    cryptoRegRegRegInst("sha256su1", "SHA256SU164", "SimdShaSigma3Op",
172                        sha2_enabled, sha256_su1Code)
173}};
174
175