m5ops.isa revision 8354:26be660e365a 
1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder.  You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gene Wu
38///
39
40def format M5ops() {{
41    decode_block = '''
42    {
43        const uint32_t m5func = bits(machInst, 23, 16);
44        switch(m5func) {
45#if FULL_SYSTEM
46            case 0x00: return new Arm(machInst);
47            case 0x01: return new Quiesce(machInst);
48            case 0x02: return new QuiesceNs(machInst);
49            case 0x03: return new QuiesceCycles(machInst);
50            case 0x04: return new QuiesceTime(machInst);
51#endif
52            case 0x07: return new Rpns(machInst);
53            case 0x09: return new WakeCPU(machInst);
54            case 0x10: return new Deprecated_ivlb(machInst);
55            case 0x11: return new Deprecated_ivle(machInst);
56            case 0x20: return new Deprecated_exit (machInst);
57            case 0x21: return new M5exit(machInst);
58#if FULL_SYSTEM
59            case 0x31: return new Loadsymbol(machInst);
60            case 0x30: return new Initparam(machInst);
61#endif
62            case 0x40: return new Resetstats(machInst);
63            case 0x41: return new Dumpstats(machInst);
64            case 0x42: return new Dumpresetstats(machInst);
65            case 0x43: return new M5checkpoint(machInst);
66#if FULL_SYSTEM
67            case 0x50: return new M5readfile(machInst);
68#endif
69            case 0x51: return new M5break(machInst);
70            case 0x52: return new M5switchcpu(machInst);
71#if FULL_SYSTEM
72            case 0x53: return new M5addsymbol(machInst);
73#endif
74            case 0x54: return new M5panic(machInst);
75            case 0x5a: return new M5workbegin(machInst);
76            case 0x5b: return new M5workend(machInst);
77        }
78   }
79   '''
80}};
81