xref: /gem5/src/arch/arm/isa/formats/branch.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Control transfer instructions
//

def format ArmBBlxImm() {{
    decode_block = '''
        if (machInst.condCode == 0xF) {
            int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
                          (bits(machInst, 24) << 1);
            return new BlxImm(machInst, imm);
        } else {
            return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
                         (ConditionCode)(uint32_t)machInst.condCode);
        }
    '''
}};

def format ArmBlBlxImm() {{
    decode_block = '''
        if (machInst.condCode == 0xF) {
            int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
                          (bits(machInst, 24) << 1);
            return new BlxImm(machInst, imm);
        } else {
            return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
                          (ConditionCode)(uint32_t)machInst.condCode);
        }
    '''
}};

def format ArmBx() {{
    decode_block = '''
        return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
                         (ConditionCode)(uint32_t)machInst.condCode);
    '''
}};

def format ArmBlxReg() {{
    decode_block = '''
        return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
                          (ConditionCode)(uint32_t)machInst.condCode);
    '''
}};

def format Thumb16CondBranchAndSvc() {{
    decode_block = '''
        if (bits(machInst, 11, 9) != 0x7) {
            return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
                         (ConditionCode)(uint32_t)bits(machInst, 11, 8));
        } else if (bits(machInst, 8)) {
            return new WarnUnimplemented("svc", machInst);
        } else {
            // This space will not be allocated in the future.
            return new WarnUnimplemented("unimplemented", machInst);
        }
    '''
}};

def format Thumb16UncondBranch() {{
    decode_block = '''
        return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC);
    '''
}};

def format Thumb32 BranchesAndMiscCtrl() {{
    decode_block = '''
        return new WarnUnimplemented("Branches_and_miscellaneous_control",
                                     machInst);
    '''
}};