xref: /gem5/src/arch/arm/isa/formats/branch.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
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// Copyright (c) 2007-2008 The Florida State University
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// modification, are permitted provided that the following conditions are
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// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Control transfer instructions
//

def format ArmBBlxImm() {{
    decode_block = '''
        if (machInst.condCode == 0xF) {
            int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
                          (bits(machInst, 24) << 1);
            return new BlxImm(machInst, imm);
        } else {
            return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
                         (ConditionCode)(uint32_t)machInst.condCode);
        }
    '''
}};

def format ArmBlBlxImm() {{
    decode_block = '''
        if (machInst.condCode == 0xF) {
            int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
                          (bits(machInst, 24) << 1);
            return new BlxImm(machInst, imm);
        } else {
            return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
                          (ConditionCode)(uint32_t)machInst.condCode);
        }
    '''
}};

def format ArmBx() {{
    decode_block = '''
        return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
                         (ConditionCode)(uint32_t)machInst.condCode);
    '''
}};

def format ArmBlxReg() {{
    decode_block = '''
        return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
                          (ConditionCode)(uint32_t)machInst.condCode);
    '''
}};

def format Branch(code,*opt_flags) {{

    #Build Instruction Flags
    #Use Link & Likely Flags to Add Link/Condition Code
    inst_flags = ('IsDirectControl', )
    linking = False
    for x in opt_flags:
        if x == 'Link':
            linking = True
            code += 'LR = NPC;\n'
        else:
            inst_flags += (x, )

    #Take into account uncond. branch instruction
    if 'cond == 1' in code:
         inst_flags += ('IsUnCondControl', )
    else:
         inst_flags += ('IsCondControl', )

    icode =  'if (testPredicate(CondCodes, condCode)) {\n'
    icode += code
    icode += '  NPC = NPC + 4 + disp;\n'
    icode += '} else {\n'
    icode += '  NPC = NPC;\n'
    if linking:
        icode += '  LR = LR;\n'
    icode += '};\n'

    code = icode

    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

def format BranchExchange(code,*opt_flags) {{
    #Build Instruction Flags
    #Use Link & Likely Flags to Add Link/Condition Code
    inst_flags = ('IsIndirectControl', )
    linking = False
    for x in opt_flags:
        if x == 'Link':
            linking = True
            code += 'LR = NPC;\n'
        else:
            inst_flags += (x, )

    #Take into account uncond. branch instruction
    if 'cond == 1' in code:
         inst_flags += ('IsUnCondControl', )
    else:
         inst_flags += ('IsCondControl', )

    #Condition code

    icode =  'if (testPredicate(CondCodes, condCode)) {\n'
    icode += code
    icode += '  NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
    icode += '} else {\n'
    icode += '  NPC = NPC;\n'
    if linking:
        icode += '  LR = LR;\n'
    icode += '};\n'

    code = icode

    iop = InstObjParams(name, Name, 'BranchExchange', code, inst_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};