thumb.isa revision 7141
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2009 The Regents of The University of Michigan 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Gabe Black 42 431: decode BIGTHUMB { 44 // 16 bit thumb instructions. 45 0: decode TOPCODE_15_13 { 46 0x0, 0x1: Thumb16ShiftAddSubMoveCmp::thumb16ShiftAddMoveCmp(); 47 0x2: decode TOPCODE_12_10 { 48 0x0: Thumb16DataProcessing::thumb16DataProcessing(); 49 0x1: Thumb16SpecDataAndBx::thumb16SpecDataAndBx(); 50 0x2, 0x3: Thumb16MemLit::thumb16MemLit(); 51 default: Thumb16MemReg::thumb16MemReg(); 52 } 53 0x3, 0x4: Thumb16MemImm::thumb16MemImm(); 54 0x5: decode TOPCODE_12_11 { 55 0x0: Thumb16Adr::thumb16Adr(); 56 0x1: Thumb16AddSp::thumb16AddSp(); //sp, immediate 57 0x2, 0x3: Thumb16Misc::thumb16Misc(); 58 } 59 0x6: decode TOPCODE_12_11 { 60 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem(); 61 default: decode TOPCODE_11_8 { 62 0xe: WarnUnimpl::undefined(); // permanently undefined 63 0xf: WarnUnimpl::svc(); // formerly swi 64 default: WarnUnimpl::b(); // conditional 65 } 66 } 67 0x7: decode TOPCODE_12_11 { 68 0x0: WarnUnimpl::b(); // unconditional 69 } 70 } 71 72 // 32 bit thumb instructions. 73 1: decode HTOPCODE_12_11 { 74 0x1: decode HTOPCODE_10_9 { 75 0x0: decode HTOPCODE_8_6 { 76 0x0, 0x6: decode HTOPCODE_4 { 77 0x0: WarnUnimpl::srs(); 78 0x1: WarnUnimpl::rfe(); 79 } 80 0x1: decode HTOPCODE_5_4 { 81 0x0: WarnUnimpl::strex(); 82 0x1: WarnUnimpl::ldrex(); 83 0x2: WarnUnimpl::strd(); // immediate 84 0x3: decode HTRN { 85 0xf: WarnUnimpl::ldrd(); // literal 86 default: WarnUnimpl::ldrd(); // immediate 87 } 88 } 89 // This uses the same encoding as regular ARM. 90 0x2: ArmMacroMem::armMacroMem(); 91 0x3: decode HTOPCODE_5_4 { 92 0x0: decode LTOPCODE_7_4 { 93 0x4: WarnUnimpl::strexb(); 94 0x5: WarnUnimpl::strexh(); 95 0x7: WarnUnimpl::strexd(); 96 } 97 0x1: decode LTOPCODE_7_4 { 98 0x0: WarnUnimpl::tbb(); 99 0x1: WarnUnimpl::tbh(); 100 0x4: WarnUnimpl::ldrexb(); 101 0x5: WarnUnimpl::ldrexh(); 102 0x7: WarnUnimpl::ldrexd(); 103 } 104 0x2: WarnUnimpl::strd(); // immediate 105 0x3: decode HTRN { 106 0xf: WarnUnimpl::ldrd(); // literal 107 default: WarnUnimpl::ldrd(); // immediate 108 } 109 } 110 // This uses the same encoding as regular ARM. 111 0x4: ArmMacroMem::armMacroMem(); 112 0x5, 0x7: decode HTOPCODE_4 { 113 0x0: WarnUnimpl::strd(); // immediate 114 0x1: decode HTRN { 115 0xf: WarnUnimpl::ldrd(); // literal 116 default: WarnUnimpl::ldrd(); // immediate 117 } 118 } 119 } 120 0x1: Thumb32DataProcShiftReg::thumb32DataProcShiftReg(); 121 default: decode HTOPCODE_9_8 { 122 0x2: decode LTOPCODE_4 { 123 0x0: decode LTCOPROC { 124 0xa, 0xb: decode OPCODE_23_20 { 125##include "vfp.isa" 126 } 127 default: WarnUnimpl::cdp(); // cdp2 128 } 129 0x1: decode LTCOPROC { 130 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 131 default: decode HTOPCODE_4 { 132 0x0: WarnUnimpl::mcr(); // mcr2 133 0x1: WarnUnimpl::mrc(); // mrc2 134 } 135 } 136 } 137 0x3: WarnUnimpl::Advanced_SIMD(); 138 default: decode LTCOPROC { 139 0xa, 0xb: decode HTOPCODE_9_4 { 140 0x00: WarnUnimpl::undefined(); 141 0x04: WarnUnimpl::mcrr(); // mcrr2 142 0x05: WarnUnimpl::mrrc(); // mrrc2 143 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 144 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 145 WarnUnimpl::stc(); // stc2 146 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 147 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 148 decode HTRN { 149 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 150 default: WarnUnimpl::ldc(); // ldc2 (immediate) 151 } 152 } 153 default: decode HTOPCODE_9_5 { 154 0x00: WarnUnimpl::undefined(); 155 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 156 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 157 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 158 WarnUnimpl::Extension_register_load_store_instruction(); 159 } 160 } 161 } 162 } 163 0x2: decode LTOPCODE_15 { 164 0x0: decode HTOPCODE_9 { 165 0x0: Thumb32DataProcModImm::thumb32DataProcModImm(); 166 0x1: WarnUnimpl::Data_processing_plain_binary_immediate(); 167 } 168 0x1: WarnUnimpl::Branches_and_miscellaneous_control(); 169 } 170 0x3: decode HTOPCODE_10_9 { 171 0x0: decode HTOPCODE_4 { 172 0x0: decode HTOPCODE_8 { 173 0x0: Thumb32StoreSingle::thumb32StoreSingle(); 174 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store(); 175 } 176 0x1: decode HTOPCODE_6_5 { 177 0x0: WarnUnimpl::Load_byte_memory_hints(); 178 0x1: WarnUnimpl::Load_halfword_memory_hints(); 179 0x2: Thumb32LoadWord::thumb32LoadWord(); 180 0x3: WarnUnimpl::undefined(); 181 } 182 } 183 0x1: decode HTOPCODE_8_7 { 184 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference(); 185 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide(); 186 default: WarnUnimpl::Data_processing_register(); 187 } 188 default: decode HTOPCODE_9_8 { 189 0x2: decode LTOPCODE_4 { 190 0x0: decode LTCOPROC { 191 0xa, 0xb: WarnUnimpl::VFP_Inst(); 192 default: WarnUnimpl::cdp(); // cdp2 193 } 194 0x1: decode LTCOPROC { 195 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 196 default: decode HTOPCODE_4 { 197 0x0: WarnUnimpl::mcr(); // mcr2 198 0x1: WarnUnimpl::mrc(); // mrc2 199 } 200 } 201 } 202 0x3: WarnUnimpl::Advanced_SIMD(); 203 default: decode LTCOPROC { 204 0xa, 0xb: decode HTOPCODE_9_4 { 205 0x00: WarnUnimpl::undefined(); 206 0x04: WarnUnimpl::mcrr(); // mcrr2 207 0x05: WarnUnimpl::mrrc(); // mrrc2 208 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 209 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 210 WarnUnimpl::stc(); // stc2 211 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 212 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 213 decode HTRN { 214 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 215 default: WarnUnimpl::ldc(); // ldc2 (immediate) 216 } 217 } 218 default: decode HTOPCODE_9_5 { 219 0x00: WarnUnimpl::undefined(); 220 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 221 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 222 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 223 WarnUnimpl::Extension_register_load_store_instruction(); 224 } 225 } 226 } 227 } 228 } 229} 230