thumb.isa revision 7117
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2009 The Regents of The University of Michigan 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Gabe Black 42 431: decode BIGTHUMB { 44 // 16 bit thumb instructions. 45 0: decode TOPCODE_15_13 { 46 0x0, 0x1: decode TOPCODE_13_11 { 47 0x0: WarnUnimpl::lsl(); //immediate 48 0x1: WarnUnimpl::lsr(); //immediate 49 0x2: WarnUnimpl::asr(); //immediate 50 0x3: decode TOPCODE_10_9 { 51 0x0: WarnUnimpl::add(); //register 52 0x1: WarnUnimpl::sub(); //register 53 0x2: WarnUnimpl::add(); //3 bit immediate 54 0x3: WarnUnimpl::sub(); //3 bit immediate 55 } 56 0x4: WarnUnimpl::mov(); //immediate 57 0x5: WarnUnimpl::cmp(); //immediate 58 0x6: WarnUnimpl::add(); //8 bit immediate, thumb 59 0x7: WarnUnimpl::sub(); //8 bit immediate, thumb 60 } 61 0x2: decode TOPCODE_12_10 { 62 // Data processing 63 0x0: decode TOPCODE_9_6 { 64 0x0: WarnUnimpl::and(); //register 65 0x1: WarnUnimpl::eor(); //register 66 0x2: WarnUnimpl::lsl(); //register 67 0x3: WarnUnimpl::lsr(); //register 68 0x4: WarnUnimpl::asr(); //register 69 0x5: WarnUnimpl::adc(); //register 70 0x6: WarnUnimpl::sbc(); //register 71 0x7: WarnUnimpl::ror(); //register 72 0x8: WarnUnimpl::tst(); //register 73 0x9: WarnUnimpl::rsb(); //immediate 74 0xa: WarnUnimpl::cmp(); //register (high registers) 75 0xb: WarnUnimpl::cmn(); //register 76 0xc: WarnUnimpl::orr(); //register 77 0xd: WarnUnimpl::mul(); 78 0xe: WarnUnimpl::bic(); //register 79 0xf: WarnUnimpl::mvn(); //register 80 } 81 // Special data instructions and branch and exchange 82 0x1: decode TOPCODE_9_6 { 83 0x0: WarnUnimpl::add(); //register (low registers) 84 0x1, 0x2, 0x3: WarnUnimpl::add(); //register (high registers) 85 0x4: WarnUnimpl::unpredictable(); //? 86 0x5, 0x6, 0x7: WarnUnimpl::cmp(); //register 87 0x8: WarnUnimpl::mov(); //register (low registers) 88 0x9, 0xa, 0xb: WarnUnimpl::mov(); //register (high registers) 89 0xc, 0xd: WarnUnimpl::bx(); 90 0xe, 0xf: WarnUnimpl::blx(); //register 91 } 92 0x2, 0x3: WarnUnimpl::ldr(); 93 default: decode TOPCODE_11_9 { 94 0x0: WarnUnimpl::str(); //register 95 0x1: WarnUnimpl::strh(); //register 96 0x2: WarnUnimpl::strb(); //register 97 0x3: WarnUnimpl::ldrsb(); //register 98 0x4: WarnUnimpl::ldr(); //register 99 0x5: WarnUnimpl::ldrh(); //register 100 0x6: WarnUnimpl::ldrb(); //register 101 0x7: WarnUnimpl::ldrsh(); //register 102 } 103 } 104 0x3: decode TOPCODE_12_11 { 105 0x0: WarnUnimpl::str(); //immediate, thumb 106 0x1: WarnUnimpl::ldr(); //immediate, thumb 107 0x2: WarnUnimpl::strb(); //immediate, thumb 108 0x3: WarnUnimpl::ldrb(); //immediate, thumb 109 } 110 0x4: decode TOPCODE_12_11 { 111 0x0: WarnUnimpl::strh(); //immediate, thumb 112 0x1: WarnUnimpl::ldrh(); //immediate, thumb 113 0x2: WarnUnimpl::str(); //immediate, thumb 114 0x3: WarnUnimpl::ldr(); //immediate, thumb 115 } 116 0x5: decode TOPCODE_12_11 { 117 0x0: WarnUnimpl::adr(); 118 0x1: WarnUnimpl::add(); //sp, immediate 119 0x2: decode TOPCODE_10_8 { 120 0x0: decode TOPCODE_7 { 121 0x0: WarnUnimpl::add(); //sp, immediate 122 0x1: WarnUnimpl::sub(); //sp, immediate 123 } 124 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 125 0x2: decode TOPCODE_7_6 { 126 0x0: WarnUnimpl::sxth(); 127 0x1: WarnUnimpl::sxtb(); 128 0x2: WarnUnimpl::uxth(); 129 0x3: WarnUnimpl::uxtb(); 130 } 131 0x4, 0x5: WarnUnimpl::pop(); 132 0x6: decode TOPCODE_7_5 { 133 0x2: WarnUnimpl::setend(); 134 0x3: WarnUnimpl::cps(); 135 } 136 } 137 0x3: decode TOPCODE_10_8 { 138 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 139 0x2: decode TOPCODE_7_6 { 140 0x0: WarnUnimpl::rev(); 141 0x1: WarnUnimpl::rev16(); 142 0x3: WarnUnimpl::revsh(); 143 } 144 0x4, 0x5: WarnUnimpl::pop(); 145 0x6: WarnUnimpl::bkpt(); 146 0x7: decode TOPCODE_3_0 { 147 0x0: WarnUnimpl::it(); 148 default: decode TOPCODE_7_4 { 149 0x0: WarnUnimpl::nop(); 150 0x1: WarnUnimpl::yield(); 151 0x2: WarnUnimpl::wfe(); 152 0x3: WarnUnimpl::wfi(); 153 0x4: WarnUnimpl::sev(); 154 default: WarnUnimpl::unallocated_hint(); 155 } 156 } 157 } 158 } 159 0x6: decode TOPCODE_12_11 { 160 0x0: WarnUnimpl::stm(); // also stmia, stmea 161 0x1: WarnUnimpl::ldm(); // also ldmia, ldmea 162 default: decode TOPCODE_11_8 { 163 0xe: WarnUnimpl::undefined(); // permanently undefined 164 0xf: WarnUnimpl::svc(); // formerly swi 165 default: WarnUnimpl::b(); // conditional 166 } 167 } 168 0x7: decode TOPCODE_12_11 { 169 0x0: WarnUnimpl::b(); // unconditional 170 } 171 } 172 173 // 32 bit thumb instructions. 174 1: decode HTOPCODE_12_11 { 175 0x1: decode HTOPCODE_10_9 { 176 0x0: decode HTOPCODE_8_6 { 177 0x0, 0x6: decode HTOPCODE_4 { 178 0x0: WarnUnimpl::srs(); 179 0x1: WarnUnimpl::rfe(); 180 } 181 0x1: decode HTOPCODE_5_4 { 182 0x0: WarnUnimpl::strex(); 183 0x1: WarnUnimpl::ldrex(); 184 0x2: WarnUnimpl::strd(); // immediate 185 0x3: decode HTRN { 186 0xf: WarnUnimpl::ldrd(); // literal 187 default: WarnUnimpl::ldrd(); // immediate 188 } 189 } 190 0x2: decode HTOPCODE_4 { 191 0x0: WarnUnimpl::stm(); // stmia, stmea 192 0x1: decode HTRN { 193 0xd: WarnUnimpl::pop(); 194 default: WarnUnimpl::ldm(); // ldmia, ldmfd 195 } 196 } 197 0x3: decode HTOPCODE_5_4 { 198 0x0: decode LTOPCODE_7_4 { 199 0x4: WarnUnimpl::strexb(); 200 0x5: WarnUnimpl::strexh(); 201 0x7: WarnUnimpl::strexd(); 202 } 203 0x1: decode LTOPCODE_7_4 { 204 0x0: WarnUnimpl::tbb(); 205 0x1: WarnUnimpl::tbh(); 206 0x4: WarnUnimpl::ldrexb(); 207 0x5: WarnUnimpl::ldrexh(); 208 0x7: WarnUnimpl::ldrexd(); 209 } 210 0x2: WarnUnimpl::strd(); // immediate 211 0x3: decode HTRN { 212 0xf: WarnUnimpl::ldrd(); // literal 213 default: WarnUnimpl::ldrd(); // immediate 214 } 215 } 216 0x4: decode HTOPCODE_4 { 217 0x0: decode HTRN { 218 0xd: WarnUnimpl::push(); 219 default: WarnUnimpl::stmdb(); // stmfd 220 } 221 0x1: WarnUnimpl::ldmdb(); // ldmea 222 } 223 0x5, 0x7: decode HTOPCODE_4 { 224 0x0: WarnUnimpl::strd(); // immediate 225 0x1: decode HTRN { 226 0xf: WarnUnimpl::ldrd(); // literal 227 default: WarnUnimpl::ldrd(); // immediate 228 } 229 } 230 } 231 0x1: decode HTOPCODE_8_5 { 232 0x0: decode LTRD { 233 0xf: decode HTS { 234 0x1: WarnUnimpl::tst(); // register 235 } 236 default: WarnUnimpl::and(); // register 237 } 238 0x1: WarnUnimpl::bic(); // register 239 0x2: decode HTRN { 240 0xf: WarnUnimpl::mov(); // register 241 default: WarnUnimpl::orr(); // register 242 } 243 0x3: decode HTRN { 244 0xf: WarnUnimpl::mvn(); // register 245 default: WarnUnimpl::orn(); // register 246 } 247 0x4: decode LTRD { 248 0xf: decode HTS { 249 0x1: WarnUnimpl::teq(); // register 250 } 251 default: WarnUnimpl::eor(); // register 252 } 253 0x6: WarnUnimpl::pkh(); 254 0x8: decode LTRD { 255 0xf: decode HTS { 256 0x1: WarnUnimpl::cmn(); // register 257 } 258 default: WarnUnimpl::add(); // register 259 } 260 0xa: WarnUnimpl::adc(); // register 261 0xb: WarnUnimpl::sbc(); // register 262 0xd: decode LTRD { 263 0xf: decode HTS { 264 0x1: WarnUnimpl::cmp(); // register 265 } 266 default: WarnUnimpl::sub(); // register 267 } 268 0xe: WarnUnimpl::rsb(); // register 269 } 270 default: decode HTOPCODE_9_8 { 271 0x2: decode LTOPCODE_4 { 272 0x0: decode LTCOPROC { 273 0xa, 0xb: decode OPCODE_23_20 { 274##include "vfp.isa" 275 } 276 default: WarnUnimpl::cdp(); // cdp2 277 } 278 0x1: decode LTCOPROC { 279 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 280 default: decode HTOPCODE_4 { 281 0x0: WarnUnimpl::mcr(); // mcr2 282 0x1: WarnUnimpl::mrc(); // mrc2 283 } 284 } 285 } 286 0x3: WarnUnimpl::Advanced_SIMD(); 287 default: decode LTCOPROC { 288 0xa, 0xb: decode HTOPCODE_9_4 { 289 0x00: WarnUnimpl::undefined(); 290 0x04: WarnUnimpl::mcrr(); // mcrr2 291 0x05: WarnUnimpl::mrrc(); // mrrc2 292 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 293 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 294 WarnUnimpl::stc(); // stc2 295 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 296 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 297 decode HTRN { 298 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 299 default: WarnUnimpl::ldc(); // ldc2 (immediate) 300 } 301 } 302 default: decode HTOPCODE_9_5 { 303 0x00: WarnUnimpl::undefined(); 304 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 305 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 306 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 307 WarnUnimpl::Extension_register_load_store_instruction(); 308 } 309 } 310 } 311 } 312 0x2: decode LTOPCODE_15 { 313 0x0: decode HTOPCODE_9 { 314 0x0: decode HTOPCODE_8_5 { 315 0x0: decode LTRD { 316 0xf: decode HTS { 317 0x1: DataModImmOp::tst({{ 318 resTemp = Rn & rotated_imm; 319 }}); 320 } 321 default: DataModImmOp::and({{ 322 Rs = resTemp = Rn & rotated_imm; 323 }}); 324 } 325 0x1: DataModImmOp::bic({{ 326 Rs = resTemp = Rn & ~rotated_imm; 327 }}); 328 0x2: decode HTRN { 329 0xf: DataModImmOp::mov({{ 330 Rs = resTemp = rotated_imm; 331 }}); 332 default: DataModImmOp::orr({{ 333 Rs = resTemp = Rn | rotated_imm; 334 }}); 335 } 336 0x3: decode HTRN { 337 0xf: DataModImmOp::mvn({{ 338 Rs = resTemp = ~rotated_imm; 339 }}); 340 default: DataModImmOp::orn({{ 341 Rs = resTemp = Rn | ~rotated_imm; 342 }}); 343 } 344 0x4: decode LTRD { 345 0xf: decode HTS { 346 0x1: DataModImmOp::teq({{ 347 resTemp = Rn ^ rotated_imm; 348 }}); 349 } 350 default: DataModImmOp::eor({{ 351 Rs = resTemp = Rn ^ rotated_imm; 352 }}); 353 } 354 0x8: decode LTRD { 355 0xf: decode HTS { 356 0x1: DataModImmOp::cmn({{ 357 resTemp = Rn + rotated_imm; 358 }}, add); 359 } 360 default: DataModImmOp::add({{ 361 Rs = resTemp = Rn + rotated_imm; 362 }}, add); 363 } 364 0xa: DataModImmOp::adc({{ 365 Rs = resTemp = Rn + rotated_imm + CondCodes<29:>; 366 }}, add); 367 0xb: DataModImmOp::sbc({{ 368 Rs = resTemp = Rn - rotated_imm - !CondCodes<29:>; 369 }}, sub); 370 0xd: decode LTRD { 371 0xf: decode HTS { 372 0x1: DataModImmOp::cmp({{ 373 resTemp = Rn - rotated_imm; 374 }}, sub); 375 } 376 default: DataModImmOp::sub({{ 377 Rs = resTemp = Rn - rotated_imm; 378 }}, sub); 379 } 380 0xe: DataModImmOp::rsb({{ 381 Rs = resTemp = rotated_imm - Rn; 382 }}, rsb); 383 } 384 0x1: WarnUnimpl::Data_processing_plain_binary_immediate(); 385 } 386 0x1: WarnUnimpl::Branches_and_miscellaneous_control(); 387 } 388 0x3: decode HTOPCODE_10_9 { 389 0x0: decode HTOPCODE_4 { 390 0x0: decode HTOPCODE_8 { 391 0x0: decode HTOPCODE_7_5 { 392 0x0: decode LTOPCODE_11_8 { 393 0x0: decode LTOPCODE_7_6 { 394 0x0: WarnUnimpl::strb(); // register 395 } 396 0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strb(); // immediate thumb 397 0xe: WarnUnimpl::strbt(); 398 } 399 0x1: decode LTOPCODE_11_8 { 400 0x0: decode LTOPCODE_7_6 { 401 0x0: WarnUnimpl::strh(); // register 402 } 403 0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strh(); // immediate thumb 404 0xe: WarnUnimpl::strht(); 405 } 406 0x2: decode LTOPCODE_11_8 { 407 0x0: decode LTOPCODE_7_6 { 408 0x0: WarnUnimpl::str(); // register 409 } 410 0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::str(); // immediate thumb 411 0xe: WarnUnimpl::strt(); 412 } 413 0x4: WarnUnimpl::strb(); // immediate, thumb 414 0x5: WarnUnimpl::strh(); // immediate, thumb 415 0x6: WarnUnimpl::str(); // immediate, thumb 416 } 417 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store(); 418 } 419 0x1: decode HTOPCODE_6_5 { 420 0x0: WarnUnimpl::Load_byte_memory_hints(); 421 0x1: WarnUnimpl::Load_halfword_memory_hints(); 422 0x2: decode HTOPCODE_8 { 423 0x0: decode HTRN { 424 0xf: ArmLoadMemory::ldr1( 425 {{ Rd.uw = Mem.uw }}, 426 {{ EA = roundUp(PC, 4) + 427 (UP ? IMMED_11_0 : -IMMED_11_0); }}); 428 default: decode HTOPCODE_7 { 429 0x0: decode LTOPCODE_11_8 { 430 0x0: decode LTOPCODE_7_6 { 431 0x0: ArmLoadMemory::ldr2( 432 {{ Rd = Mem; }}, 433 {{ EA = Rn + 434 (Rm << 435 bits(machInst, 5, 4)); }} 436 ); 437 } 438 0x9: ArmLoadMemory::ldr3( 439 {{ Rd = Mem; 440 Rn = Rn - IMMED_11_0; }}, 441 {{ EA = Rn; }} 442 ); 443 0xb: ArmLoadMemory::ldr4( 444 {{ Rd = Mem; 445 Rn = Rn + IMMED_11_0; }}, 446 {{ EA = Rn; }} 447 ); 448 0xc: ArmLoadMemory::ldr5( 449 {{ Rd = Mem; }}, 450 {{ EA = Rn - IMMED_11_0; }} 451 ); 452 0xd: ArmLoadMemory::ldr6( 453 {{ Rd = Mem; 454 Rn = Rn - IMMED_11_0; }}, 455 {{ EA = Rn - IMMED_11_0; }} 456 ); 457 0xf: ArmLoadMemory::ldr7( 458 {{ Rd = Mem; 459 Rn = Rn + IMMED_11_0; }}, 460 {{ EA = Rn + IMMED_11_0; }} 461 ); 462 0xe: ArmLoadMemory::ldrt( 463 {{ Rd = Mem; }}, 464 {{ EA = Rn + IMMED_11_0; }} 465 ); // This should force user level access 466 } 467 0x1: ArmLoadMemory::ldr8( 468 {{ Rd = Mem; }}, 469 {{ EA = Rn + IMMED_11_0; }} 470 ); 471 } 472 } 473 } 474 0x3: WarnUnimpl::undefined(); 475 } 476 } 477 0x1: decode HTOPCODE_8_7 { 478 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference(); 479 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide(); 480 default: WarnUnimpl::Data_processing_register(); 481 } 482 default: decode HTOPCODE_9_8 { 483 0x2: decode LTOPCODE_4 { 484 0x0: decode LTCOPROC { 485 0xa, 0xb: WarnUnimpl::VFP_Inst(); 486 default: WarnUnimpl::cdp(); // cdp2 487 } 488 0x1: decode LTCOPROC { 489 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 490 default: decode HTOPCODE_4 { 491 0x0: WarnUnimpl::mcr(); // mcr2 492 0x1: WarnUnimpl::mrc(); // mrc2 493 } 494 } 495 } 496 0x3: WarnUnimpl::Advanced_SIMD(); 497 default: decode LTCOPROC { 498 0xa, 0xb: decode HTOPCODE_9_4 { 499 0x00: WarnUnimpl::undefined(); 500 0x04: WarnUnimpl::mcrr(); // mcrr2 501 0x05: WarnUnimpl::mrrc(); // mrrc2 502 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 503 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 504 WarnUnimpl::stc(); // stc2 505 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 506 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 507 decode HTRN { 508 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 509 default: WarnUnimpl::ldc(); // ldc2 (immediate) 510 } 511 } 512 default: decode HTOPCODE_9_5 { 513 0x00: WarnUnimpl::undefined(); 514 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 515 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 516 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 517 WarnUnimpl::Extension_register_load_store_instruction(); 518 } 519 } 520 } 521 } 522 } 523} 524