thumb.isa revision 7136
16019SN/A// -*- mode:c++ -*- 26019SN/A 37102SN/A// Copyright (c) 2010 ARM Limited 47102SN/A// All rights reserved 57102SN/A// 67102SN/A// The license below extends only to copyright in the software and shall 77102SN/A// not be construed as granting a license to any other intellectual 87102SN/A// property including but not limited to intellectual property relating 97102SN/A// to a hardware implementation of the functionality of the software 107102SN/A// licensed hereunder. You may use the software subject to the license 117102SN/A// terms below provided that you ensure that this notice is replicated 127102SN/A// unmodified and in its entirety in all distributions of the software, 137102SN/A// modified or unmodified, in source code or in binary form. 147102SN/A// 157102SN/A// Copyright (c) 2009 The Regents of The University of Michigan 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 417102SN/A// Authors: Gabe Black 426019SN/A 437102SN/A1: decode BIGTHUMB { 447104SN/A // 16 bit thumb instructions. 457104SN/A 0: decode TOPCODE_15_13 { 467104SN/A 0x0, 0x1: decode TOPCODE_13_11 { 477104SN/A 0x0: WarnUnimpl::lsl(); //immediate 487104SN/A 0x1: WarnUnimpl::lsr(); //immediate 497104SN/A 0x2: WarnUnimpl::asr(); //immediate 507104SN/A 0x3: decode TOPCODE_10_9 { 517104SN/A 0x0: WarnUnimpl::add(); //register 527104SN/A 0x1: WarnUnimpl::sub(); //register 537104SN/A 0x2: WarnUnimpl::add(); //3 bit immediate 547104SN/A 0x3: WarnUnimpl::sub(); //3 bit immediate 557104SN/A } 567104SN/A 0x4: WarnUnimpl::mov(); //immediate 577104SN/A 0x5: WarnUnimpl::cmp(); //immediate 587104SN/A 0x6: WarnUnimpl::add(); //8 bit immediate, thumb 597104SN/A 0x7: WarnUnimpl::sub(); //8 bit immediate, thumb 607104SN/A } 617104SN/A 0x2: decode TOPCODE_12_10 { 627104SN/A // Data processing 637104SN/A 0x0: decode TOPCODE_9_6 { 647104SN/A 0x0: WarnUnimpl::and(); //register 657104SN/A 0x1: WarnUnimpl::eor(); //register 667104SN/A 0x2: WarnUnimpl::lsl(); //register 677104SN/A 0x3: WarnUnimpl::lsr(); //register 687104SN/A 0x4: WarnUnimpl::asr(); //register 697104SN/A 0x5: WarnUnimpl::adc(); //register 707104SN/A 0x6: WarnUnimpl::sbc(); //register 717104SN/A 0x7: WarnUnimpl::ror(); //register 727104SN/A 0x8: WarnUnimpl::tst(); //register 737104SN/A 0x9: WarnUnimpl::rsb(); //immediate 747104SN/A 0xa: WarnUnimpl::cmp(); //register (high registers) 757104SN/A 0xb: WarnUnimpl::cmn(); //register 767104SN/A 0xc: WarnUnimpl::orr(); //register 777104SN/A 0xd: WarnUnimpl::mul(); 787104SN/A 0xe: WarnUnimpl::bic(); //register 797104SN/A 0xf: WarnUnimpl::mvn(); //register 807104SN/A } 817104SN/A // Special data instructions and branch and exchange 827104SN/A 0x1: decode TOPCODE_9_6 { 837104SN/A 0x0: WarnUnimpl::add(); //register (low registers) 847104SN/A 0x1, 0x2, 0x3: WarnUnimpl::add(); //register (high registers) 857104SN/A 0x4: WarnUnimpl::unpredictable(); //? 867104SN/A 0x5, 0x6, 0x7: WarnUnimpl::cmp(); //register 877104SN/A 0x8: WarnUnimpl::mov(); //register (low registers) 887104SN/A 0x9, 0xa, 0xb: WarnUnimpl::mov(); //register (high registers) 897104SN/A 0xc, 0xd: WarnUnimpl::bx(); 907104SN/A 0xe, 0xf: WarnUnimpl::blx(); //register 917104SN/A } 927126Sgblack@eecs.umich.edu 0x2, 0x3: Thumb16MemLit::thumb16MemLit(); 937124Sgblack@eecs.umich.edu default: Thumb16MemReg::thumb16MemReg(); 947104SN/A } 957125Sgblack@eecs.umich.edu 0x3, 0x4: Thumb16MemImm::thumb16MemImm(); 967104SN/A 0x5: decode TOPCODE_12_11 { 977104SN/A 0x0: WarnUnimpl::adr(); 987104SN/A 0x1: WarnUnimpl::add(); //sp, immediate 997104SN/A 0x2: decode TOPCODE_10_8 { 1007104SN/A 0x0: decode TOPCODE_7 { 1017104SN/A 0x0: WarnUnimpl::add(); //sp, immediate 1027104SN/A 0x1: WarnUnimpl::sub(); //sp, immediate 1037104SN/A } 1047104SN/A 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 1057104SN/A 0x2: decode TOPCODE_7_6 { 1067104SN/A 0x0: WarnUnimpl::sxth(); 1077104SN/A 0x1: WarnUnimpl::sxtb(); 1087104SN/A 0x2: WarnUnimpl::uxth(); 1097104SN/A 0x3: WarnUnimpl::uxtb(); 1107104SN/A } 1117104SN/A 0x4, 0x5: WarnUnimpl::pop(); 1127104SN/A 0x6: decode TOPCODE_7_5 { 1137104SN/A 0x2: WarnUnimpl::setend(); 1147104SN/A 0x3: WarnUnimpl::cps(); 1157104SN/A } 1167104SN/A } 1177104SN/A 0x3: decode TOPCODE_10_8 { 1187104SN/A 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 1197104SN/A 0x2: decode TOPCODE_7_6 { 1207104SN/A 0x0: WarnUnimpl::rev(); 1217104SN/A 0x1: WarnUnimpl::rev16(); 1227104SN/A 0x3: WarnUnimpl::revsh(); 1237104SN/A } 1247104SN/A 0x4, 0x5: WarnUnimpl::pop(); 1257104SN/A 0x6: WarnUnimpl::bkpt(); 1267104SN/A 0x7: decode TOPCODE_3_0 { 1277104SN/A 0x0: WarnUnimpl::it(); 1287104SN/A default: decode TOPCODE_7_4 { 1297104SN/A 0x0: WarnUnimpl::nop(); 1307104SN/A 0x1: WarnUnimpl::yield(); 1317104SN/A 0x2: WarnUnimpl::wfe(); 1327104SN/A 0x3: WarnUnimpl::wfi(); 1337104SN/A 0x4: WarnUnimpl::sev(); 1347104SN/A default: WarnUnimpl::unallocated_hint(); 1357104SN/A } 1367104SN/A } 1377104SN/A } 1387104SN/A } 1397104SN/A 0x6: decode TOPCODE_12_11 { 1407135Sgblack@eecs.umich.edu 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem(); 1417104SN/A default: decode TOPCODE_11_8 { 1427104SN/A 0xe: WarnUnimpl::undefined(); // permanently undefined 1437104SN/A 0xf: WarnUnimpl::svc(); // formerly swi 1447104SN/A default: WarnUnimpl::b(); // conditional 1457104SN/A } 1467104SN/A } 1477104SN/A 0x7: decode TOPCODE_12_11 { 1487104SN/A 0x0: WarnUnimpl::b(); // unconditional 1497104SN/A } 1507104SN/A } 1517107SN/A 1527107SN/A // 32 bit thumb instructions. 1537107SN/A 1: decode HTOPCODE_12_11 { 1547107SN/A 0x1: decode HTOPCODE_10_9 { 1557107SN/A 0x0: decode HTOPCODE_8_6 { 1567107SN/A 0x0, 0x6: decode HTOPCODE_4 { 1577107SN/A 0x0: WarnUnimpl::srs(); 1587107SN/A 0x1: WarnUnimpl::rfe(); 1597107SN/A } 1607107SN/A 0x1: decode HTOPCODE_5_4 { 1617107SN/A 0x0: WarnUnimpl::strex(); 1627107SN/A 0x1: WarnUnimpl::ldrex(); 1637107SN/A 0x2: WarnUnimpl::strd(); // immediate 1647107SN/A 0x3: decode HTRN { 1657107SN/A 0xf: WarnUnimpl::ldrd(); // literal 1667107SN/A default: WarnUnimpl::ldrd(); // immediate 1677107SN/A } 1687107SN/A } 1697136Sgblack@eecs.umich.edu // This uses the same encoding as regular ARM. 1707136Sgblack@eecs.umich.edu 0x2: ArmMacroMem::armMacroMem(); 1717107SN/A 0x3: decode HTOPCODE_5_4 { 1727107SN/A 0x0: decode LTOPCODE_7_4 { 1737107SN/A 0x4: WarnUnimpl::strexb(); 1747107SN/A 0x5: WarnUnimpl::strexh(); 1757107SN/A 0x7: WarnUnimpl::strexd(); 1767107SN/A } 1777107SN/A 0x1: decode LTOPCODE_7_4 { 1787107SN/A 0x0: WarnUnimpl::tbb(); 1797107SN/A 0x1: WarnUnimpl::tbh(); 1807107SN/A 0x4: WarnUnimpl::ldrexb(); 1817107SN/A 0x5: WarnUnimpl::ldrexh(); 1827107SN/A 0x7: WarnUnimpl::ldrexd(); 1837107SN/A } 1847107SN/A 0x2: WarnUnimpl::strd(); // immediate 1857107SN/A 0x3: decode HTRN { 1867107SN/A 0xf: WarnUnimpl::ldrd(); // literal 1877107SN/A default: WarnUnimpl::ldrd(); // immediate 1887107SN/A } 1897107SN/A } 1907136Sgblack@eecs.umich.edu // This uses the same encoding as regular ARM. 1917136Sgblack@eecs.umich.edu 0x4: ArmMacroMem::armMacroMem(); 1927107SN/A 0x5, 0x7: decode HTOPCODE_4 { 1937107SN/A 0x0: WarnUnimpl::strd(); // immediate 1947107SN/A 0x1: decode HTRN { 1957107SN/A 0xf: WarnUnimpl::ldrd(); // literal 1967107SN/A default: WarnUnimpl::ldrd(); // immediate 1977107SN/A } 1987107SN/A } 1997107SN/A } 2007107SN/A 0x1: decode HTOPCODE_8_5 { 2017107SN/A 0x0: decode LTRD { 2027107SN/A 0xf: decode HTS { 2037107SN/A 0x1: WarnUnimpl::tst(); // register 2047107SN/A } 2057107SN/A default: WarnUnimpl::and(); // register 2067107SN/A } 2077107SN/A 0x1: WarnUnimpl::bic(); // register 2087107SN/A 0x2: decode HTRN { 2097107SN/A 0xf: WarnUnimpl::mov(); // register 2107107SN/A default: WarnUnimpl::orr(); // register 2117107SN/A } 2127107SN/A 0x3: decode HTRN { 2137107SN/A 0xf: WarnUnimpl::mvn(); // register 2147107SN/A default: WarnUnimpl::orn(); // register 2157107SN/A } 2167107SN/A 0x4: decode LTRD { 2177107SN/A 0xf: decode HTS { 2187107SN/A 0x1: WarnUnimpl::teq(); // register 2197107SN/A } 2207107SN/A default: WarnUnimpl::eor(); // register 2217107SN/A } 2227107SN/A 0x6: WarnUnimpl::pkh(); 2237107SN/A 0x8: decode LTRD { 2247107SN/A 0xf: decode HTS { 2257107SN/A 0x1: WarnUnimpl::cmn(); // register 2267107SN/A } 2277107SN/A default: WarnUnimpl::add(); // register 2287107SN/A } 2297107SN/A 0xa: WarnUnimpl::adc(); // register 2307107SN/A 0xb: WarnUnimpl::sbc(); // register 2317107SN/A 0xd: decode LTRD { 2327107SN/A 0xf: decode HTS { 2337107SN/A 0x1: WarnUnimpl::cmp(); // register 2347107SN/A } 2357107SN/A default: WarnUnimpl::sub(); // register 2367107SN/A } 2377107SN/A 0xe: WarnUnimpl::rsb(); // register 2387107SN/A } 2397107SN/A default: decode HTOPCODE_9_8 { 2407107SN/A 0x2: decode LTOPCODE_4 { 2417107SN/A 0x0: decode LTCOPROC { 2427107SN/A 0xa, 0xb: decode OPCODE_23_20 { 2437117Sgblack@eecs.umich.edu##include "vfp.isa" 2447107SN/A } 2457107SN/A default: WarnUnimpl::cdp(); // cdp2 2467107SN/A } 2477107SN/A 0x1: decode LTCOPROC { 2487107SN/A 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 2497107SN/A default: decode HTOPCODE_4 { 2507107SN/A 0x0: WarnUnimpl::mcr(); // mcr2 2517107SN/A 0x1: WarnUnimpl::mrc(); // mrc2 2527107SN/A } 2537107SN/A } 2547107SN/A } 2557107SN/A 0x3: WarnUnimpl::Advanced_SIMD(); 2567107SN/A default: decode LTCOPROC { 2577107SN/A 0xa, 0xb: decode HTOPCODE_9_4 { 2587107SN/A 0x00: WarnUnimpl::undefined(); 2597107SN/A 0x04: WarnUnimpl::mcrr(); // mcrr2 2607107SN/A 0x05: WarnUnimpl::mrrc(); // mrrc2 2617107SN/A 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 2627107SN/A 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 2637107SN/A WarnUnimpl::stc(); // stc2 2647107SN/A 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 2657107SN/A 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 2667107SN/A decode HTRN { 2677107SN/A 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 2687107SN/A default: WarnUnimpl::ldc(); // ldc2 (immediate) 2697107SN/A } 2707107SN/A } 2717107SN/A default: decode HTOPCODE_9_5 { 2727107SN/A 0x00: WarnUnimpl::undefined(); 2737107SN/A 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 2747107SN/A 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 2757107SN/A 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 2767107SN/A WarnUnimpl::Extension_register_load_store_instruction(); 2777107SN/A } 2787107SN/A } 2797107SN/A } 2807107SN/A } 2817107SN/A 0x2: decode LTOPCODE_15 { 2827107SN/A 0x0: decode HTOPCODE_9 { 2837108SN/A 0x0: decode HTOPCODE_8_5 { 2847108SN/A 0x0: decode LTRD { 2857108SN/A 0xf: decode HTS { 2867112SN/A 0x1: DataModImmOp::tst({{ 2877112SN/A resTemp = Rn & rotated_imm; 2887112SN/A }}); 2897108SN/A } 2907112SN/A default: DataModImmOp::and({{ 2917112SN/A Rs = resTemp = Rn & rotated_imm; 2927112SN/A }}); 2937108SN/A } 2947112SN/A 0x1: DataModImmOp::bic({{ 2957112SN/A Rs = resTemp = Rn & ~rotated_imm; 2967112SN/A }}); 2977108SN/A 0x2: decode HTRN { 2987112SN/A 0xf: DataModImmOp::mov({{ 2997112SN/A Rs = resTemp = rotated_imm; 3007112SN/A }}); 3017112SN/A default: DataModImmOp::orr({{ 3027112SN/A Rs = resTemp = Rn | rotated_imm; 3037112SN/A }}); 3047108SN/A } 3057108SN/A 0x3: decode HTRN { 3067112SN/A 0xf: DataModImmOp::mvn({{ 3077112SN/A Rs = resTemp = ~rotated_imm; 3087112SN/A }}); 3097112SN/A default: DataModImmOp::orn({{ 3107112SN/A Rs = resTemp = Rn | ~rotated_imm; 3117112SN/A }}); 3127108SN/A } 3137108SN/A 0x4: decode LTRD { 3147108SN/A 0xf: decode HTS { 3157112SN/A 0x1: DataModImmOp::teq({{ 3167112SN/A resTemp = Rn ^ rotated_imm; 3177112SN/A }}); 3187108SN/A } 3197112SN/A default: DataModImmOp::eor({{ 3207112SN/A Rs = resTemp = Rn ^ rotated_imm; 3217112SN/A }}); 3227108SN/A } 3237108SN/A 0x8: decode LTRD { 3247108SN/A 0xf: decode HTS { 3257112SN/A 0x1: DataModImmOp::cmn({{ 3267112SN/A resTemp = Rn + rotated_imm; 3277112SN/A }}, add); 3287108SN/A } 3297112SN/A default: DataModImmOp::add({{ 3307112SN/A Rs = resTemp = Rn + rotated_imm; 3317112SN/A }}, add); 3327108SN/A } 3337112SN/A 0xa: DataModImmOp::adc({{ 3347112SN/A Rs = resTemp = Rn + rotated_imm + CondCodes<29:>; 3357112SN/A }}, add); 3367112SN/A 0xb: DataModImmOp::sbc({{ 3377112SN/A Rs = resTemp = Rn - rotated_imm - !CondCodes<29:>; 3387112SN/A }}, sub); 3397108SN/A 0xd: decode LTRD { 3407108SN/A 0xf: decode HTS { 3417112SN/A 0x1: DataModImmOp::cmp({{ 3427112SN/A resTemp = Rn - rotated_imm; 3437112SN/A }}, sub); 3447108SN/A } 3457112SN/A default: DataModImmOp::sub({{ 3467112SN/A Rs = resTemp = Rn - rotated_imm; 3477112SN/A }}, sub); 3487108SN/A } 3497112SN/A 0xe: DataModImmOp::rsb({{ 3507112SN/A Rs = resTemp = rotated_imm - Rn; 3517112SN/A }}, rsb); 3527108SN/A } 3537107SN/A 0x1: WarnUnimpl::Data_processing_plain_binary_immediate(); 3547107SN/A } 3557107SN/A 0x1: WarnUnimpl::Branches_and_miscellaneous_control(); 3567107SN/A } 3577107SN/A 0x3: decode HTOPCODE_10_9 { 3587107SN/A 0x0: decode HTOPCODE_4 { 3597107SN/A 0x0: decode HTOPCODE_8 { 3607123Sgblack@eecs.umich.edu 0x0: Thumb32StoreSingle::thumb32StoreSingle(); 3617107SN/A 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store(); 3627107SN/A } 3637107SN/A 0x1: decode HTOPCODE_6_5 { 3647107SN/A 0x0: WarnUnimpl::Load_byte_memory_hints(); 3657107SN/A 0x1: WarnUnimpl::Load_halfword_memory_hints(); 3667121Sgblack@eecs.umich.edu 0x2: Thumb32LoadWord::thumb32LoadWord(); 3677107SN/A 0x3: WarnUnimpl::undefined(); 3687107SN/A } 3697107SN/A } 3707107SN/A 0x1: decode HTOPCODE_8_7 { 3717107SN/A 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference(); 3727107SN/A 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide(); 3737107SN/A default: WarnUnimpl::Data_processing_register(); 3747107SN/A } 3757107SN/A default: decode HTOPCODE_9_8 { 3767107SN/A 0x2: decode LTOPCODE_4 { 3777107SN/A 0x0: decode LTCOPROC { 3787107SN/A 0xa, 0xb: WarnUnimpl::VFP_Inst(); 3797107SN/A default: WarnUnimpl::cdp(); // cdp2 3807107SN/A } 3817107SN/A 0x1: decode LTCOPROC { 3827107SN/A 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 3837107SN/A default: decode HTOPCODE_4 { 3847107SN/A 0x0: WarnUnimpl::mcr(); // mcr2 3857107SN/A 0x1: WarnUnimpl::mrc(); // mrc2 3867107SN/A } 3877107SN/A } 3887107SN/A } 3897107SN/A 0x3: WarnUnimpl::Advanced_SIMD(); 3907107SN/A default: decode LTCOPROC { 3917107SN/A 0xa, 0xb: decode HTOPCODE_9_4 { 3927107SN/A 0x00: WarnUnimpl::undefined(); 3937107SN/A 0x04: WarnUnimpl::mcrr(); // mcrr2 3947107SN/A 0x05: WarnUnimpl::mrrc(); // mrrc2 3957107SN/A 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 3967107SN/A 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 3977107SN/A WarnUnimpl::stc(); // stc2 3987107SN/A 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 3997107SN/A 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 4007107SN/A decode HTRN { 4017107SN/A 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 4027107SN/A default: WarnUnimpl::ldc(); // ldc2 (immediate) 4037107SN/A } 4047107SN/A } 4057107SN/A default: decode HTOPCODE_9_5 { 4067107SN/A 0x00: WarnUnimpl::undefined(); 4077107SN/A 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 4087107SN/A 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 4097107SN/A 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 4107107SN/A WarnUnimpl::Extension_register_load_store_instruction(); 4117107SN/A } 4127107SN/A } 4137107SN/A } 4147107SN/A } 4157107SN/A } 4166268SN/A} 417