arm.isa revision 7161
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode ENCODING { 54format DataOp { 55 0x0: decode SEVEN_AND_FOUR { 56 1: decode MISC_OPCODE { 57 0x9: decode PREPOST { 58 0: ArmMultAndMultAcc::armMultAndMultAcc(); 59 1: decode PUBWL { 60 0x10: WarnUnimpl::swp(); 61 0x14: WarnUnimpl::swpb(); 62 0x18: WarnUnimpl::strex(); 63 0x19: WarnUnimpl::ldrex(); 64 } 65 } 66 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 67 } 68 0: decode IS_MISC { 69 0: ArmDataProcReg::armDataProcReg(); 70 1: decode OPCODE_7 { 71 0x0: decode MISC_OPCODE { 72 0x0: decode OPCODE { 73 0x8: PredOp::mrs_cpsr({{ 74 Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 75 }}); 76 0x9: decode USEIMM { 77 // The mask field is the same as the RN index. 78 0: PredOp::msr_cpsr_reg({{ 79 uint32_t newCpsr = 80 cpsrWriteByInstr(Cpsr | CondCodes, 81 Rm, RN, false); 82 Cpsr = ~CondCodesMask & newCpsr; 83 CondCodes = CondCodesMask & newCpsr; 84 }}); 85 1: PredImmOp::msr_cpsr_imm({{ 86 uint32_t newCpsr = 87 cpsrWriteByInstr(Cpsr | CondCodes, 88 rotated_imm, RN, false); 89 Cpsr = ~CondCodesMask & newCpsr; 90 CondCodes = CondCodesMask & newCpsr; 91 }}); 92 } 93 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 94 0xb: decode USEIMM { 95 // The mask field is the same as the RN index. 96 0: PredOp::msr_spsr_reg({{ 97 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 98 }}); 99 1: PredImmOp::msr_spsr_imm({{ 100 Spsr = spsrWriteByInstr(Spsr, rotated_imm, 101 RN, false); 102 }}); 103 } 104 } 105 0x1: decode OPCODE { 106 0x9: ArmBx::armBx(); 107 0xb: PredOp::clz({{ 108 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 109 }}); 110 } 111 0x2: decode OPCODE { 112 0x9: WarnUnimpl::bxj(); 113 } 114 0x3: decode OPCODE { 115 0x9: ArmBlxReg::armBlxReg(); 116 } 117 0x5: decode OPCODE { 118 0x8: WarnUnimpl::qadd(); 119 0x9: WarnUnimpl::qsub(); 120 0xa: WarnUnimpl::qdadd(); 121 0xb: WarnUnimpl::qdsub(); 122 } 123 } 124 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 125 } 126 } 127 } 128 0x1: decode IS_MISC { 129 0: ArmDataProcImm::armDataProcImm(); 130 1: decode OPCODE { 131 // The following two instructions aren't supposed to be defined 132 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 133 0x9: decode RN { 134 0: decode IMM { 135 0: PredImmOp::nop({{ ; }}); 136 1: WarnUnimpl::yield(); 137 2: WarnUnimpl::wfe(); 138 3: WarnUnimpl::wfi(); 139 4: WarnUnimpl::sev(); 140 } 141 default: PredImmOp::msr_i_cpsr({{ 142 uint32_t newCpsr = 143 cpsrWriteByInstr(Cpsr | CondCodes, 144 rotated_imm, RN, false); 145 Cpsr = ~CondCodesMask & newCpsr; 146 CondCodes = CondCodesMask & newCpsr; 147 }}); 148 } 149 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 150 0xb: PredImmOp::msr_i_spsr({{ 151 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 152 }}); 153 } 154 } 155 0x2: AddrMode2::addrMode2(True); 156 0x3: decode OPCODE_4 { 157 0: AddrMode2::addrMode2(False); 158 1: decode OPCODE_24_23 { 159 0x0: WarnUnimpl::parallel_add_subtract_instructions(); 160 0x1: decode MEDIA_OPCODE { 161 0x8: decode MISC_OPCODE { 162 0x1, 0x9: WarnUnimpl::pkhbt(); 163 0x7: WarnUnimpl::sxtab16(); 164 0xb: WarnUnimpl::sel(); 165 0x5, 0xd: WarnUnimpl::pkhtb(); 166 0x3: WarnUnimpl::sign_zero_extend_add(); 167 } 168 0xa, 0xb: decode SHIFT { 169 0x0, 0x2: WarnUnimpl::ssat(); 170 0x1: WarnUnimpl::ssat16(); 171 } 172 0xe, 0xf: decode SHIFT { 173 0x0, 0x2: WarnUnimpl::usat(); 174 0x1: WarnUnimpl::usat16(); 175 } 176 } 177 0x2: ArmSignedMultiplies::armSignedMultiplies(); 178 0x3: decode MEDIA_OPCODE { 179 0x18: decode RN { 180 0xf: WarnUnimpl::usada8(); 181 default: WarnUnimpl::usad8(); 182 } 183 } 184 } 185 } 186 0x4: ArmMacroMem::armMacroMem(); 187 0x5: decode OPCODE_24 { 188 0: ArmBBlxImm::armBBlxImm(); 189 1: ArmBlBlxImm::armBlBlxImm(); 190 } 191 0x6: decode CPNUM { 192 0xb: decode LOADOP { 193 0x0: WarnUnimpl::fstmx(); 194 0x1: WarnUnimpl::fldmx(); 195 } 196 } 197 0x7: decode OPCODE_24 { 198 0: decode OPCODE_4 { 199 0: decode CPNUM { 200 0xa, 0xb: decode OPCODE_23_20 { 201##include "vfp.isa" 202 } 203 } // CPNUM 204 1: decode CPNUM { // 27-24=1110,4 ==1 205 1: decode OPCODE_15_12 { 206 format FloatOp { 207 0xf: decode OPCODE_23_21 { 208 format FloatCmp { 209 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 210 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 211 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 212 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 213 } 214 } 215 default: decode OPCODE_23_20 { 216 0x0: decode OPCODE_7 { 217 0: flts({{ Fn.sf = (float) Rd.sw; }}); 218 1: fltd({{ Fn.df = (double) Rd.sw; }}); 219 } 220 0x1: decode OPCODE_7 { 221 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 222 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 223 } 224 0x2: wfs({{ Fpsr = Rd; }}); 225 0x3: rfs({{ Rd = Fpsr; }}); 226 0x4: FailUnimpl::wfc(); 227 0x5: FailUnimpl::rfc(); 228 } 229 } // format FloatOp 230 } 231 0xa: decode MISC_OPCODE { 232 0x1: decode MEDIA_OPCODE { 233 0xf: decode RN { 234 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 235 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 236 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 237 } 238 0xe: decode RN { 239 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 240 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 241 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 242 } 243 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 244 } // MISC_OPCODE (CPNUM 0xA) 245 0xf: decode RN { 246 // Barrriers, Cache Maintence, NOPS 247 7: decode OPCODE_23_21 { 248 0: decode RM { 249 0: decode OPC2 { 250 4: decode OPCODE_20 { 251 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 252 } 253 } 254 1: WarnUnimpl::cp15_cache_maint(); 255 4: WarnUnimpl::cp15_par(); 256 5: decode OPC2 { 257 0,1: WarnUnimpl::cp15_cache_maint2(); 258 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 259 6,7: WarnUnimpl::cp15_bp_maint(); 260 } 261 6: WarnUnimpl::cp15_cache_maint3(); 262 8: WarnUnimpl::cp15_va_to_pa(); 263 10: decode OPC2 { 264 1,2: WarnUnimpl::cp15_cache_maint3(); 265 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 266 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 267 } 268 11: WarnUnimpl::cp15_cache_maint4(); 269 13: decode OPC2 { 270 1: decode OPCODE_20 { 271 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 272 } 273 } 274 14: WarnUnimpl::cp15_cache_maint5(); 275 } // RM 276 } // OPCODE_23_21 CR 277 278 // Thread ID and context ID registers 279 // Thread ID register needs cheaper access than miscreg 280 13: WarnUnimpl::mcr_mrc_cp15_c7(); 281 282 // All the rest 283 default: decode OPCODE_20 { 284 0: PredOp::mcr_cp15({{ 285 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 286 }}); 287 1: PredOp::mrc_cp15({{ 288 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 289 }}); 290 } 291 } // RN 292 } // CPNUM (OP4 == 1) 293 } //OPCODE_4 294 295#if FULL_SYSTEM 296 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 297#else 298 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 299 { 300 if (IMMED_23_0) 301 xc->syscall(IMMED_23_0); 302 else 303 xc->syscall(R7); 304 } 305 }}); 306#endif // FULL_SYSTEM 307 } // OPCODE_24 308 309} 310} 311 312