arm.isa revision 6747
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40 41decode ENCODING default Unknown::unknown() { 42format DataOp { 43 0x0: decode SEVEN_AND_FOUR { 44 1: decode MISC_OPCODE { 45 0x9: decode PREPOST { 46 0: decode OPCODE { 47 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 48 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 49 0x2: WarnUnimpl::umall(); 50 0x4: umull({{ 51 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 52 Rd = (uint32_t)(resTemp & 0xffffffff); 53 Rn = (uint32_t)(resTemp >> 32); 54 }}, llbit); 55 0x5: smlal({{ 56 resTemp = ((int64_t)Rm) * ((int64_t)Rs); 57 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd); 58 Rd = (uint32_t)(resTemp & 0xffffffff); 59 Rn = (uint32_t)(resTemp >> 32); 60 }}, llbit); 61 0x6: smull({{ 62 resTemp = ((int64_t)(int32_t)Rm)* 63 ((int64_t)(int32_t)Rs); 64 Rd = (int32_t)(resTemp & 0xffffffff); 65 Rn = (int32_t)(resTemp >> 32); 66 }}, llbit); 67 0x7: umlal({{ 68 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 69 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 70 Rd = (uint32_t)(resTemp & 0xffffffff); 71 Rn = (uint32_t)(resTemp >> 32); 72 }}, llbit); 73 } 74 1: decode PUBWL { 75 0x10: WarnUnimpl::swp(); 76 0x14: WarnUnimpl::swpb(); 77 0x18: WarnUnimpl::strex(); 78 0x19: WarnUnimpl::ldrex(); 79 } 80 } 81 format AddrMode3 { 82 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, 83 load, {{ Rd = Mem.uh; }}); 84 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); 85 Rdo = bits(Mem.ud, 63, 32); }}, 86 load, {{ Rd = Mem.sb; }}); 87 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | 88 (Rdo.ud << 32); }}, 89 load, {{ Rd = Mem.sh; }}); 90 } 91 } 92 0: decode IS_MISC { 93 0: decode OPCODE { 94 0x0: and({{ Rd = resTemp = Rn & op2; }}); 95 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 96 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); 97 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); 98 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); 99 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add); 100 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub); 101 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb); 102 0x8: tst({{ resTemp = Rn & op2; }}); 103 0x9: teq({{ resTemp = Rn ^ op2; }}); 104 0xa: cmp({{ resTemp = Rn - op2; }}, sub); 105 0xb: cmn({{ resTemp = Rn + op2; }}, add); 106 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 107 0xd: mov({{ Rd = resTemp = op2; }}); 108 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 109 0xf: mvn({{ Rd = resTemp = ~op2; }}); 110 } 111 1: decode MISC_OPCODE { 112 0x0: decode OPCODE { 113 0x8: PredOp::mrs_cpsr({{ 114 Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 115 }}); 116 0x9: PredOp::msr_cpsr({{ 117 //assert(!RN<1:0>); 118 if (OPCODE_18) { 119 Cpsr = Cpsr<31:20> | mbits(Rm, 19, 16) | Cpsr<15:0>; 120 } 121 if (OPCODE_19) { 122 CondCodes = mbits(Rm, 31,27); 123 } 124 }}); 125 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 126 0xb: WarnUnimpl::msr_spsr(); 127 } 128 0x1: decode OPCODE { 129 0x9: BranchExchange::bx({{ }}); 130 0xb: PredOp::clz({{ 131 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 132 }}); 133 } 134 0x2: decode OPCODE { 135 0x9: WarnUnimpl::bxj(); 136 } 137 0x3: decode OPCODE { 138 0x9: BranchExchange::blx({{ }}, Link); 139 } 140 0x5: decode OPCODE { 141 0x8: WarnUnimpl::qadd(); 142 0x9: WarnUnimpl::qsub(); 143 0xa: WarnUnimpl::qdadd(); 144 0xb: WarnUnimpl::qdsub(); 145 } 146 0x8: decode OPCODE { 147 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 148 0x9: WarnUnimpl::smlalbb(); 149 0xa: WarnUnimpl::smlawb(); 150 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none); 151 } 152 0xa: decode OPCODE { 153 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 154 0x9: smulwb({{ 155 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16); 156 }}, none); 157 0xa: WarnUnimpl::smlaltb(); 158 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none); 159 } 160 0xc: decode OPCODE { 161 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 162 0x9: WarnUnimpl::smlawt(); 163 0xa: WarnUnimpl::smlalbt(); 164 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none); 165 } 166 0xe: decode OPCODE { 167 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 168 0x9: smulwt({{ 169 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16); 170 }}, none); 171 0xa: WarnUnimpl::smlaltt(); 172 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none); 173 } 174 } 175 } 176 } 177 0x1: decode IS_MISC { 178 0: decode OPCODE { 179 format DataImmOp { 180 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 181 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 182 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); 183 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); 184 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); 185 0x5: adci({{ 186 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>; 187 }}, add); 188 0x6: sbci({{ 189 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>; 190 }}, sub); 191 0x7: rsci({{ 192 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>; 193 }}, rsb); 194 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 195 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 196 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); 197 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); 198 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 199 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 200 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 201 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 202 } 203 } 204 1: decode OPCODE { 205 // The following two instructions aren't supposed to be defined 206 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 207 0x9: DataImmOp::msr_ia_cpsr ({{ 208 //assert(!RN<1:0>); 209 if (OPCODE_18) { 210 Cpsr = Cpsr<31:20> | rotated_imm | Cpsr<15:0>; 211 } 212 if (OPCODE_19) { 213 CondCodes = rotated_imm; 214 } 215 }}); 216 217 0xa: WarnUnimpl::mrs_i_cpsr(); 218 0xb: WarnUnimpl::mrs_i_spsr(); 219 } 220 } 221 0x2: AddrMode2::addrMode2(Disp, disp); 222 0x3: decode OPCODE_4 { 223 0: AddrMode2::addrMode2(Shift, Rm_Imm); 224 1: decode MEDIA_OPCODE { 225 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 226 0x8: decode MISC_OPCODE { 227 0x1, 0x9: WarnUnimpl::pkhbt(); 228 0x7: WarnUnimpl::sxtab16(); 229 0xb: WarnUnimpl::sel(); 230 0x5, 0xd: WarnUnimpl::pkhtb(); 231 0x3: WarnUnimpl::sign_zero_extend_add(); 232 } 233 0xa, 0xb: decode SHIFT { 234 0x0, 0x2: WarnUnimpl::ssat(); 235 0x1: WarnUnimpl::ssat16(); 236 } 237 0xe, 0xf: decode SHIFT { 238 0x0, 0x2: WarnUnimpl::usat(); 239 0x1: WarnUnimpl::usat16(); 240 } 241 0x10: decode RN { 242 0xf: decode MISC_OPCODE { 243 0x1: WarnUnimpl::smuad(); 244 0x3: WarnUnimpl::smuadx(); 245 0x5: WarnUnimpl::smusd(); 246 0x7: WarnUnimpl::smusdx(); 247 } 248 default: decode MISC_OPCODE { 249 0x1: WarnUnimpl::smlad(); 250 0x3: WarnUnimpl::smladx(); 251 0x5: WarnUnimpl::smlsd(); 252 0x7: WarnUnimpl::smlsdx(); 253 } 254 } 255 0x14: decode MISC_OPCODE { 256 0x1: WarnUnimpl::smlald(); 257 0x3: WarnUnimpl::smlaldx(); 258 0x5: WarnUnimpl::smlsld(); 259 0x7: WarnUnimpl::smlsldx(); 260 } 261 0x15: decode RN { 262 0xf: decode MISC_OPCODE { 263 0x1: WarnUnimpl::smmul(); 264 0x3: WarnUnimpl::smmulr(); 265 } 266 default: decode MISC_OPCODE { 267 0x1: WarnUnimpl::smmla(); 268 0x3: WarnUnimpl::smmlar(); 269 0xd: WarnUnimpl::smmls(); 270 0xf: WarnUnimpl::smmlsr(); 271 } 272 } 273 0x18: decode RN { 274 0xf: WarnUnimpl::usada8(); 275 default: WarnUnimpl::usad8(); 276 } 277 } 278 } 279 0x4: decode PUSWL { 280 // Right now we only handle cases when S (PSRUSER) is not set 281 default: ArmMacroStore::ldmstm({{ }}); 282 } 283 0x5: decode OPCODE_24 { 284 // Branch (and Link) Instructions 285 0: Branch::b({{ }}); 286 1: Branch::bl({{ }}, Link); 287 } 288 0x6: decode CPNUM { 289 0x1: decode PUNWL { 290 0x02,0x0a: decode OPCODE_15 { 291 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 292 Rn = Rn + disp8; }}, 293 {{ EA = Rn; }}); 294 1: ArmMacroFPAOp::stfd_({{ }}); 295 } 296 0x03,0x0b: decode OPCODE_15 { 297 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 298 Rn = Rn + disp8; }}, 299 {{ EA = Rn; }}); 300 1: ArmMacroFPAOp::ldfd_({{ }}); 301 } 302 0x06,0x0e: decode OPCODE_15 { 303 0: ArmMacroFPAOp::stfe_nw({{ }}); 304 } 305 0x07,0x0f: decode OPCODE_15 { 306 0: ArmMacroFPAOp::ldfe_nw({{ }}); 307 } 308 0x10,0x18: decode OPCODE_15 { 309 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 310 {{ EA = Rn + disp8; }}); 311 1: ArmMacroFPAOp::stfd_p({{ }}); 312 } 313 0x11,0x19: decode OPCODE_15 { 314 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 315 {{ EA = Rn + disp8; }}); 316 1: ArmMacroFPAOp::ldfd_p({{ }}); 317 } 318 0x12,0x1a: decode OPCODE_15 { 319 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 320 Rn = Rn + disp8; }}, 321 {{ EA = Rn + disp8; }}); 322 1: ArmMacroFPAOp::stfd_pw({{ }}); 323 } 324 0x13,0x1b: decode OPCODE_15 { 325 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 326 Rn = Rn + disp8; }}, 327 {{ EA = Rn + disp8; }}); 328 1: ArmMacroFPAOp::ldfd_pw({{ }}); 329 } 330 0x14,0x1c: decode OPCODE_15 { 331 0: ArmMacroFPAOp::stfe_pn({{ }}); 332 } 333 0x15,0x1d: decode OPCODE_15 { 334 0: ArmMacroFPAOp::ldfe_pn({{ }}); 335 } 336 0x16,0x1e: decode OPCODE_15 { 337 0: ArmMacroFPAOp::stfe_pnw({{ }}); 338 } 339 0x17,0x1f: decode OPCODE_15 { 340 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 341 } 342 } 343 0x2: decode PUNWL { 344 // could really just decode as a single instruction 345 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 346 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 347 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 348 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 349 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 350 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 351 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 352 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 353 } 354 0xb: decode LOADOP { 355 0x0: WarnUnimpl::fstmx(); 356 0x1: WarnUnimpl::fldmx(); 357 } 358 } 359 0x7: decode OPCODE_24 { 360 0: decode OPCODE_4 { 361 0: decode CPNUM { 362 format FloatOp { 363 0x1: decode OPCODE_23_20 { 364 0x0: decode OPCODE_15 { 365 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 366 1: mvf({{ Fd.sf = Fm.sf; }}); 367 } 368 0x1: decode OPCODE_15 { 369 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 370 1: mnf({{ Fd.sf = -Fm.sf; }}); 371 } 372 0x2: decode OPCODE_15 { 373 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 374 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 375 } 376 0x3: decode OPCODE_15 { 377 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 378 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 379 } 380 0x4: decode OPCODE_15 { 381 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 382 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 383 } 384 0x5: decode OPCODE_15 { 385 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 386 1: log({{ Fd.sf = log10(Fm.sf); }}); 387 } 388 0x6: decode OPCODE_15 { 389 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 390 1: lgn({{ Fd.sf = log(Fm.sf); }}); 391 } 392 0x7: decode OPCODE_15 { 393 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 394 1: exp({{ Fd.sf = exp(Fm.sf); }}); 395 } 396 0x8: decode OPCODE_15 { 397 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 398 1: sin({{ Fd.sf = sin(Fm.sf); }}); 399 } 400 0x9: decode OPCODE_15 { 401 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 402 1: cos({{ Fd.sf = cos(Fm.sf); }}); 403 } 404 0xa: decode OPCODE_15 { 405 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 406 1: tan({{ Fd.sf = tan(Fm.sf); }}); 407 } 408 0xb: decode OPCODE_15 { 409 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 410 1: asn({{ Fd.sf = asin(Fm.sf); }}); 411 } 412 0xc: decode OPCODE_15 { 413 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 414 1: acs({{ Fd.sf = acos(Fm.sf); }}); 415 } 416 0xd: decode OPCODE_15 { 417 1: atn({{ Fd.sf = atan(Fm.sf); }}); 418 } 419 0xe: decode OPCODE_15 { 420 // Unnormalised Round 421 1: FailUnimpl::urd(); 422 } 423 0xf: decode OPCODE_15 { 424 // Normalise 425 1: FailUnimpl::nrm(); 426 } 427 } // OPCODE_23_20 428 } // format FloatOp 429 } // CPNUM 430 1: decode CPNUM { // 27-24=1110,4 ==1 431 1: decode OPCODE_15_12 { 432 format FloatOp { 433 0xf: decode OPCODE_23_21 { 434 format FloatCmp { 435 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 436 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 437 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 438 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 439 } 440 } 441 default: decode OPCODE_23_20 { 442 0x0: decode OPCODE_7 { 443 0: flts({{ Fn.sf = (float) Rd.sw; }}); 444 1: fltd({{ Fn.df = (double) Rd.sw; }}); 445 } 446 0x1: decode OPCODE_7 { 447 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 448 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 449 } 450 0x2: wfs({{ Fpsr = Rd; }}); 451 0x3: rfs({{ Rd = Fpsr; }}); 452 0x4: FailUnimpl::wfc(); 453 0x5: FailUnimpl::rfc(); 454 } 455 } // format FloatOp 456 } 457 0xa: decode MISC_OPCODE { 458 0x1: decode MEDIA_OPCODE { 459 0xf: decode RN { 460 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 461 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 462 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 463 } 464 0xe: decode RN { 465 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 466 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 467 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 468 } 469 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 470 } // MISC_OPCODE (CPNUM 0xA) 471 0xf: decode OPCODE_20 { 472 0: WarnUnimpl::mcr_cp15(); 473 1: WarnUnimpl::mrc_cp15(); 474 } 475 } // CPNUM (OP4 == 1) 476 } //OPCODE_4 477 478#if FULL_SYSTEM 479 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 480#else 481 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 482 { 483 if (IMMED_23_0) 484 xc->syscall(IMMED_23_0); 485 else 486 xc->syscall(R7); 487 } 488 }}); 489#endif // FULL_SYSTEM 490 } // OPCODE_24 491 492} 493} 494 495