arm.isa revision 6272
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40decode COND_CODE default Unknown::unknown() { 41 0xf: decode COND_CODE { 42 0x0: decode OPCODE { 43 // Just a simple trick to allow us to specify our new uops here 44 0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }}, 45 'IsMicroop'); 46 0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }}, 47 'IsMicroop'); 48 0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }}, 49 {{ EA = Raddr + disp; }}, 50 inst_flags = [IsMicroop]); 51 0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }}, 52 {{ EA = Raddr + disp; }}, 53 inst_flags = [IsMicroop]); 54 0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }}, 55 'IsMicroop'); 56 0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }}, 57 'IsMicroop'); 58 } 59 0x1: decode OPCODE { 60 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }}, 61 'IsMicroop'); 62 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff; 63 Rlo = Fd.ud & 0xffffffff; }}, 64 'IsMicroop'); 65 0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }}, 66 {{ EA = Rn + disp; }}, 67 inst_flags = [IsMicroop]); 68 0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }}, 69 {{ EA = Rn + disp; }}, 70 inst_flags = [IsMicroop]); 71 0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }}, 72 {{ EA = Rn + disp; }}, 73 inst_flags = [IsMicroop]); 74 0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }}, 75 {{ EA = Rn + disp; }}, 76 inst_flags = [IsMicroop]); 77 } 78 default: Unknown::unknown(); // TODO: Ignore other NV space for now 79 } 80default: decode ENCODING { 81format DataOp { 82 0x0: decode SEVEN_AND_FOUR { 83 1: decode MISC_OPCODE { 84 0x9: decode PREPOST { 85 0: decode OPCODE { 86 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, 87 {{ Cpsr<29:> }}, 88 {{ Cpsr<28:> }}); 89 0x1: mla({{ Rn = resTemp = Rm * Rs; }}, 90 {{ Cpsr<29:> }}, 91 {{ Cpsr<28:> }}); 92 0x2: WarnUnimpl::umall(); 93 0x4: umull({{ 94 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 95 Rd = (uint32_t)(resTemp & 0xffffffff); 96 Rn = (uint32_t)(resTemp >> 32); 97 }}, {{ 1 }}, {{ 1 }}); 98 0x5: WarnUnimpl::smlal(); 99 0x6: smull({{ 100 resTemp = ((int64_t)(int32_t)Rm)* 101 ((int64_t)(int32_t)Rs); 102 Rd = (int32_t)(resTemp & 0xffffffff); 103 Rn = (int32_t)(resTemp >> 32); 104 }}, {{ 1 }}, {{ 1 }}); 105 0x7: umlal({{ 106 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 107 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 108 Rd = (uint32_t)(resTemp & 0xffffffff); 109 Rn = (uint32_t)(resTemp >> 32); 110 }}, {{ 1 }}, {{ 1 }}); 111 } 112 1: decode PUBWL { 113 0x10: WarnUnimpl::swp(); 114 0x14: WarnUnimpl::swpb(); 115 0x18: WarnUnimpl::strex(); 116 0x19: WarnUnimpl::ldrex(); 117 } 118 } 119 0xb: decode PUBWL { 120 format ArmStoreMemory { 121 0x0, 0x8: strh_({{ Mem.uh = Rd.uh; 122 Rn = Rn + Rm; }}, 123 {{ EA = Rn; }}); 124 0x4, 0xc: strh_il({{ Mem.uh = Rd.uh; 125 Rn = Rn + hilo; }}, 126 {{ EA = Rn; }}); 127 0x10, 0x18: strh_p({{ Mem.uh = Rd.uh; }}, 128 {{ EA = Rn + Rm; }}); 129 0x12, 0x1a: strh_pw({{ Mem.uh = Rd.uh; 130 Rn = Rn + Rm; }}, 131 {{ EA = Rn + Rm; }}); 132 0x14, 0x1c: strh_pil({{ Mem.uh = Rd.uh; }}, 133 {{ EA = Rn + hilo; }}); 134 0x16, 0x1e: strh_piwl({{ Mem.uh = Rd.uh; 135 Rn = Rn + hilo; }}, 136 {{ EA = Rn + hilo; }}); 137 } 138 format ArmLoadMemory { 139 0x1, 0x9: ldrh_l({{ Rd.uh = Mem.uh; 140 Rn = Rn + Rm; }}, 141 {{ EA = Rn; }}); 142 0x5, 0xd: ldrh_il({{ Rd.uh = Mem.uh; 143 Rn = Rn + hilo; }}, 144 {{ EA = Rn; }}); 145 0x11, 0x19: ldrh_pl({{ Rd.uh = Mem.uh; }}, 146 {{ EA = Rn + Rm; }}); 147 0x13, 0x1b: ldrh_pwl({{ Rd.uh = Mem.uh; 148 Rn = Rn + Rm; }}, 149 {{ EA = Rn + Rm; }}); 150 0x15, 0x1d: ldrh_pil({{ Rd.uh = Mem.uh; }}, 151 {{ EA = Rn + hilo; }}); 152 0x17, 0x1f: ldrh_piwl({{ Rd.uh = Mem.uh; 153 Rn = Rn + hilo; }}, 154 {{ EA = Rn + hilo; }}); 155 } 156 } 157 format ArmLoadMemory { 158 0xd: decode PUBWL { 159 0x1: ldrsb_l({{ Rd = Mem.sb; 160 Rn = Rn + Rm; }}, 161 {{ EA = Rn; }}); 162 0x5: ldrsb_il({{ Rd = Mem.sb; 163 Rn = Rn + hilo; }}, 164 {{ EA = Rn; }}); 165 0x9: ldrsb_ul({{ Rd = Mem.sb; 166 Rn = Rn - Rm; }}, 167 {{ EA = Rn; }}); 168 0xd: ldrsb_uil({{ Rd = Mem.sb; 169 Rn = Rn - hilo; }}, 170 {{ EA = Rn; }}); 171 0x11: ldrsb_pl({{ Rd = Mem.sb; }}, 172 {{ EA = Rn + Rm; }}); 173 0x13: ldrsb_pwl({{ Rd = Mem.sb; 174 Rn = Rn + Rm; }}, 175 {{ EA = Rn + Rm; }}); 176 0x15: ldrsb_pil({{ Rd = Mem.sb; }}, 177 {{ EA = Rn + hilo; }}); 178 0x17: ldrsb_piwl({{ Rd = Mem.sb; 179 Rn = Rn + hilo; }}, 180 {{ EA = Rn + hilo; }}); 181 0x19: ldrsb_pul({{ Rd = Mem.sb; }}, 182 {{ EA = Rn - Rm; }}); 183 0x1b: ldrsb_puwl({{ Rd = Mem.sb; 184 Rn = Rn - Rm; }}, 185 {{ EA = Rn - Rm; }}); 186 0x1d: ldrsb_puil({{ Rd = Mem.sb; }}, 187 {{ EA = Rn - hilo; }}); 188 0x1f: ldrsb_puiwl({{ Rd = Mem.sb; 189 Rn = Rn - hilo; }}, 190 {{ EA = Rn - hilo; }}); 191 } 192 0xf: decode PUBWL { 193 0x1: ldrsh_l({{ Rd = Mem.sh; 194 Rn = Rn + Rm; }}, 195 {{ EA = Rn; }}); 196 0x5: ldrsh_il({{ Rd = Mem.sh; 197 Rn = Rn + hilo; }}, 198 {{ EA = Rn; }}); 199 0x9: ldrsh_ul({{ Rd = Mem.sh; 200 Rn = Rn - Rm; }}, 201 {{ EA = Rn; }}); 202 0xd: ldrsh_uil({{ Rd = Mem.sh; 203 Rn = Rn - hilo; }}, 204 {{ EA = Rn; }}); 205 0x11: ldrsh_pl({{ Rd = Mem.sh; }}, 206 {{ EA = Rn + Rm; }}); 207 0x13: ldrsh_pwl({{ Rd = Mem.sh; 208 Rn = Rn + Rm; }}, 209 {{ EA = Rn + Rm; }}); 210 0x15: ldrsh_pil({{ Rd = Mem.sh; }}, 211 {{ EA = Rn + hilo; }}); 212 0x17: ldrsh_piwl({{ Rd = Mem.sh; 213 Rn = Rn + hilo; }}, 214 {{ EA = Rn + hilo; }}); 215 0x19: ldrsh_pul({{ Rd = Mem.sh; }}, 216 {{ EA = Rn - Rm; }}); 217 0x1b: ldrsh_puwl({{ Rd = Mem.sh; 218 Rn = Rn - Rm; }}, 219 {{ EA = Rn - Rm; }}); 220 0x1d: ldrsh_puil({{ Rd = Mem.sh; }}, 221 {{ EA = Rn - hilo; }}); 222 0x1f: ldrsh_puiwl({{ Rd = Mem.sh; 223 Rn = Rn - hilo; }}, 224 {{ EA = Rn - hilo; }}); 225 } 226 } 227 } 228 0: decode IS_MISC { 229 0: decode OPCODE { 230 0x0: and({{ Rd = resTemp = Rn & op2; }}, 231 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 232 {{ Cpsr<28:> }}); 233 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}, 234 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 235 {{ Cpsr<28:> }}); 236 0x2: sub({{ Rd = resTemp = Rn - op2; }}, 237 {{ arm_sub_carry(resTemp, Rn, op2) }}, 238 {{ arm_sub_overflow(resTemp, Rn, op2) }}); 239 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, 240 {{ arm_sub_carry(resTemp, op2, Rn) }}, 241 {{ arm_sub_overflow(resTemp, op2, Rn) }}); 242 0x4: add({{ Rd = resTemp = Rn + op2; }}, 243 {{ arm_add_carry(resTemp, Rn, op2) }}, 244 {{ arm_add_overflow(resTemp, Rn, op2) }}); 245 0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }}, 246 {{ arm_add_carry(resTemp, Rn, op2) }}, 247 {{ arm_add_overflow(resTemp, Rn, op2) }}); 248 0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }}, 249 {{ arm_sub_carry(resTemp, Rn, op2) }}, 250 {{ arm_sub_overflow(resTemp, Rn, op2) }}); 251 0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }}, 252 {{ arm_sub_carry(resTemp, op2, Rn) }}, 253 {{ arm_sub_overflow(resTemp, op2, Rn) }}); 254 0x8: tst({{ resTemp = Rn & op2; }}, 255 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 256 {{ Cpsr<28:> }}); 257 0x9: teq({{ resTemp = Rn ^ op2; }}, 258 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 259 {{ Cpsr<28:> }}); 260 0xa: cmp({{ resTemp = Rn - op2; }}, 261 {{ arm_sub_carry(resTemp, Rn, op2) }}, 262 {{ arm_sub_overflow(resTemp, Rn, op2) }}); 263 0xb: cmn({{ resTemp = Rn + op2; }}, 264 {{ arm_add_carry(resTemp, Rn, op2) }}, 265 {{ arm_add_overflow(resTemp, Rn, op2) }}); 266 0xc: orr({{ Rd = resTemp = Rn | op2; }}, 267 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 268 {{ Cpsr<28:> }}); 269 0xd: mov({{ Rd = resTemp = op2; }}, 270 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 271 {{ Cpsr<28:> }}); 272 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}, 273 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 274 {{ Cpsr<28:> }}); 275 0xf: mvn({{ Rd = resTemp = ~op2; }}, 276 {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }}, 277 {{ Cpsr<28:> }}); 278 } 279 1: decode MISC_OPCODE { 280 0x0: decode OPCODE { 281 0x8: WarnUnimpl::mrs_cpsr(); 282 0x9: WarnUnimpl::msr_cpsr(); 283 0xa: WarnUnimpl::mrs_spsr(); 284 0xb: WarnUnimpl::msr_spsr(); 285 } 286 0x1: decode OPCODE { 287 0x9: BranchExchange::bx({{ }}); 288 0xb: PredOp::clz({{ 289 if (Rm == 0) 290 Rd = 32; 291 else 292 { 293 int i; 294 for (i = 0; i < 32; i++) 295 { 296 if (Rm & (1<<(31-i))) 297 break; 298 } 299 Rd = i; 300 } 301 }}); 302 } 303 0x2: decode OPCODE { 304 0x9: WarnUnimpl::bxj(); 305 } 306 0x3: decode OPCODE { 307 0x9: BranchExchange::blx({{ }}, Link); 308 } 309 0x5: decode OPCODE { 310 0x8: WarnUnimpl::qadd(); 311 0x9: WarnUnimpl::qsub(); 312 0xa: WarnUnimpl::qdadd(); 313 0xb: WarnUnimpl::qdsub(); 314 } 315 0x8: decode OPCODE { 316 0x8: WarnUnimpl::smlabb(); 317 0x9: WarnUnimpl::smlalbb(); 318 0xa: WarnUnimpl::smlawb(); 319 0xb: WarnUnimpl::smulbb(); 320 } 321 0xa: decode OPCODE { 322 0x8: WarnUnimpl::smlatb(); 323 0x9: WarnUnimpl::smulwb(); 324 0xa: WarnUnimpl::smlaltb(); 325 0xb: WarnUnimpl::smultb(); 326 } 327 0xc: decode OPCODE { 328 0x8: WarnUnimpl::smlabt(); 329 0x9: WarnUnimpl::smlawt(); 330 0xa: WarnUnimpl::smlalbt(); 331 0xb: WarnUnimpl::smulbt(); 332 } 333 0xe: decode OPCODE { 334 0x8: WarnUnimpl::smlatt(); 335 0x9: WarnUnimpl::smulwt(); 336 0xa: WarnUnimpl::smlaltt(); 337 0xb: WarnUnimpl::smultt(); 338 } 339 } 340 } 341 } 342 0x1: decode IS_MISC { 343 0: decode OPCODE { 344 format DataImmOp { 345 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}, 346 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 347 {{ Cpsr<28:> }}); 348 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}, 349 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 350 {{ Cpsr<28:> }}); 351 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, 352 {{ arm_sub_carry(resTemp, Rn, rotated_imm) }}, 353 {{ arm_sub_overflow(resTemp, Rn, rotated_imm) }}); 354 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, 355 {{ arm_sub_carry(resTemp, rotated_imm, Rn) }}, 356 {{ arm_sub_overflow(resTemp, rotated_imm, Rn) }}); 357 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, 358 {{ arm_add_carry(resTemp, Rn, rotated_imm) }}, 359 {{ arm_add_overflow(resTemp, Rn, rotated_imm) }}); 360 0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }}, 361 {{ arm_add_carry(resTemp, Rn, rotated_imm) }}, 362 {{ arm_add_overflow(resTemp, Rn, rotated_imm) }}); 363 0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }}, 364 {{ arm_sub_carry(resTemp, Rn, rotated_imm) }}, 365 {{ arm_sub_overflow(resTemp, Rn, rotated_imm) }}); 366 0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}}, 367 {{ arm_sub_carry(resTemp, rotated_imm, Rn) }}, 368 {{ arm_sub_overflow(resTemp, rotated_imm, Rn) }}); 369 0x8: tsti({{ resTemp = Rn & rotated_imm; }}, 370 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 371 {{ Cpsr<28:> }}); 372 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}, 373 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 374 {{ Cpsr<28:> }}); 375 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, 376 {{ arm_sub_carry(resTemp, Rn, rotated_imm) }}, 377 {{ arm_sub_overflow(resTemp, Rn, rotated_imm) }}); 378 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, 379 {{ arm_add_carry(resTemp, Rn, rotated_imm) }}, 380 {{ arm_add_overflow(resTemp, Rn, rotated_imm) }}); 381 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}, 382 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 383 {{ Cpsr<28:> }}); 384 0xd: movi({{ Rd = resTemp = rotated_imm; }}, 385 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 386 {{ Cpsr<28:> }}); 387 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}, 388 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 389 {{ Cpsr<28:> }}); 390 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}, 391 {{ (rotate ? rotated_carry:Cpsr<29:>) }}, 392 {{ Cpsr<28:> }}); 393 } 394 } 395 1: decode OPCODE { 396 // The following two instructions aren't supposed to be defined 397 0x8: WarnUnimpl::undefined_instruction(); 398 0x9: WarnUnimpl::undefined_instruction(); 399 400 0xa: WarnUnimpl::mrs_i_cpsr(); 401 0xb: WarnUnimpl::mrs_i_spsr(); 402 } 403 } 404 0x2: decode PUBWL { 405 // CAREFUL: 406 // Can always do EA + disp, since we negate disp using the UP flag 407 // Post-indexed variants 408 0x00,0x08: ArmStoreMemory::str_({{ Mem = Rd; 409 Rn = Rn + disp; }}, 410 {{ EA = Rn; }}); 411 0x01,0x09: ArmLoadMemory::ldr_l({{ Rn = Rn + disp; 412 Rd = Mem; }}, 413 {{ EA = Rn; }}); 414 0x04,0x0c: ArmStoreMemory::strb_b({{ Mem.ub = Rd.ub; 415 Rn = Rn + disp; }}, 416 {{ EA = Rn; }}); 417 0x05,0x0d: ArmLoadMemory::ldrb_bl({{ Rn = Rn + disp; 418 Rd.ub = Mem.ub; }}, 419 {{ EA = Rn; }}); 420 // Pre-indexed variants 421 0x10,0x18: ArmStoreMemory::str_p({{ Mem = Rd; }}); 422 0x11,0x19: ArmLoadMemory::ldr_pl({{ Rd = Mem; }}); 423 0x12,0x1a: ArmStoreMemory::str_pw({{ Mem = Rd; 424 Rn = Rn + disp; }}); 425 0x13,0x1b: ArmLoadMemory::ldr_pwl({{ Rn = Rn + disp; 426 Rd = Mem; }}); 427 0x14,0x1c: ArmStoreMemory::strb_pb({{ Mem.ub = Rd.ub; }}); 428 0x15,0x1d: ArmLoadMemory::ldrb_pbl({{ Rd.ub = Mem.ub; }}); 429 0x16,0x1e: ArmStoreMemory::strb_pbw({{ Mem.ub = Rd.ub; 430 Rn = Rn + disp; }}); 431 0x17,0x1f: ArmLoadMemory::ldrb_pbwl({{ Rn = Rn + disp; 432 Rd.ub = Mem.ub; }}); 433 } 434 0x3: decode OPCODE_4 { 435 0: decode PUBWL { 436 0x00,0x08: ArmStoreMemory::strr_({{ 437 Mem = Rd; 438 Rn = Rn + Rm_Imm; }}, 439 {{ EA = Rn; }}); 440 0x01,0x09: ArmLoadMemory::ldrr_l({{ 441 Rd = Mem; 442 Rn = Rn + Rm_Imm; }}, 443 {{ EA = Rn; }}); 444 0x04,0x0c: ArmStoreMemory::strr_b({{ 445 Mem.ub = Rd.ub; 446 Rn = Rn + Rm_Imm; }}, 447 {{ EA = Rn; }}); 448 0x05,0x0d: ArmLoadMemory::ldrr_bl({{ 449 Rd.ub = Mem.ub; 450 Rn = Rn + Rm_Imm; }}, 451 {{ EA = Rn; }}); 452 0x10,0x18: ArmStoreMemory::strr_p({{ 453 Mem = Rd; }}, 454 {{ EA = Rn + Rm_Imm; }}); 455 0x11,0x19: ArmLoadMemory::ldrr_pl({{ 456 Rd = Mem; }}, 457 {{ EA = Rn + Rm_Imm; }}); 458 0x12,0x1a: ArmStoreMemory::strr_pw({{ 459 Mem = Rd; 460 Rn = Rn + Rm_Imm; }}, 461 {{ EA = Rn + Rm_Imm; }}); 462 0x13,0x1b: ArmLoadMemory::ldrr_pwl({{ 463 Rd = Mem; 464 Rn = Rn + Rm_Imm; }}, 465 {{ EA = Rn + Rm_Imm; }}); 466 0x14,0x1c: ArmStoreMemory::strr_pb({{ 467 Mem.ub = Rd.ub; }}, 468 {{ EA = Rn + Rm_Imm; }}); 469 0x15,0x1d: ArmLoadMemory::ldrr_pbl({{ 470 Rd.ub = Mem.ub; }}, 471 {{ EA = Rn + Rm_Imm; }}); 472 0x16,0x1e: ArmStoreMemory::strr_pbw({{ 473 Mem.ub = Rd.ub; 474 Rn = Rn + Rm_Imm; }}, 475 {{ EA = Rn + Rm_Imm; }}); 476 0x17,0x1f: ArmLoadMemory::ldrr_pbwl({{ 477 Rd.ub = Mem.ub; 478 Rn = Rn + Rm_Imm; }}, 479 {{ EA = Rn + Rm_Imm; }}); 480 } 481 1: decode MEDIA_OPCODE { 482 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 483 0x8: decode MISC_OPCODE { 484 0x1, 0x9: WarnUnimpl::pkhbt(); 485 0x7: WarnUnimpl::sxtab16(); 486 0xb: WarnUnimpl::sel(); 487 0x5, 0xd: WarnUnimpl::pkhtb(); 488 0x3: WarnUnimpl::sign_zero_extend_add(); 489 } 490 0xa, 0xb: decode SHIFT { 491 0x0, 0x2: WarnUnimpl::ssat(); 492 0x1: WarnUnimpl::ssat16(); 493 } 494 0xe, 0xf: decode SHIFT { 495 0x0, 0x2: WarnUnimpl::usat(); 496 0x1: WarnUnimpl::usat16(); 497 } 498 0x10: decode RN { 499 0xf: decode MISC_OPCODE { 500 0x1: WarnUnimpl::smuad(); 501 0x3: WarnUnimpl::smuadx(); 502 0x5: WarnUnimpl::smusd(); 503 0x7: WarnUnimpl::smusdx(); 504 } 505 default: decode MISC_OPCODE { 506 0x1: WarnUnimpl::smlad(); 507 0x3: WarnUnimpl::smladx(); 508 0x5: WarnUnimpl::smlsd(); 509 0x7: WarnUnimpl::smlsdx(); 510 } 511 } 512 0x14: decode MISC_OPCODE { 513 0x1: WarnUnimpl::smlald(); 514 0x3: WarnUnimpl::smlaldx(); 515 0x5: WarnUnimpl::smlsld(); 516 0x7: WarnUnimpl::smlsldx(); 517 } 518 0x15: decode RN { 519 0xf: decode MISC_OPCODE { 520 0x1: WarnUnimpl::smmul(); 521 0x3: WarnUnimpl::smmulr(); 522 } 523 default: decode MISC_OPCODE { 524 0x1: WarnUnimpl::smmla(); 525 0x3: WarnUnimpl::smmlar(); 526 0xd: WarnUnimpl::smmls(); 527 0xf: WarnUnimpl::smmlsr(); 528 } 529 } 530 0x18: decode RN { 531 0xf: WarnUnimpl::usada8(); 532 default: WarnUnimpl::usad8(); 533 } 534 } 535 } 536 0x4: decode PUSWL { 537 // Right now we only handle cases when S (PSRUSER) is not set 538 default: ArmMacroStore::ldmstm({{ }}); 539 } 540 0x5: decode OPCODE_24 { 541 // Branch (and Link) Instructions 542 0: Branch::b({{ }}); 543 1: Branch::bl({{ }}, Link); 544 } 545 0x6: decode CPNUM { 546 0x1: decode PUNWL { 547 0x02,0x0a: decode OPCODE_15 { 548 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 549 Rn = Rn + disp8; }}, 550 {{ EA = Rn; }}); 551 1: ArmMacroFPAOp::stfd_({{ }}); 552 } 553 0x03,0x0b: decode OPCODE_15 { 554 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 555 Rn = Rn + disp8; }}, 556 {{ EA = Rn; }}); 557 1: ArmMacroFPAOp::ldfd_({{ }}); 558 } 559 0x06,0x0e: decode OPCODE_15 { 560 0: ArmMacroFPAOp::stfe_nw({{ }}); 561 } 562 0x07,0x0f: decode OPCODE_15 { 563 0: ArmMacroFPAOp::ldfe_nw({{ }}); 564 } 565 0x10,0x18: decode OPCODE_15 { 566 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 567 {{ EA = Rn + disp8; }}); 568 1: ArmMacroFPAOp::stfd_p({{ }}); 569 } 570 0x11,0x19: decode OPCODE_15 { 571 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 572 {{ EA = Rn + disp8; }}); 573 1: ArmMacroFPAOp::ldfd_p({{ }}); 574 } 575 0x12,0x1a: decode OPCODE_15 { 576 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 577 Rn = Rn + disp8; }}, 578 {{ EA = Rn + disp8; }}); 579 1: ArmMacroFPAOp::stfd_pw({{ }}); 580 } 581 0x13,0x1b: decode OPCODE_15 { 582 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 583 Rn = Rn + disp8; }}, 584 {{ EA = Rn + disp8; }}); 585 1: ArmMacroFPAOp::ldfd_pw({{ }}); 586 } 587 0x14,0x1c: decode OPCODE_15 { 588 0: ArmMacroFPAOp::stfe_pn({{ }}); 589 } 590 0x15,0x1d: decode OPCODE_15 { 591 0: ArmMacroFPAOp::ldfe_pn({{ }}); 592 } 593 0x16,0x1e: decode OPCODE_15 { 594 0: ArmMacroFPAOp::stfe_pnw({{ }}); 595 } 596 0x17,0x1f: decode OPCODE_15 { 597 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 598 } 599 } 600 0x2: decode PUNWL { 601 // could really just decode as a single instruction 602 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 603 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 604 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 605 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 606 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 607 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 608 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 609 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 610 } 611 } 612 0x7: decode OPCODE_24 { 613 0: decode CPNUM { 614 // Coprocessor Instructions 615 0x1: decode OPCODE_4 { 616 format FloatOp { 617 // Basic FPA Instructions 618 0: decode OPCODE_23_20 { 619 0x0: decode OPCODE_15 { 620 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 621 1: mvf({{ Fd.sf = Fm.sf; }}); 622 } 623 0x1: decode OPCODE_15 { 624 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 625 1: mnf({{ Fd.sf = -Fm.sf; }}); 626 } 627 0x2: decode OPCODE_15 { 628 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 629 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 630 } 631 0x3: decode OPCODE_15 { 632 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 633 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 634 } 635 0x4: decode OPCODE_15 { 636 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 637 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 638 } 639 0x5: decode OPCODE_15 { 640 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 641 1: log({{ Fd.sf = log10(Fm.sf); }}); 642 } 643 0x6: decode OPCODE_15 { 644 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 645 1: lgn({{ Fd.sf = log(Fm.sf); }}); 646 } 647 0x7: decode OPCODE_15 { 648 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 649 1: exp({{ Fd.sf = exp(Fm.sf); }}); 650 } 651 0x8: decode OPCODE_15 { 652 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 653 1: sin({{ Fd.sf = sin(Fm.sf); }}); 654 } 655 0x9: decode OPCODE_15 { 656 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 657 1: cos({{ Fd.sf = cos(Fm.sf); }}); 658 } 659 0xa: decode OPCODE_15 { 660 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 661 1: tan({{ Fd.sf = tan(Fm.sf); }}); 662 } 663 0xb: decode OPCODE_15 { 664 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 665 1: asn({{ Fd.sf = asin(Fm.sf); }}); 666 } 667 0xc: decode OPCODE_15 { 668 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 669 1: acs({{ Fd.sf = acos(Fm.sf); }}); 670 } 671 0xd: decode OPCODE_15 { 672 1: atn({{ Fd.sf = atan(Fm.sf); }}); 673 } 674 0xe: decode OPCODE_15 { 675 // Unnormalised Round 676 1: FailUnimpl::urd(); 677 } 678 0xf: decode OPCODE_15 { 679 // Normalise 680 1: FailUnimpl::nrm(); 681 } 682 } 683 1: decode OPCODE_15_12 { 684 0xf: decode OPCODE_23_21 { 685 format FloatCmp { 686 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 687 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 688 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 689 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 690 } 691 } 692 default: decode OPCODE_23_20 { 693 0x0: decode OPCODE_7 { 694 0: flts({{ Fn.sf = (float) Rd.sw; }}); 695 1: fltd({{ Fn.df = (double) Rd.sw; }}); 696 } 697 0x1: decode OPCODE_7 { 698 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 699 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 700 } 701 0x2: wfs({{ Fpsr = Rd; }}); 702 0x3: rfs({{ Rd = Fpsr; }}); 703 0x4: FailUnimpl::wfc(); 704 0x5: FailUnimpl::rfc(); 705 } 706 } 707 } 708 } 709 } 710 format PredOp { 711 // ARM System Call (SoftWare Interrupt) 712 1: swi({{ if (testPredicate(Cpsr, condCode)) 713 { 714 xc->syscall(IMMED_23_0); 715 } 716 }}); 717 } 718 } 719} 720} 721} 722 723