arm.isa revision 7401
16019SN/A// -*- mode:c++ -*- 26019SN/A 37102SN/A// Copyright (c) 2010 ARM Limited 47102SN/A// All rights reserved 57102SN/A// 67102SN/A// The license below extends only to copyright in the software and shall 77102SN/A// not be construed as granting a license to any other intellectual 87102SN/A// property including but not limited to intellectual property relating 97102SN/A// to a hardware implementation of the functionality of the software 107102SN/A// licensed hereunder. You may use the software subject to the license 117102SN/A// terms below provided that you ensure that this notice is replicated 127102SN/A// unmodified and in its entirety in all distributions of the software, 137102SN/A// modified or unmodified, in source code or in binary form. 147102SN/A// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426019SN/A 436019SN/A//////////////////////////////////////////////////////////////////// 446019SN/A// 456019SN/A// The actual ARM ISA decoder 466019SN/A// -------------------------- 476019SN/A// The following instructions are specified in the ARM ISA 486019SN/A// Specification. Decoding closely follows the style specified 496019SN/A// in the ARM ISA specification document starting with Table B.1 or 3-1 506019SN/A// 516019SN/A// 526310SN/A 537191Sgblack@eecs.umich.edu0: decode COND_CODE { 547191Sgblack@eecs.umich.edu0xF: ArmUnconditional::armUnconditional(); 557191Sgblack@eecs.umich.edudefault: decode ENCODING { 566268SN/Aformat DataOp { 576268SN/A 0x0: decode SEVEN_AND_FOUR { 586268SN/A 1: decode MISC_OPCODE { 596268SN/A 0x9: decode PREPOST { 607161Sgblack@eecs.umich.edu 0: ArmMultAndMultAcc::armMultAndMultAcc(); 617206Sgblack@eecs.umich.edu 1: ArmSyncMem::armSyncMem(); 626019SN/A } 637129Sgblack@eecs.umich.edu 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 646019SN/A } 656268SN/A 0: decode IS_MISC { 667139Sgblack@eecs.umich.edu 0: ArmDataProcReg::armDataProcReg(); 677161Sgblack@eecs.umich.edu 1: decode OPCODE_7 { 687161Sgblack@eecs.umich.edu 0x0: decode MISC_OPCODE { 697203Sgblack@eecs.umich.edu 0x0: ArmMsrMrs::armMsrMrs(); 707344SAli.Saidi@ARM.com // bxj unimplemented, treated as bx 717344SAli.Saidi@ARM.com 0x1,0x2: ArmBxClz::armBxClz(); 727161Sgblack@eecs.umich.edu 0x3: decode OPCODE { 737161Sgblack@eecs.umich.edu 0x9: ArmBlxReg::armBlxReg(); 747161Sgblack@eecs.umich.edu } 757195Sgblack@eecs.umich.edu 0x5: ArmSatAddSub::armSatAddSub(); 767401SAli.Saidi@ARM.com 0x7: Breakpoint::bkpt(); 776268SN/A } 787161Sgblack@eecs.umich.edu 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 796268SN/A } 806268SN/A } 816268SN/A } 826268SN/A 0x1: decode IS_MISC { 837139Sgblack@eecs.umich.edu 0: ArmDataProcImm::armDataProcImm(); 846268SN/A 1: decode OPCODE { 856268SN/A // The following two instructions aren't supposed to be defined 866741SN/A 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 876756SN/A 0x9: decode RN { 886756SN/A 0: decode IMM { 896756SN/A 0: PredImmOp::nop({{ ; }}); 907350SAli.Saidi@ARM.com#if FULL_SYSTEM 917350SAli.Saidi@ARM.com 1: PredImmOp::yield({{ ; }}); 927350SAli.Saidi@ARM.com 2: PredImmOp::wfe({{ 937350SAli.Saidi@ARM.com if (SevMailbox) 947350SAli.Saidi@ARM.com SevMailbox = 0; 957350SAli.Saidi@ARM.com else 967350SAli.Saidi@ARM.com PseudoInst::quiesce(xc->tcBase()); 977350SAli.Saidi@ARM.com }}, IsNonSpeculative, IsQuiesce); 987350SAli.Saidi@ARM.com 3: PredImmOp::wfi({{ 997350SAli.Saidi@ARM.com PseudoInst::quiesce(xc->tcBase()); 1007350SAli.Saidi@ARM.com }}, IsNonSpeculative, IsQuiesce); 1017350SAli.Saidi@ARM.com 4: PredImmOp::sev({{ 1027350SAli.Saidi@ARM.com // Need a way for O3 to not scoreboard these 1037350SAli.Saidi@ARM.com // accesses as pipeflushs 1047350SAli.Saidi@ARM.com System *sys = xc->tcBase()->getSystemPtr(); 1057350SAli.Saidi@ARM.com for (int x = 0; x < sys->numContexts(); x++) { 1067350SAli.Saidi@ARM.com ThreadContext *oc = sys->getThreadContext(x); 1077350SAli.Saidi@ARM.com oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 1087350SAli.Saidi@ARM.com } 1097350SAli.Saidi@ARM.com }}); 1107350SAli.Saidi@ARM.com#endif 1116756SN/A } 1126756SN/A default: PredImmOp::msr_i_cpsr({{ 1137400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 1146756SN/A uint32_t newCpsr = 1156756SN/A cpsrWriteByInstr(Cpsr | CondCodes, 1167400SAli.Saidi@ARM.com rotated_imm, RN, false, sctlr.nmfi); 1176756SN/A Cpsr = ~CondCodesMask & newCpsr; 1186756SN/A CondCodes = CondCodesMask & newCpsr; 1196756SN/A }}); 1206756SN/A } 1216756SN/A 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 1226756SN/A 0xb: PredImmOp::msr_i_spsr({{ 1237102SN/A Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 1246741SN/A }}); 1256019SN/A } 1266268SN/A } 1277120Sgblack@eecs.umich.edu 0x2: AddrMode2::addrMode2(True); 1286268SN/A 0x3: decode OPCODE_4 { 1297120Sgblack@eecs.umich.edu 0: AddrMode2::addrMode2(False); 1307161Sgblack@eecs.umich.edu 1: decode OPCODE_24_23 { 1317194Sgblack@eecs.umich.edu 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 1327210Sgblack@eecs.umich.edu 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 1337161Sgblack@eecs.umich.edu 0x2: ArmSignedMultiplies::armSignedMultiplies(); 1347255Sgblack@eecs.umich.edu 0x3: ArmMiscMedia::armMiscMedia(); 1356269SN/A } 1366268SN/A } 1377134Sgblack@eecs.umich.edu 0x4: ArmMacroMem::armMacroMem(); 1386268SN/A 0x5: decode OPCODE_24 { 1397152Sgblack@eecs.umich.edu 0: ArmBBlxImm::armBBlxImm(); 1407152Sgblack@eecs.umich.edu 1: ArmBlBlxImm::armBlBlxImm(); 1416268SN/A } 1426268SN/A 0x6: decode CPNUM { 1437334Sgblack@eecs.umich.edu 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 1446268SN/A } 1456268SN/A 0x7: decode OPCODE_24 { 1466743SN/A 0: decode OPCODE_4 { 1476743SN/A 0: decode CPNUM { 1487363Sgblack@eecs.umich.edu 0xa, 0xb: VfpData::vfpData(); 1496743SN/A } // CPNUM 1506743SN/A 1: decode CPNUM { // 27-24=1110,4 ==1 1516743SN/A 1: decode OPCODE_15_12 { 1526743SN/A format FloatOp { 1536268SN/A 0xf: decode OPCODE_23_21 { 1546268SN/A format FloatCmp { 1556268SN/A 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 1566268SN/A 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 1576268SN/A 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 1586268SN/A 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 1596019SN/A } 1606019SN/A } 1616268SN/A default: decode OPCODE_23_20 { 1626268SN/A 0x0: decode OPCODE_7 { 1636268SN/A 0: flts({{ Fn.sf = (float) Rd.sw; }}); 1646268SN/A 1: fltd({{ Fn.df = (double) Rd.sw; }}); 1656019SN/A } 1666268SN/A 0x1: decode OPCODE_7 { 1676268SN/A 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 1686268SN/A 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 1696019SN/A } 1706268SN/A 0x2: wfs({{ Fpsr = Rd; }}); 1716268SN/A 0x3: rfs({{ Rd = Fpsr; }}); 1726268SN/A 0x4: FailUnimpl::wfc(); 1736268SN/A 0x5: FailUnimpl::rfc(); 1746019SN/A } 1756743SN/A } // format FloatOp 1766019SN/A } 1777321Sgblack@eecs.umich.edu 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 1787269Sgblack@eecs.umich.edu 0xf: McrMrc15::mcrMrc15(); 1796743SN/A } // CPNUM (OP4 == 1) 1806743SN/A } //OPCODE_4 1816743SN/A 1827199Sgblack@eecs.umich.edu 1: Svc::svc(); 1836743SN/A } // OPCODE_24 1846743SN/A 1856268SN/A} 1866268SN/A} 1877191Sgblack@eecs.umich.edu} 1886019SN/A 189