arm.isa revision 7334
16145Snate@binkert.org// -*- mode:c++ -*- 26145Snate@binkert.org 36145Snate@binkert.org// Copyright (c) 2010 ARM Limited 46145Snate@binkert.org// All rights reserved 56145Snate@binkert.org// 66145Snate@binkert.org// The license below extends only to copyright in the software and shall 76145Snate@binkert.org// not be construed as granting a license to any other intellectual 86145Snate@binkert.org// property including but not limited to intellectual property relating 96145Snate@binkert.org// to a hardware implementation of the functionality of the software 106145Snate@binkert.org// licensed hereunder. You may use the software subject to the license 116145Snate@binkert.org// terms below provided that you ensure that this notice is replicated 126145Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 136145Snate@binkert.org// modified or unmodified, in source code or in binary form. 146145Snate@binkert.org// 156145Snate@binkert.org// Copyright (c) 2007-2008 The Florida State University 166145Snate@binkert.org// All rights reserved. 176145Snate@binkert.org// 186145Snate@binkert.org// Redistribution and use in source and binary forms, with or without 196145Snate@binkert.org// modification, are permitted provided that the following conditions are 206145Snate@binkert.org// met: redistributions of source code must retain the above copyright 216145Snate@binkert.org// notice, this list of conditions and the following disclaimer; 226145Snate@binkert.org// redistributions in binary form must reproduce the above copyright 236145Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 246145Snate@binkert.org// documentation and/or other materials provided with the distribution; 256145Snate@binkert.org// neither the name of the copyright holders nor the names of its 266145Snate@binkert.org// contributors may be used to endorse or promote products derived from 276145Snate@binkert.org// this software without specific prior written permission. 286145Snate@binkert.org// 296145Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307054Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317054Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327054Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337054Snate@binkert.org// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347054Snate@binkert.org// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357054Snate@binkert.org// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366145Snate@binkert.org// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376145Snate@binkert.org// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387054Snate@binkert.org// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397054Snate@binkert.org// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406145Snate@binkert.org// 417055Snate@binkert.org// Authors: Stephen Hines 427454Snate@binkert.org 437055Snate@binkert.org//////////////////////////////////////////////////////////////////// 446154Snate@binkert.org// 457054Snate@binkert.org// The actual ARM ISA decoder 467054Snate@binkert.org// -------------------------- 476154Snate@binkert.org// The following instructions are specified in the ARM ISA 486285Snate@binkert.org// Specification. Decoding closely follows the style specified 496145Snate@binkert.org// in the ARM ISA specification document starting with Table B.1 or 3-1 506145Snate@binkert.org// 516145Snate@binkert.org// 527054Snate@binkert.org 537054Snate@binkert.org0: decode COND_CODE { 547054Snate@binkert.org0xF: ArmUnconditional::armUnconditional(); 557054Snate@binkert.orgdefault: decode ENCODING { 567054Snate@binkert.orgformat DataOp { 577054Snate@binkert.org 0x0: decode SEVEN_AND_FOUR { 587054Snate@binkert.org 1: decode MISC_OPCODE { 596145Snate@binkert.org 0x9: decode PREPOST { 607454Snate@binkert.org 0: ArmMultAndMultAcc::armMultAndMultAcc(); 617454Snate@binkert.org 1: ArmSyncMem::armSyncMem(); 627054Snate@binkert.org } 636145Snate@binkert.org 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 647055Snate@binkert.org } 657054Snate@binkert.org 0: decode IS_MISC { 667055Snate@binkert.org 0: ArmDataProcReg::armDataProcReg(); 677054Snate@binkert.org 1: decode OPCODE_7 { 687054Snate@binkert.org 0x0: decode MISC_OPCODE { 697054Snate@binkert.org 0x0: ArmMsrMrs::armMsrMrs(); 707054Snate@binkert.org 0x1: ArmBxClz::armBxClz(); 717054Snate@binkert.org 0x2: decode OPCODE { 727054Snate@binkert.org 0x9: WarnUnimpl::bxj(); 737054Snate@binkert.org } 747054Snate@binkert.org 0x3: decode OPCODE { 757054Snate@binkert.org 0x9: ArmBlxReg::armBlxReg(); 766145Snate@binkert.org } 777454Snate@binkert.org 0x5: ArmSatAddSub::armSatAddSub(); 787054Snate@binkert.org } 797054Snate@binkert.org 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 807054Snate@binkert.org } 817054Snate@binkert.org } 826145Snate@binkert.org } 837054Snate@binkert.org 0x1: decode IS_MISC { 846145Snate@binkert.org 0: ArmDataProcImm::armDataProcImm(); 857055Snate@binkert.org 1: decode OPCODE { 866145Snate@binkert.org // The following two instructions aren't supposed to be defined 877054Snate@binkert.org 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 887054Snate@binkert.org 0x9: decode RN { 897054Snate@binkert.org 0: decode IMM { 907054Snate@binkert.org 0: PredImmOp::nop({{ ; }}); 916145Snate@binkert.org 1: WarnUnimpl::yield(); 927054Snate@binkert.org 2: WarnUnimpl::wfe(); 937054Snate@binkert.org 3: WarnUnimpl::wfi(); 947054Snate@binkert.org 4: WarnUnimpl::sev(); 956145Snate@binkert.org } 967454Snate@binkert.org default: PredImmOp::msr_i_cpsr({{ 977454Snate@binkert.org uint32_t newCpsr = 987454Snate@binkert.org cpsrWriteByInstr(Cpsr | CondCodes, 997054Snate@binkert.org rotated_imm, RN, false); 1007454Snate@binkert.org Cpsr = ~CondCodesMask & newCpsr; 1017054Snate@binkert.org CondCodes = CondCodesMask & newCpsr; 1027054Snate@binkert.org }}); 1037054Snate@binkert.org } 1047054Snate@binkert.org 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 1057054Snate@binkert.org 0xb: PredImmOp::msr_i_spsr({{ 1066145Snate@binkert.org Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 1077054Snate@binkert.org }}); 1087054Snate@binkert.org } 1097054Snate@binkert.org } 1106145Snate@binkert.org 0x2: AddrMode2::addrMode2(True); 1116145Snate@binkert.org 0x3: decode OPCODE_4 { 1127055Snate@binkert.org 0: AddrMode2::addrMode2(False); 1137055Snate@binkert.org 1: decode OPCODE_24_23 { 1146145Snate@binkert.org 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 1157054Snate@binkert.org 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 1167055Snate@binkert.org 0x2: ArmSignedMultiplies::armSignedMultiplies(); 1177054Snate@binkert.org 0x3: ArmMiscMedia::armMiscMedia(); 1186145Snate@binkert.org } 1196145Snate@binkert.org } 1207054Snate@binkert.org 0x4: ArmMacroMem::armMacroMem(); 121 0x5: decode OPCODE_24 { 122 0: ArmBBlxImm::armBBlxImm(); 123 1: ArmBlBlxImm::armBlBlxImm(); 124 } 125 0x6: decode CPNUM { 126 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 127 } 128 0x7: decode OPCODE_24 { 129 0: decode OPCODE_4 { 130 0: decode CPNUM { 131 0xa, 0xb: decode OPCODE_23_20 { 132##include "vfp.isa" 133 } 134 } // CPNUM 135 1: decode CPNUM { // 27-24=1110,4 ==1 136 1: decode OPCODE_15_12 { 137 format FloatOp { 138 0xf: decode OPCODE_23_21 { 139 format FloatCmp { 140 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 141 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 142 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 143 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 144 } 145 } 146 default: decode OPCODE_23_20 { 147 0x0: decode OPCODE_7 { 148 0: flts({{ Fn.sf = (float) Rd.sw; }}); 149 1: fltd({{ Fn.df = (double) Rd.sw; }}); 150 } 151 0x1: decode OPCODE_7 { 152 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 153 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 154 } 155 0x2: wfs({{ Fpsr = Rd; }}); 156 0x3: rfs({{ Rd = Fpsr; }}); 157 0x4: FailUnimpl::wfc(); 158 0x5: FailUnimpl::rfc(); 159 } 160 } // format FloatOp 161 } 162 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 163 0xf: McrMrc15::mcrMrc15(); 164 } // CPNUM (OP4 == 1) 165 } //OPCODE_4 166 167 1: Svc::svc(); 168 } // OPCODE_24 169 170} 171} 172} 173 174