arm.isa revision 7206
16019SN/A// -*- mode:c++ -*- 26019SN/A 37102SN/A// Copyright (c) 2010 ARM Limited 47102SN/A// All rights reserved 57102SN/A// 67102SN/A// The license below extends only to copyright in the software and shall 77102SN/A// not be construed as granting a license to any other intellectual 87102SN/A// property including but not limited to intellectual property relating 97102SN/A// to a hardware implementation of the functionality of the software 107102SN/A// licensed hereunder. You may use the software subject to the license 117102SN/A// terms below provided that you ensure that this notice is replicated 127102SN/A// unmodified and in its entirety in all distributions of the software, 137102SN/A// modified or unmodified, in source code or in binary form. 147102SN/A// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426019SN/A 436019SN/A//////////////////////////////////////////////////////////////////// 446019SN/A// 456019SN/A// The actual ARM ISA decoder 466019SN/A// -------------------------- 476019SN/A// The following instructions are specified in the ARM ISA 486019SN/A// Specification. Decoding closely follows the style specified 496019SN/A// in the ARM ISA specification document starting with Table B.1 or 3-1 506019SN/A// 516019SN/A// 526310SN/A 537191Sgblack@eecs.umich.edu0: decode COND_CODE { 547191Sgblack@eecs.umich.edu0xF: ArmUnconditional::armUnconditional(); 557191Sgblack@eecs.umich.edudefault: decode ENCODING { 566268SN/Aformat DataOp { 576268SN/A 0x0: decode SEVEN_AND_FOUR { 586268SN/A 1: decode MISC_OPCODE { 596268SN/A 0x9: decode PREPOST { 607161Sgblack@eecs.umich.edu 0: ArmMultAndMultAcc::armMultAndMultAcc(); 617206Sgblack@eecs.umich.edu 1: ArmSyncMem::armSyncMem(); 626019SN/A } 637129Sgblack@eecs.umich.edu 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 646019SN/A } 656268SN/A 0: decode IS_MISC { 667139Sgblack@eecs.umich.edu 0: ArmDataProcReg::armDataProcReg(); 677161Sgblack@eecs.umich.edu 1: decode OPCODE_7 { 687161Sgblack@eecs.umich.edu 0x0: decode MISC_OPCODE { 697203Sgblack@eecs.umich.edu 0x0: ArmMsrMrs::armMsrMrs(); 707161Sgblack@eecs.umich.edu 0x1: decode OPCODE { 717161Sgblack@eecs.umich.edu 0x9: ArmBx::armBx(); 727161Sgblack@eecs.umich.edu 0xb: PredOp::clz({{ 737161Sgblack@eecs.umich.edu Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 746751SN/A }}); 756751SN/A } 767161Sgblack@eecs.umich.edu 0x2: decode OPCODE { 777161Sgblack@eecs.umich.edu 0x9: WarnUnimpl::bxj(); 787161Sgblack@eecs.umich.edu } 797161Sgblack@eecs.umich.edu 0x3: decode OPCODE { 807161Sgblack@eecs.umich.edu 0x9: ArmBlxReg::armBlxReg(); 817161Sgblack@eecs.umich.edu } 827195Sgblack@eecs.umich.edu 0x5: ArmSatAddSub::armSatAddSub(); 836268SN/A } 847161Sgblack@eecs.umich.edu 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 856268SN/A } 866268SN/A } 876268SN/A } 886268SN/A 0x1: decode IS_MISC { 897139Sgblack@eecs.umich.edu 0: ArmDataProcImm::armDataProcImm(); 906268SN/A 1: decode OPCODE { 916268SN/A // The following two instructions aren't supposed to be defined 926741SN/A 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 936756SN/A 0x9: decode RN { 946756SN/A 0: decode IMM { 956756SN/A 0: PredImmOp::nop({{ ; }}); 966756SN/A 1: WarnUnimpl::yield(); 976756SN/A 2: WarnUnimpl::wfe(); 986756SN/A 3: WarnUnimpl::wfi(); 996756SN/A 4: WarnUnimpl::sev(); 1006756SN/A } 1016756SN/A default: PredImmOp::msr_i_cpsr({{ 1026756SN/A uint32_t newCpsr = 1036756SN/A cpsrWriteByInstr(Cpsr | CondCodes, 1046756SN/A rotated_imm, RN, false); 1056756SN/A Cpsr = ~CondCodesMask & newCpsr; 1066756SN/A CondCodes = CondCodesMask & newCpsr; 1076756SN/A }}); 1086756SN/A } 1096756SN/A 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 1106756SN/A 0xb: PredImmOp::msr_i_spsr({{ 1117102SN/A Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 1126741SN/A }}); 1136019SN/A } 1146268SN/A } 1157120Sgblack@eecs.umich.edu 0x2: AddrMode2::addrMode2(True); 1166268SN/A 0x3: decode OPCODE_4 { 1177120Sgblack@eecs.umich.edu 0: AddrMode2::addrMode2(False); 1187161Sgblack@eecs.umich.edu 1: decode OPCODE_24_23 { 1197194Sgblack@eecs.umich.edu 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 1207161Sgblack@eecs.umich.edu 0x1: decode MEDIA_OPCODE { 1217161Sgblack@eecs.umich.edu 0x8: decode MISC_OPCODE { 1227161Sgblack@eecs.umich.edu 0x1, 0x9: WarnUnimpl::pkhbt(); 1237161Sgblack@eecs.umich.edu 0x7: WarnUnimpl::sxtab16(); 1247161Sgblack@eecs.umich.edu 0xb: WarnUnimpl::sel(); 1257161Sgblack@eecs.umich.edu 0x5, 0xd: WarnUnimpl::pkhtb(); 1267161Sgblack@eecs.umich.edu 0x3: WarnUnimpl::sign_zero_extend_add(); 1276269SN/A } 1287161Sgblack@eecs.umich.edu 0xa, 0xb: decode SHIFT { 1297161Sgblack@eecs.umich.edu 0x0, 0x2: WarnUnimpl::ssat(); 1307161Sgblack@eecs.umich.edu 0x1: WarnUnimpl::ssat16(); 1317161Sgblack@eecs.umich.edu } 1327161Sgblack@eecs.umich.edu 0xe, 0xf: decode SHIFT { 1337161Sgblack@eecs.umich.edu 0x0, 0x2: WarnUnimpl::usat(); 1347161Sgblack@eecs.umich.edu 0x1: WarnUnimpl::usat16(); 1356269SN/A } 1366269SN/A } 1377161Sgblack@eecs.umich.edu 0x2: ArmSignedMultiplies::armSignedMultiplies(); 1387161Sgblack@eecs.umich.edu 0x3: decode MEDIA_OPCODE { 1397161Sgblack@eecs.umich.edu 0x18: decode RN { 1407161Sgblack@eecs.umich.edu 0xf: WarnUnimpl::usada8(); 1417161Sgblack@eecs.umich.edu default: WarnUnimpl::usad8(); 1426269SN/A } 1436269SN/A } 1446269SN/A } 1456268SN/A } 1467134Sgblack@eecs.umich.edu 0x4: ArmMacroMem::armMacroMem(); 1476268SN/A 0x5: decode OPCODE_24 { 1487152Sgblack@eecs.umich.edu 0: ArmBBlxImm::armBBlxImm(); 1497152Sgblack@eecs.umich.edu 1: ArmBlBlxImm::armBlBlxImm(); 1506268SN/A } 1516268SN/A 0x6: decode CPNUM { 1527179Sgblack@eecs.umich.edu 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 1536268SN/A } 1546268SN/A 0x7: decode OPCODE_24 { 1556743SN/A 0: decode OPCODE_4 { 1566743SN/A 0: decode CPNUM { 1577105SN/A 0xa, 0xb: decode OPCODE_23_20 { 1587117Sgblack@eecs.umich.edu##include "vfp.isa" 1597105SN/A } 1606743SN/A } // CPNUM 1616743SN/A 1: decode CPNUM { // 27-24=1110,4 ==1 1626743SN/A 1: decode OPCODE_15_12 { 1636743SN/A format FloatOp { 1646268SN/A 0xf: decode OPCODE_23_21 { 1656268SN/A format FloatCmp { 1666268SN/A 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 1676268SN/A 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 1686268SN/A 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 1696268SN/A 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 1706019SN/A } 1716019SN/A } 1726268SN/A default: decode OPCODE_23_20 { 1736268SN/A 0x0: decode OPCODE_7 { 1746268SN/A 0: flts({{ Fn.sf = (float) Rd.sw; }}); 1756268SN/A 1: fltd({{ Fn.df = (double) Rd.sw; }}); 1766019SN/A } 1776268SN/A 0x1: decode OPCODE_7 { 1786268SN/A 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 1796268SN/A 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 1806019SN/A } 1816268SN/A 0x2: wfs({{ Fpsr = Rd; }}); 1826268SN/A 0x3: rfs({{ Rd = Fpsr; }}); 1836268SN/A 0x4: FailUnimpl::wfc(); 1846268SN/A 0x5: FailUnimpl::rfc(); 1856019SN/A } 1866743SN/A } // format FloatOp 1876019SN/A } 1886743SN/A 0xa: decode MISC_OPCODE { 1896743SN/A 0x1: decode MEDIA_OPCODE { 1906743SN/A 0xf: decode RN { 1916743SN/A 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 1926743SN/A 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 1936743SN/A 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 1946743SN/A } 1956743SN/A 0xe: decode RN { 1966743SN/A 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 1976743SN/A 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 1986743SN/A 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 1996743SN/A } 2006743SN/A } // MEDIA_OPCODE (MISC_OPCODE 0x1) 2016743SN/A } // MISC_OPCODE (CPNUM 0xA) 2026759SN/A 0xf: decode RN { 2036759SN/A // Barrriers, Cache Maintence, NOPS 2046759SN/A 7: decode OPCODE_23_21 { 2056759SN/A 0: decode RM { 2066759SN/A 0: decode OPC2 { 2076759SN/A 4: decode OPCODE_20 { 2086759SN/A 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 2096759SN/A } 2106759SN/A } 2116759SN/A 1: WarnUnimpl::cp15_cache_maint(); 2126759SN/A 4: WarnUnimpl::cp15_par(); 2136759SN/A 5: decode OPC2 { 2146759SN/A 0,1: WarnUnimpl::cp15_cache_maint2(); 2156759SN/A 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 2166759SN/A 6,7: WarnUnimpl::cp15_bp_maint(); 2176759SN/A } 2186759SN/A 6: WarnUnimpl::cp15_cache_maint3(); 2196759SN/A 8: WarnUnimpl::cp15_va_to_pa(); 2206759SN/A 10: decode OPC2 { 2216759SN/A 1,2: WarnUnimpl::cp15_cache_maint3(); 2226759SN/A 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 2236759SN/A 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 2246759SN/A } 2256759SN/A 11: WarnUnimpl::cp15_cache_maint4(); 2266759SN/A 13: decode OPC2 { 2276759SN/A 1: decode OPCODE_20 { 2286759SN/A 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 2296759SN/A } 2306759SN/A } 2316759SN/A 14: WarnUnimpl::cp15_cache_maint5(); 2326759SN/A } // RM 2336759SN/A } // OPCODE_23_21 CR 2347102SN/A 2356759SN/A // Thread ID and context ID registers 2366759SN/A // Thread ID register needs cheaper access than miscreg 2377102SN/A 13: WarnUnimpl::mcr_mrc_cp15_c7(); 2386759SN/A 2396759SN/A // All the rest 2406759SN/A default: decode OPCODE_20 { 2417102SN/A 0: PredOp::mcr_cp15({{ 2427102SN/A fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 2436759SN/A }}); 2447102SN/A 1: PredOp::mrc_cp15({{ 2457102SN/A fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 2466759SN/A }}); 2476759SN/A } 2487102SN/A } // RN 2496743SN/A } // CPNUM (OP4 == 1) 2506743SN/A } //OPCODE_4 2516743SN/A 2527199Sgblack@eecs.umich.edu 1: Svc::svc(); 2536743SN/A } // OPCODE_24 2546743SN/A 2556268SN/A} 2566268SN/A} 2577191Sgblack@eecs.umich.edu} 2586019SN/A 259