arm.isa revision 7194
16019SN/A// -*- mode:c++ -*- 26019SN/A 37102SN/A// Copyright (c) 2010 ARM Limited 47102SN/A// All rights reserved 57102SN/A// 67102SN/A// The license below extends only to copyright in the software and shall 77102SN/A// not be construed as granting a license to any other intellectual 87102SN/A// property including but not limited to intellectual property relating 97102SN/A// to a hardware implementation of the functionality of the software 107102SN/A// licensed hereunder. You may use the software subject to the license 117102SN/A// terms below provided that you ensure that this notice is replicated 127102SN/A// unmodified and in its entirety in all distributions of the software, 137102SN/A// modified or unmodified, in source code or in binary form. 147102SN/A// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426019SN/A 436019SN/A//////////////////////////////////////////////////////////////////// 446019SN/A// 456019SN/A// The actual ARM ISA decoder 466019SN/A// -------------------------- 476019SN/A// The following instructions are specified in the ARM ISA 486019SN/A// Specification. Decoding closely follows the style specified 496019SN/A// in the ARM ISA specification document starting with Table B.1 or 3-1 506019SN/A// 516019SN/A// 526310SN/A 537191Sgblack@eecs.umich.edu0: decode COND_CODE { 547191Sgblack@eecs.umich.edu0xF: ArmUnconditional::armUnconditional(); 557191Sgblack@eecs.umich.edudefault: decode ENCODING { 566268SN/Aformat DataOp { 576268SN/A 0x0: decode SEVEN_AND_FOUR { 586268SN/A 1: decode MISC_OPCODE { 596268SN/A 0x9: decode PREPOST { 607161Sgblack@eecs.umich.edu 0: ArmMultAndMultAcc::armMultAndMultAcc(); 616268SN/A 1: decode PUBWL { 626268SN/A 0x10: WarnUnimpl::swp(); 636268SN/A 0x14: WarnUnimpl::swpb(); 646268SN/A 0x18: WarnUnimpl::strex(); 656268SN/A 0x19: WarnUnimpl::ldrex(); 666019SN/A } 676019SN/A } 687129Sgblack@eecs.umich.edu 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 696019SN/A } 706268SN/A 0: decode IS_MISC { 717139Sgblack@eecs.umich.edu 0: ArmDataProcReg::armDataProcReg(); 727161Sgblack@eecs.umich.edu 1: decode OPCODE_7 { 737161Sgblack@eecs.umich.edu 0x0: decode MISC_OPCODE { 747161Sgblack@eecs.umich.edu 0x0: decode OPCODE { 757161Sgblack@eecs.umich.edu 0x8: PredOp::mrs_cpsr({{ 767161Sgblack@eecs.umich.edu Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 776753SN/A }}); 787161Sgblack@eecs.umich.edu 0x9: decode USEIMM { 797161Sgblack@eecs.umich.edu // The mask field is the same as the RN index. 807161Sgblack@eecs.umich.edu 0: PredOp::msr_cpsr_reg({{ 817161Sgblack@eecs.umich.edu uint32_t newCpsr = 827161Sgblack@eecs.umich.edu cpsrWriteByInstr(Cpsr | CondCodes, 837161Sgblack@eecs.umich.edu Rm, RN, false); 847161Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 857161Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 867161Sgblack@eecs.umich.edu }}); 877161Sgblack@eecs.umich.edu 1: PredImmOp::msr_cpsr_imm({{ 887161Sgblack@eecs.umich.edu uint32_t newCpsr = 897161Sgblack@eecs.umich.edu cpsrWriteByInstr(Cpsr | CondCodes, 907161Sgblack@eecs.umich.edu rotated_imm, RN, false); 917161Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 927161Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 937161Sgblack@eecs.umich.edu }}); 947161Sgblack@eecs.umich.edu } 957161Sgblack@eecs.umich.edu 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 967161Sgblack@eecs.umich.edu 0xb: decode USEIMM { 977161Sgblack@eecs.umich.edu // The mask field is the same as the RN index. 987161Sgblack@eecs.umich.edu 0: PredOp::msr_spsr_reg({{ 997161Sgblack@eecs.umich.edu Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 1007161Sgblack@eecs.umich.edu }}); 1017161Sgblack@eecs.umich.edu 1: PredImmOp::msr_spsr_imm({{ 1027161Sgblack@eecs.umich.edu Spsr = spsrWriteByInstr(Spsr, rotated_imm, 1037161Sgblack@eecs.umich.edu RN, false); 1047161Sgblack@eecs.umich.edu }}); 1057161Sgblack@eecs.umich.edu } 1067161Sgblack@eecs.umich.edu } 1077161Sgblack@eecs.umich.edu 0x1: decode OPCODE { 1087161Sgblack@eecs.umich.edu 0x9: ArmBx::armBx(); 1097161Sgblack@eecs.umich.edu 0xb: PredOp::clz({{ 1107161Sgblack@eecs.umich.edu Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 1116751SN/A }}); 1126751SN/A } 1137161Sgblack@eecs.umich.edu 0x2: decode OPCODE { 1147161Sgblack@eecs.umich.edu 0x9: WarnUnimpl::bxj(); 1157161Sgblack@eecs.umich.edu } 1167161Sgblack@eecs.umich.edu 0x3: decode OPCODE { 1177161Sgblack@eecs.umich.edu 0x9: ArmBlxReg::armBlxReg(); 1187161Sgblack@eecs.umich.edu } 1197161Sgblack@eecs.umich.edu 0x5: decode OPCODE { 1207161Sgblack@eecs.umich.edu 0x8: WarnUnimpl::qadd(); 1217161Sgblack@eecs.umich.edu 0x9: WarnUnimpl::qsub(); 1227161Sgblack@eecs.umich.edu 0xa: WarnUnimpl::qdadd(); 1237161Sgblack@eecs.umich.edu 0xb: WarnUnimpl::qdsub(); 1246751SN/A } 1256268SN/A } 1267161Sgblack@eecs.umich.edu 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 1276268SN/A } 1286268SN/A } 1296268SN/A } 1306268SN/A 0x1: decode IS_MISC { 1317139Sgblack@eecs.umich.edu 0: ArmDataProcImm::armDataProcImm(); 1326268SN/A 1: decode OPCODE { 1336268SN/A // The following two instructions aren't supposed to be defined 1346741SN/A 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 1356756SN/A 0x9: decode RN { 1366756SN/A 0: decode IMM { 1376756SN/A 0: PredImmOp::nop({{ ; }}); 1386756SN/A 1: WarnUnimpl::yield(); 1396756SN/A 2: WarnUnimpl::wfe(); 1406756SN/A 3: WarnUnimpl::wfi(); 1416756SN/A 4: WarnUnimpl::sev(); 1426756SN/A } 1436756SN/A default: PredImmOp::msr_i_cpsr({{ 1446756SN/A uint32_t newCpsr = 1456756SN/A cpsrWriteByInstr(Cpsr | CondCodes, 1466756SN/A rotated_imm, RN, false); 1476756SN/A Cpsr = ~CondCodesMask & newCpsr; 1486756SN/A CondCodes = CondCodesMask & newCpsr; 1496756SN/A }}); 1506756SN/A } 1516756SN/A 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 1526756SN/A 0xb: PredImmOp::msr_i_spsr({{ 1537102SN/A Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 1546741SN/A }}); 1556019SN/A } 1566268SN/A } 1577120Sgblack@eecs.umich.edu 0x2: AddrMode2::addrMode2(True); 1586268SN/A 0x3: decode OPCODE_4 { 1597120Sgblack@eecs.umich.edu 0: AddrMode2::addrMode2(False); 1607161Sgblack@eecs.umich.edu 1: decode OPCODE_24_23 { 1617194Sgblack@eecs.umich.edu 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 1627161Sgblack@eecs.umich.edu 0x1: decode MEDIA_OPCODE { 1637161Sgblack@eecs.umich.edu 0x8: decode MISC_OPCODE { 1647161Sgblack@eecs.umich.edu 0x1, 0x9: WarnUnimpl::pkhbt(); 1657161Sgblack@eecs.umich.edu 0x7: WarnUnimpl::sxtab16(); 1667161Sgblack@eecs.umich.edu 0xb: WarnUnimpl::sel(); 1677161Sgblack@eecs.umich.edu 0x5, 0xd: WarnUnimpl::pkhtb(); 1687161Sgblack@eecs.umich.edu 0x3: WarnUnimpl::sign_zero_extend_add(); 1696269SN/A } 1707161Sgblack@eecs.umich.edu 0xa, 0xb: decode SHIFT { 1717161Sgblack@eecs.umich.edu 0x0, 0x2: WarnUnimpl::ssat(); 1727161Sgblack@eecs.umich.edu 0x1: WarnUnimpl::ssat16(); 1737161Sgblack@eecs.umich.edu } 1747161Sgblack@eecs.umich.edu 0xe, 0xf: decode SHIFT { 1757161Sgblack@eecs.umich.edu 0x0, 0x2: WarnUnimpl::usat(); 1767161Sgblack@eecs.umich.edu 0x1: WarnUnimpl::usat16(); 1776269SN/A } 1786269SN/A } 1797161Sgblack@eecs.umich.edu 0x2: ArmSignedMultiplies::armSignedMultiplies(); 1807161Sgblack@eecs.umich.edu 0x3: decode MEDIA_OPCODE { 1817161Sgblack@eecs.umich.edu 0x18: decode RN { 1827161Sgblack@eecs.umich.edu 0xf: WarnUnimpl::usada8(); 1837161Sgblack@eecs.umich.edu default: WarnUnimpl::usad8(); 1846269SN/A } 1856269SN/A } 1866269SN/A } 1876268SN/A } 1887134Sgblack@eecs.umich.edu 0x4: ArmMacroMem::armMacroMem(); 1896268SN/A 0x5: decode OPCODE_24 { 1907152Sgblack@eecs.umich.edu 0: ArmBBlxImm::armBBlxImm(); 1917152Sgblack@eecs.umich.edu 1: ArmBlBlxImm::armBlBlxImm(); 1926268SN/A } 1936268SN/A 0x6: decode CPNUM { 1947179Sgblack@eecs.umich.edu 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 1956268SN/A } 1966268SN/A 0x7: decode OPCODE_24 { 1976743SN/A 0: decode OPCODE_4 { 1986743SN/A 0: decode CPNUM { 1997105SN/A 0xa, 0xb: decode OPCODE_23_20 { 2007117Sgblack@eecs.umich.edu##include "vfp.isa" 2017105SN/A } 2026743SN/A } // CPNUM 2036743SN/A 1: decode CPNUM { // 27-24=1110,4 ==1 2046743SN/A 1: decode OPCODE_15_12 { 2056743SN/A format FloatOp { 2066268SN/A 0xf: decode OPCODE_23_21 { 2076268SN/A format FloatCmp { 2086268SN/A 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 2096268SN/A 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 2106268SN/A 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 2116268SN/A 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 2126019SN/A } 2136019SN/A } 2146268SN/A default: decode OPCODE_23_20 { 2156268SN/A 0x0: decode OPCODE_7 { 2166268SN/A 0: flts({{ Fn.sf = (float) Rd.sw; }}); 2176268SN/A 1: fltd({{ Fn.df = (double) Rd.sw; }}); 2186019SN/A } 2196268SN/A 0x1: decode OPCODE_7 { 2206268SN/A 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 2216268SN/A 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 2226019SN/A } 2236268SN/A 0x2: wfs({{ Fpsr = Rd; }}); 2246268SN/A 0x3: rfs({{ Rd = Fpsr; }}); 2256268SN/A 0x4: FailUnimpl::wfc(); 2266268SN/A 0x5: FailUnimpl::rfc(); 2276019SN/A } 2286743SN/A } // format FloatOp 2296019SN/A } 2306743SN/A 0xa: decode MISC_OPCODE { 2316743SN/A 0x1: decode MEDIA_OPCODE { 2326743SN/A 0xf: decode RN { 2336743SN/A 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 2346743SN/A 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 2356743SN/A 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 2366743SN/A } 2376743SN/A 0xe: decode RN { 2386743SN/A 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 2396743SN/A 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 2406743SN/A 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 2416743SN/A } 2426743SN/A } // MEDIA_OPCODE (MISC_OPCODE 0x1) 2436743SN/A } // MISC_OPCODE (CPNUM 0xA) 2446759SN/A 0xf: decode RN { 2456759SN/A // Barrriers, Cache Maintence, NOPS 2466759SN/A 7: decode OPCODE_23_21 { 2476759SN/A 0: decode RM { 2486759SN/A 0: decode OPC2 { 2496759SN/A 4: decode OPCODE_20 { 2506759SN/A 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 2516759SN/A } 2526759SN/A } 2536759SN/A 1: WarnUnimpl::cp15_cache_maint(); 2546759SN/A 4: WarnUnimpl::cp15_par(); 2556759SN/A 5: decode OPC2 { 2566759SN/A 0,1: WarnUnimpl::cp15_cache_maint2(); 2576759SN/A 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 2586759SN/A 6,7: WarnUnimpl::cp15_bp_maint(); 2596759SN/A } 2606759SN/A 6: WarnUnimpl::cp15_cache_maint3(); 2616759SN/A 8: WarnUnimpl::cp15_va_to_pa(); 2626759SN/A 10: decode OPC2 { 2636759SN/A 1,2: WarnUnimpl::cp15_cache_maint3(); 2646759SN/A 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 2656759SN/A 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 2666759SN/A } 2676759SN/A 11: WarnUnimpl::cp15_cache_maint4(); 2686759SN/A 13: decode OPC2 { 2696759SN/A 1: decode OPCODE_20 { 2706759SN/A 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 2716759SN/A } 2726759SN/A } 2736759SN/A 14: WarnUnimpl::cp15_cache_maint5(); 2746759SN/A } // RM 2756759SN/A } // OPCODE_23_21 CR 2767102SN/A 2776759SN/A // Thread ID and context ID registers 2786759SN/A // Thread ID register needs cheaper access than miscreg 2797102SN/A 13: WarnUnimpl::mcr_mrc_cp15_c7(); 2806759SN/A 2816759SN/A // All the rest 2826759SN/A default: decode OPCODE_20 { 2837102SN/A 0: PredOp::mcr_cp15({{ 2847102SN/A fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 2856759SN/A }}); 2867102SN/A 1: PredOp::mrc_cp15({{ 2877102SN/A fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 2886759SN/A }}); 2896759SN/A } 2907102SN/A } // RN 2916743SN/A } // CPNUM (OP4 == 1) 2926743SN/A } //OPCODE_4 2936743SN/A 2946743SN/A#if FULL_SYSTEM 2957102SN/A 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 2966743SN/A#else 2976743SN/A 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 2986743SN/A { 2996743SN/A if (IMMED_23_0) 3006743SN/A xc->syscall(IMMED_23_0); 3016743SN/A else 3026743SN/A xc->syscall(R7); 3036019SN/A } 3046743SN/A }}); 3056743SN/A#endif // FULL_SYSTEM 3066743SN/A } // OPCODE_24 3076743SN/A 3086268SN/A} 3096268SN/A} 3107191Sgblack@eecs.umich.edu} 3116019SN/A 312