arm.isa revision 6759
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40 41decode ENCODING default Unknown::unknown() { 42format DataOp { 43 0x0: decode SEVEN_AND_FOUR { 44 1: decode MISC_OPCODE { 45 0x9: decode PREPOST { 46 0: decode OPCODE { 47 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 48 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 49 0x2: WarnUnimpl::umall(); 50 0x4: umull({{ 51 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 52 Rd = (uint32_t)(resTemp & 0xffffffff); 53 Rn = (uint32_t)(resTemp >> 32); 54 }}, llbit); 55 0x5: smlal({{ 56 resTemp = ((int64_t)Rm) * ((int64_t)Rs); 57 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd); 58 Rd = (uint32_t)(resTemp & 0xffffffff); 59 Rn = (uint32_t)(resTemp >> 32); 60 }}, llbit); 61 0x6: smull({{ 62 resTemp = ((int64_t)(int32_t)Rm)* 63 ((int64_t)(int32_t)Rs); 64 Rd = (int32_t)(resTemp & 0xffffffff); 65 Rn = (int32_t)(resTemp >> 32); 66 }}, llbit); 67 0x7: umlal({{ 68 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 69 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 70 Rd = (uint32_t)(resTemp & 0xffffffff); 71 Rn = (uint32_t)(resTemp >> 32); 72 }}, llbit); 73 } 74 1: decode PUBWL { 75 0x10: WarnUnimpl::swp(); 76 0x14: WarnUnimpl::swpb(); 77 0x18: WarnUnimpl::strex(); 78 0x19: WarnUnimpl::ldrex(); 79 } 80 } 81 format AddrMode3 { 82 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, 83 load, {{ Rd = Mem.uh; }}); 84 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); 85 Rdo = bits(Mem.ud, 63, 32); }}, 86 load, {{ Rd = Mem.sb; }}); 87 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | 88 (Rdo.ud << 32); }}, 89 load, {{ Rd = Mem.sh; }}); 90 } 91 } 92 0: decode IS_MISC { 93 0: decode OPCODE { 94 0x0: and({{ Rd = resTemp = Rn & op2; }}); 95 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 96 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); 97 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); 98 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); 99 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add); 100 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub); 101 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb); 102 0x8: tst({{ resTemp = Rn & op2; }}); 103 0x9: teq({{ resTemp = Rn ^ op2; }}); 104 0xa: cmp({{ resTemp = Rn - op2; }}, sub); 105 0xb: cmn({{ resTemp = Rn + op2; }}, add); 106 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 107 0xd: mov({{ Rd = resTemp = op2; }}); 108 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 109 0xf: mvn({{ Rd = resTemp = ~op2; }}); 110 } 111 1: decode MISC_OPCODE { 112 0x0: decode OPCODE { 113 0x8: PredOp::mrs_cpsr({{ 114 Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 115 }}); 116 0x9: decode USEIMM { 117 // The mask field is the same as the RN index. 118 0: PredOp::msr_cpsr_reg({{ 119 uint32_t newCpsr = 120 cpsrWriteByInstr(Cpsr | CondCodes, 121 Rm, RN, false); 122 Cpsr = ~CondCodesMask & newCpsr; 123 CondCodes = CondCodesMask & newCpsr; 124 }}); 125 1: PredImmOp::msr_cpsr_imm({{ 126 uint32_t newCpsr = 127 cpsrWriteByInstr(Cpsr | CondCodes, 128 rotated_imm, RN, false); 129 Cpsr = ~CondCodesMask & newCpsr; 130 CondCodes = CondCodesMask & newCpsr; 131 }}); 132 } 133 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 134 0xb: decode USEIMM { 135 // The mask field is the same as the RN index. 136 0: PredOp::msr_spsr_reg({{ 137 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 138 }}); 139 1: PredImmOp::msr_spsr_imm({{ 140 Spsr = spsrWriteByInstr(Spsr, rotated_imm, 141 RN, false); 142 }}); 143 } 144 } 145 0x1: decode OPCODE { 146 0x9: BranchExchange::bx({{ }}); 147 0xb: PredOp::clz({{ 148 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 149 }}); 150 } 151 0x2: decode OPCODE { 152 0x9: WarnUnimpl::bxj(); 153 } 154 0x3: decode OPCODE { 155 0x9: BranchExchange::blx({{ }}, Link); 156 } 157 0x5: decode OPCODE { 158 0x8: WarnUnimpl::qadd(); 159 0x9: WarnUnimpl::qsub(); 160 0xa: WarnUnimpl::qdadd(); 161 0xb: WarnUnimpl::qdsub(); 162 } 163 0x8: decode OPCODE { 164 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 165 0x9: WarnUnimpl::smlalbb(); 166 0xa: WarnUnimpl::smlawb(); 167 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none); 168 } 169 0xa: decode OPCODE { 170 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 171 0x9: smulwb({{ 172 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16); 173 }}, none); 174 0xa: WarnUnimpl::smlaltb(); 175 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none); 176 } 177 0xc: decode OPCODE { 178 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 179 0x9: WarnUnimpl::smlawt(); 180 0xa: WarnUnimpl::smlalbt(); 181 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none); 182 } 183 0xe: decode OPCODE { 184 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 185 0x9: smulwt({{ 186 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16); 187 }}, none); 188 0xa: WarnUnimpl::smlaltt(); 189 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none); 190 } 191 } 192 } 193 } 194 0x1: decode IS_MISC { 195 0: decode OPCODE { 196 format DataImmOp { 197 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 198 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 199 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); 200 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); 201 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); 202 0x5: adci({{ 203 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>; 204 }}, add); 205 0x6: sbci({{ 206 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>; 207 }}, sub); 208 0x7: rsci({{ 209 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>; 210 }}, rsb); 211 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 212 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 213 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); 214 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); 215 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 216 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 217 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 218 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 219 } 220 } 221 1: decode OPCODE { 222 // The following two instructions aren't supposed to be defined 223 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 224 0x9: decode RN { 225 0: decode IMM { 226 0: PredImmOp::nop({{ ; }}); 227 1: WarnUnimpl::yield(); 228 2: WarnUnimpl::wfe(); 229 3: WarnUnimpl::wfi(); 230 4: WarnUnimpl::sev(); 231 } 232 default: PredImmOp::msr_i_cpsr({{ 233 uint32_t newCpsr = 234 cpsrWriteByInstr(Cpsr | CondCodes, 235 rotated_imm, RN, false); 236 Cpsr = ~CondCodesMask & newCpsr; 237 CondCodes = CondCodesMask & newCpsr; 238 }}); 239 } 240 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 241 0xb: PredImmOp::msr_i_spsr({{ 242 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 243 }}); 244 } 245 } 246 0x2: AddrMode2::addrMode2(Disp, disp); 247 0x3: decode OPCODE_4 { 248 0: AddrMode2::addrMode2(Shift, Rm_Imm); 249 1: decode MEDIA_OPCODE { 250 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 251 0x8: decode MISC_OPCODE { 252 0x1, 0x9: WarnUnimpl::pkhbt(); 253 0x7: WarnUnimpl::sxtab16(); 254 0xb: WarnUnimpl::sel(); 255 0x5, 0xd: WarnUnimpl::pkhtb(); 256 0x3: WarnUnimpl::sign_zero_extend_add(); 257 } 258 0xa, 0xb: decode SHIFT { 259 0x0, 0x2: WarnUnimpl::ssat(); 260 0x1: WarnUnimpl::ssat16(); 261 } 262 0xe, 0xf: decode SHIFT { 263 0x0, 0x2: WarnUnimpl::usat(); 264 0x1: WarnUnimpl::usat16(); 265 } 266 0x10: decode RN { 267 0xf: decode MISC_OPCODE { 268 0x1: WarnUnimpl::smuad(); 269 0x3: WarnUnimpl::smuadx(); 270 0x5: WarnUnimpl::smusd(); 271 0x7: WarnUnimpl::smusdx(); 272 } 273 default: decode MISC_OPCODE { 274 0x1: WarnUnimpl::smlad(); 275 0x3: WarnUnimpl::smladx(); 276 0x5: WarnUnimpl::smlsd(); 277 0x7: WarnUnimpl::smlsdx(); 278 } 279 } 280 0x14: decode MISC_OPCODE { 281 0x1: WarnUnimpl::smlald(); 282 0x3: WarnUnimpl::smlaldx(); 283 0x5: WarnUnimpl::smlsld(); 284 0x7: WarnUnimpl::smlsldx(); 285 } 286 0x15: decode RN { 287 0xf: decode MISC_OPCODE { 288 0x1: WarnUnimpl::smmul(); 289 0x3: WarnUnimpl::smmulr(); 290 } 291 default: decode MISC_OPCODE { 292 0x1: WarnUnimpl::smmla(); 293 0x3: WarnUnimpl::smmlar(); 294 0xd: WarnUnimpl::smmls(); 295 0xf: WarnUnimpl::smmlsr(); 296 } 297 } 298 0x18: decode RN { 299 0xf: WarnUnimpl::usada8(); 300 default: WarnUnimpl::usad8(); 301 } 302 } 303 } 304 0x4: decode PUSWL { 305 // Right now we only handle cases when S (PSRUSER) is not set 306 default: ArmMacroStore::ldmstm({{ }}); 307 } 308 0x5: decode OPCODE_24 { 309 // Branch (and Link) Instructions 310 0: Branch::b({{ }}); 311 1: Branch::bl({{ }}, Link); 312 } 313 0x6: decode CPNUM { 314 0x1: decode PUNWL { 315 0x02,0x0a: decode OPCODE_15 { 316 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 317 Rn = Rn + disp8; }}, 318 {{ EA = Rn; }}); 319 1: ArmMacroFPAOp::stfd_({{ }}); 320 } 321 0x03,0x0b: decode OPCODE_15 { 322 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 323 Rn = Rn + disp8; }}, 324 {{ EA = Rn; }}); 325 1: ArmMacroFPAOp::ldfd_({{ }}); 326 } 327 0x06,0x0e: decode OPCODE_15 { 328 0: ArmMacroFPAOp::stfe_nw({{ }}); 329 } 330 0x07,0x0f: decode OPCODE_15 { 331 0: ArmMacroFPAOp::ldfe_nw({{ }}); 332 } 333 0x10,0x18: decode OPCODE_15 { 334 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 335 {{ EA = Rn + disp8; }}); 336 1: ArmMacroFPAOp::stfd_p({{ }}); 337 } 338 0x11,0x19: decode OPCODE_15 { 339 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 340 {{ EA = Rn + disp8; }}); 341 1: ArmMacroFPAOp::ldfd_p({{ }}); 342 } 343 0x12,0x1a: decode OPCODE_15 { 344 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 345 Rn = Rn + disp8; }}, 346 {{ EA = Rn + disp8; }}); 347 1: ArmMacroFPAOp::stfd_pw({{ }}); 348 } 349 0x13,0x1b: decode OPCODE_15 { 350 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 351 Rn = Rn + disp8; }}, 352 {{ EA = Rn + disp8; }}); 353 1: ArmMacroFPAOp::ldfd_pw({{ }}); 354 } 355 0x14,0x1c: decode OPCODE_15 { 356 0: ArmMacroFPAOp::stfe_pn({{ }}); 357 } 358 0x15,0x1d: decode OPCODE_15 { 359 0: ArmMacroFPAOp::ldfe_pn({{ }}); 360 } 361 0x16,0x1e: decode OPCODE_15 { 362 0: ArmMacroFPAOp::stfe_pnw({{ }}); 363 } 364 0x17,0x1f: decode OPCODE_15 { 365 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 366 } 367 } 368 0x2: decode PUNWL { 369 // could really just decode as a single instruction 370 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 371 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 372 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 373 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 374 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 375 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 376 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 377 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 378 } 379 0xb: decode LOADOP { 380 0x0: WarnUnimpl::fstmx(); 381 0x1: WarnUnimpl::fldmx(); 382 } 383 } 384 0x7: decode OPCODE_24 { 385 0: decode OPCODE_4 { 386 0: decode CPNUM { 387 format FloatOp { 388 0x1: decode OPCODE_23_20 { 389 0x0: decode OPCODE_15 { 390 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 391 1: mvf({{ Fd.sf = Fm.sf; }}); 392 } 393 0x1: decode OPCODE_15 { 394 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 395 1: mnf({{ Fd.sf = -Fm.sf; }}); 396 } 397 0x2: decode OPCODE_15 { 398 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 399 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 400 } 401 0x3: decode OPCODE_15 { 402 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 403 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 404 } 405 0x4: decode OPCODE_15 { 406 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 407 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 408 } 409 0x5: decode OPCODE_15 { 410 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 411 1: log({{ Fd.sf = log10(Fm.sf); }}); 412 } 413 0x6: decode OPCODE_15 { 414 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 415 1: lgn({{ Fd.sf = log(Fm.sf); }}); 416 } 417 0x7: decode OPCODE_15 { 418 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 419 1: exp({{ Fd.sf = exp(Fm.sf); }}); 420 } 421 0x8: decode OPCODE_15 { 422 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 423 1: sin({{ Fd.sf = sin(Fm.sf); }}); 424 } 425 0x9: decode OPCODE_15 { 426 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 427 1: cos({{ Fd.sf = cos(Fm.sf); }}); 428 } 429 0xa: decode OPCODE_15 { 430 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 431 1: tan({{ Fd.sf = tan(Fm.sf); }}); 432 } 433 0xb: decode OPCODE_15 { 434 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 435 1: asn({{ Fd.sf = asin(Fm.sf); }}); 436 } 437 0xc: decode OPCODE_15 { 438 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 439 1: acs({{ Fd.sf = acos(Fm.sf); }}); 440 } 441 0xd: decode OPCODE_15 { 442 1: atn({{ Fd.sf = atan(Fm.sf); }}); 443 } 444 0xe: decode OPCODE_15 { 445 // Unnormalised Round 446 1: FailUnimpl::urd(); 447 } 448 0xf: decode OPCODE_15 { 449 // Normalise 450 1: FailUnimpl::nrm(); 451 } 452 } // OPCODE_23_20 453 } // format FloatOp 454 } // CPNUM 455 1: decode CPNUM { // 27-24=1110,4 ==1 456 1: decode OPCODE_15_12 { 457 format FloatOp { 458 0xf: decode OPCODE_23_21 { 459 format FloatCmp { 460 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 461 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 462 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 463 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 464 } 465 } 466 default: decode OPCODE_23_20 { 467 0x0: decode OPCODE_7 { 468 0: flts({{ Fn.sf = (float) Rd.sw; }}); 469 1: fltd({{ Fn.df = (double) Rd.sw; }}); 470 } 471 0x1: decode OPCODE_7 { 472 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 473 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 474 } 475 0x2: wfs({{ Fpsr = Rd; }}); 476 0x3: rfs({{ Rd = Fpsr; }}); 477 0x4: FailUnimpl::wfc(); 478 0x5: FailUnimpl::rfc(); 479 } 480 } // format FloatOp 481 } 482 0xa: decode MISC_OPCODE { 483 0x1: decode MEDIA_OPCODE { 484 0xf: decode RN { 485 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 486 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 487 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 488 } 489 0xe: decode RN { 490 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 491 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 492 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 493 } 494 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 495 } // MISC_OPCODE (CPNUM 0xA) 496 0xf: decode RN { 497 // Barrriers, Cache Maintence, NOPS 498 7: decode OPCODE_23_21 { 499 0: decode RM { 500 0: decode OPC2 { 501 4: decode OPCODE_20 { 502 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 503 } 504 } 505 1: WarnUnimpl::cp15_cache_maint(); 506 4: WarnUnimpl::cp15_par(); 507 5: decode OPC2 { 508 0,1: WarnUnimpl::cp15_cache_maint2(); 509 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 510 6,7: WarnUnimpl::cp15_bp_maint(); 511 } 512 6: WarnUnimpl::cp15_cache_maint3(); 513 8: WarnUnimpl::cp15_va_to_pa(); 514 10: decode OPC2 { 515 1,2: WarnUnimpl::cp15_cache_maint3(); 516 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 517 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 518 } 519 11: WarnUnimpl::cp15_cache_maint4(); 520 13: decode OPC2 { 521 1: decode OPCODE_20 { 522 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 523 } 524 } 525 14: WarnUnimpl::cp15_cache_maint5(); 526 } // RM 527 } // OPCODE_23_21 CR 528 529 // Thread ID and context ID registers 530 // Thread ID register needs cheaper access than miscreg 531 13: WarnUnimpl::mcr_mrc_cp15_c7(); 532 533 // All the rest 534 default: decode OPCODE_20 { 535 0: PredOp::mcr_cp15({{ 536 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 537 }}); 538 1: PredOp::mrc_cp15({{ 539 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 540 }}); 541 } 542 } // RN 543 } // CPNUM (OP4 == 1) 544 } //OPCODE_4 545 546#if FULL_SYSTEM 547 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 548#else 549 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 550 { 551 if (IMMED_23_0) 552 xc->syscall(IMMED_23_0); 553 else 554 xc->syscall(R7); 555 } 556 }}); 557#endif // FULL_SYSTEM 558 } // OPCODE_24 559 560} 561} 562 563