arm.isa revision 6743
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40 41decode ENCODING default Unknown::unknown() { 42format DataOp { 43 0x0: decode SEVEN_AND_FOUR { 44 1: decode MISC_OPCODE { 45 0x9: decode PREPOST { 46 0: decode OPCODE { 47 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 48 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 49 0x2: WarnUnimpl::umall(); 50 0x4: umull({{ 51 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 52 Rd = (uint32_t)(resTemp & 0xffffffff); 53 Rn = (uint32_t)(resTemp >> 32); 54 }}, llbit); 55 0x5: smlal({{ 56 resTemp = ((int64_t)Rm) * ((int64_t)Rs); 57 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd); 58 Rd = (uint32_t)(resTemp & 0xffffffff); 59 Rn = (uint32_t)(resTemp >> 32); 60 }}, llbit); 61 0x6: smull({{ 62 resTemp = ((int64_t)(int32_t)Rm)* 63 ((int64_t)(int32_t)Rs); 64 Rd = (int32_t)(resTemp & 0xffffffff); 65 Rn = (int32_t)(resTemp >> 32); 66 }}, llbit); 67 0x7: umlal({{ 68 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 69 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 70 Rd = (uint32_t)(resTemp & 0xffffffff); 71 Rn = (uint32_t)(resTemp >> 32); 72 }}, llbit); 73 } 74 1: decode PUBWL { 75 0x10: WarnUnimpl::swp(); 76 0x14: WarnUnimpl::swpb(); 77 0x18: WarnUnimpl::strex(); 78 0x19: WarnUnimpl::ldrex(); 79 } 80 } 81 format AddrMode3 { 82 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, 83 load, {{ Rd = Mem.uh; }}); 84 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); 85 Rdo = bits(Mem.ud, 63, 32); }}, 86 load, {{ Rd = Mem.sb; }}); 87 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | 88 (Rdo.ud << 32); }}, 89 load, {{ Rd = Mem.sh; }}); 90 } 91 } 92 0: decode IS_MISC { 93 0: decode OPCODE { 94 0x0: and({{ Rd = resTemp = Rn & op2; }}); 95 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 96 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); 97 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); 98 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); 99 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add); 100 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub); 101 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb); 102 0x8: tst({{ resTemp = Rn & op2; }}); 103 0x9: teq({{ resTemp = Rn ^ op2; }}); 104 0xa: cmp({{ resTemp = Rn - op2; }}, sub); 105 0xb: cmn({{ resTemp = Rn + op2; }}, add); 106 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 107 0xd: mov({{ Rd = resTemp = op2; }}); 108 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 109 0xf: mvn({{ Rd = resTemp = ~op2; }}); 110 } 111 1: decode MISC_OPCODE { 112 0x0: decode OPCODE { 113 0x8: PredOp::mrs_cpsr({{ Rd = Cpsr | CondCodes; }}); 114 0x9: PredOp::msr_cpsr({{ 115 //assert(!RN<1:0>); 116 if (OPCODE_18) { 117 Cpsr = Cpsr<31:20> | mbits(Rm, 19, 16) | Cpsr<15:0>; 118 } 119 if (OPCODE_19) { 120 CondCodes = mbits(Rm, 31,27); 121 } 122 }}); 123 0xa: PredOp::mrs_spsr({{ Rd = 0; // should be SPSR}}); 124 0xb: WarnUnimpl::msr_spsr(); 125 } 126 0x1: decode OPCODE { 127 0x9: BranchExchange::bx({{ }}); 128 0xb: PredOp::clz({{ 129 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 130 }}); 131 } 132 0x2: decode OPCODE { 133 0x9: WarnUnimpl::bxj(); 134 } 135 0x3: decode OPCODE { 136 0x9: BranchExchange::blx({{ }}, Link); 137 } 138 0x5: decode OPCODE { 139 0x8: WarnUnimpl::qadd(); 140 0x9: WarnUnimpl::qsub(); 141 0xa: WarnUnimpl::qdadd(); 142 0xb: WarnUnimpl::qdsub(); 143 } 144 0x8: decode OPCODE { 145 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 146 0x9: WarnUnimpl::smlalbb(); 147 0xa: WarnUnimpl::smlawb(); 148 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none); 149 } 150 0xa: decode OPCODE { 151 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 152 0x9: smulwb({{ 153 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16); 154 }}, none); 155 0xa: WarnUnimpl::smlaltb(); 156 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none); 157 } 158 0xc: decode OPCODE { 159 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 160 0x9: WarnUnimpl::smlawt(); 161 0xa: WarnUnimpl::smlalbt(); 162 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none); 163 } 164 0xe: decode OPCODE { 165 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 166 0x9: smulwt({{ 167 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16); 168 }}, none); 169 0xa: WarnUnimpl::smlaltt(); 170 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none); 171 } 172 } 173 } 174 } 175 0x1: decode IS_MISC { 176 0: decode OPCODE { 177 format DataImmOp { 178 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 179 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 180 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); 181 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); 182 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); 183 0x5: adci({{ 184 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>; 185 }}, add); 186 0x6: sbci({{ 187 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>; 188 }}, sub); 189 0x7: rsci({{ 190 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>; 191 }}, rsb); 192 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 193 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 194 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); 195 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); 196 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 197 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 198 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 199 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 200 } 201 } 202 1: decode OPCODE { 203 // The following two instructions aren't supposed to be defined 204 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 205 0x9: DataImmOp::msr_ia_cpsr ({{ 206 //assert(!RN<1:0>); 207 if (OPCODE_18) { 208 Cpsr = Cpsr<31:20> | rotated_imm | Cpsr<15:0>; 209 } 210 if (OPCODE_19) { 211 CondCodes = rotated_imm; 212 } 213 }}); 214 215 0xa: WarnUnimpl::mrs_i_cpsr(); 216 0xb: WarnUnimpl::mrs_i_spsr(); 217 } 218 } 219 0x2: AddrMode2::addrMode2(Disp, disp); 220 0x3: decode OPCODE_4 { 221 0: AddrMode2::addrMode2(Shift, Rm_Imm); 222 1: decode MEDIA_OPCODE { 223 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 224 0x8: decode MISC_OPCODE { 225 0x1, 0x9: WarnUnimpl::pkhbt(); 226 0x7: WarnUnimpl::sxtab16(); 227 0xb: WarnUnimpl::sel(); 228 0x5, 0xd: WarnUnimpl::pkhtb(); 229 0x3: WarnUnimpl::sign_zero_extend_add(); 230 } 231 0xa, 0xb: decode SHIFT { 232 0x0, 0x2: WarnUnimpl::ssat(); 233 0x1: WarnUnimpl::ssat16(); 234 } 235 0xe, 0xf: decode SHIFT { 236 0x0, 0x2: WarnUnimpl::usat(); 237 0x1: WarnUnimpl::usat16(); 238 } 239 0x10: decode RN { 240 0xf: decode MISC_OPCODE { 241 0x1: WarnUnimpl::smuad(); 242 0x3: WarnUnimpl::smuadx(); 243 0x5: WarnUnimpl::smusd(); 244 0x7: WarnUnimpl::smusdx(); 245 } 246 default: decode MISC_OPCODE { 247 0x1: WarnUnimpl::smlad(); 248 0x3: WarnUnimpl::smladx(); 249 0x5: WarnUnimpl::smlsd(); 250 0x7: WarnUnimpl::smlsdx(); 251 } 252 } 253 0x14: decode MISC_OPCODE { 254 0x1: WarnUnimpl::smlald(); 255 0x3: WarnUnimpl::smlaldx(); 256 0x5: WarnUnimpl::smlsld(); 257 0x7: WarnUnimpl::smlsldx(); 258 } 259 0x15: decode RN { 260 0xf: decode MISC_OPCODE { 261 0x1: WarnUnimpl::smmul(); 262 0x3: WarnUnimpl::smmulr(); 263 } 264 default: decode MISC_OPCODE { 265 0x1: WarnUnimpl::smmla(); 266 0x3: WarnUnimpl::smmlar(); 267 0xd: WarnUnimpl::smmls(); 268 0xf: WarnUnimpl::smmlsr(); 269 } 270 } 271 0x18: decode RN { 272 0xf: WarnUnimpl::usada8(); 273 default: WarnUnimpl::usad8(); 274 } 275 } 276 } 277 0x4: decode PUSWL { 278 // Right now we only handle cases when S (PSRUSER) is not set 279 default: ArmMacroStore::ldmstm({{ }}); 280 } 281 0x5: decode OPCODE_24 { 282 // Branch (and Link) Instructions 283 0: Branch::b({{ }}); 284 1: Branch::bl({{ }}, Link); 285 } 286 0x6: decode CPNUM { 287 0x1: decode PUNWL { 288 0x02,0x0a: decode OPCODE_15 { 289 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 290 Rn = Rn + disp8; }}, 291 {{ EA = Rn; }}); 292 1: ArmMacroFPAOp::stfd_({{ }}); 293 } 294 0x03,0x0b: decode OPCODE_15 { 295 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 296 Rn = Rn + disp8; }}, 297 {{ EA = Rn; }}); 298 1: ArmMacroFPAOp::ldfd_({{ }}); 299 } 300 0x06,0x0e: decode OPCODE_15 { 301 0: ArmMacroFPAOp::stfe_nw({{ }}); 302 } 303 0x07,0x0f: decode OPCODE_15 { 304 0: ArmMacroFPAOp::ldfe_nw({{ }}); 305 } 306 0x10,0x18: decode OPCODE_15 { 307 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 308 {{ EA = Rn + disp8; }}); 309 1: ArmMacroFPAOp::stfd_p({{ }}); 310 } 311 0x11,0x19: decode OPCODE_15 { 312 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 313 {{ EA = Rn + disp8; }}); 314 1: ArmMacroFPAOp::ldfd_p({{ }}); 315 } 316 0x12,0x1a: decode OPCODE_15 { 317 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 318 Rn = Rn + disp8; }}, 319 {{ EA = Rn + disp8; }}); 320 1: ArmMacroFPAOp::stfd_pw({{ }}); 321 } 322 0x13,0x1b: decode OPCODE_15 { 323 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 324 Rn = Rn + disp8; }}, 325 {{ EA = Rn + disp8; }}); 326 1: ArmMacroFPAOp::ldfd_pw({{ }}); 327 } 328 0x14,0x1c: decode OPCODE_15 { 329 0: ArmMacroFPAOp::stfe_pn({{ }}); 330 } 331 0x15,0x1d: decode OPCODE_15 { 332 0: ArmMacroFPAOp::ldfe_pn({{ }}); 333 } 334 0x16,0x1e: decode OPCODE_15 { 335 0: ArmMacroFPAOp::stfe_pnw({{ }}); 336 } 337 0x17,0x1f: decode OPCODE_15 { 338 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 339 } 340 } 341 0x2: decode PUNWL { 342 // could really just decode as a single instruction 343 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 344 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 345 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 346 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 347 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 348 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 349 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 350 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 351 } 352 0xb: decode LOADOP { 353 0x0: WarnUnimpl::fstmx(); 354 0x1: WarnUnimpl::fldmx(); 355 } 356 } 357 0x7: decode OPCODE_24 { 358 0: decode OPCODE_4 { 359 0: decode CPNUM { 360 format FloatOp { 361 0x1: decode OPCODE_23_20 { 362 0x0: decode OPCODE_15 { 363 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 364 1: mvf({{ Fd.sf = Fm.sf; }}); 365 } 366 0x1: decode OPCODE_15 { 367 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 368 1: mnf({{ Fd.sf = -Fm.sf; }}); 369 } 370 0x2: decode OPCODE_15 { 371 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 372 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 373 } 374 0x3: decode OPCODE_15 { 375 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 376 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 377 } 378 0x4: decode OPCODE_15 { 379 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 380 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 381 } 382 0x5: decode OPCODE_15 { 383 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 384 1: log({{ Fd.sf = log10(Fm.sf); }}); 385 } 386 0x6: decode OPCODE_15 { 387 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 388 1: lgn({{ Fd.sf = log(Fm.sf); }}); 389 } 390 0x7: decode OPCODE_15 { 391 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 392 1: exp({{ Fd.sf = exp(Fm.sf); }}); 393 } 394 0x8: decode OPCODE_15 { 395 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 396 1: sin({{ Fd.sf = sin(Fm.sf); }}); 397 } 398 0x9: decode OPCODE_15 { 399 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 400 1: cos({{ Fd.sf = cos(Fm.sf); }}); 401 } 402 0xa: decode OPCODE_15 { 403 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 404 1: tan({{ Fd.sf = tan(Fm.sf); }}); 405 } 406 0xb: decode OPCODE_15 { 407 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 408 1: asn({{ Fd.sf = asin(Fm.sf); }}); 409 } 410 0xc: decode OPCODE_15 { 411 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 412 1: acs({{ Fd.sf = acos(Fm.sf); }}); 413 } 414 0xd: decode OPCODE_15 { 415 1: atn({{ Fd.sf = atan(Fm.sf); }}); 416 } 417 0xe: decode OPCODE_15 { 418 // Unnormalised Round 419 1: FailUnimpl::urd(); 420 } 421 0xf: decode OPCODE_15 { 422 // Normalise 423 1: FailUnimpl::nrm(); 424 } 425 } // OPCODE_23_20 426 } // format FloatOp 427 } // CPNUM 428 1: decode CPNUM { // 27-24=1110,4 ==1 429 1: decode OPCODE_15_12 { 430 format FloatOp { 431 0xf: decode OPCODE_23_21 { 432 format FloatCmp { 433 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 434 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 435 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 436 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 437 } 438 } 439 default: decode OPCODE_23_20 { 440 0x0: decode OPCODE_7 { 441 0: flts({{ Fn.sf = (float) Rd.sw; }}); 442 1: fltd({{ Fn.df = (double) Rd.sw; }}); 443 } 444 0x1: decode OPCODE_7 { 445 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 446 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 447 } 448 0x2: wfs({{ Fpsr = Rd; }}); 449 0x3: rfs({{ Rd = Fpsr; }}); 450 0x4: FailUnimpl::wfc(); 451 0x5: FailUnimpl::rfc(); 452 } 453 } // format FloatOp 454 } 455 0xa: decode MISC_OPCODE { 456 0x1: decode MEDIA_OPCODE { 457 0xf: decode RN { 458 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 459 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 460 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 461 } 462 0xe: decode RN { 463 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 464 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 465 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 466 } 467 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 468 } // MISC_OPCODE (CPNUM 0xA) 469 0xf: decode OPCODE_20 { 470 0: WarnUnimpl::mcr_cp15(); 471 1: WarnUnimpl::mrc_cp15(); 472 } 473 } // CPNUM (OP4 == 1) 474 } //OPCODE_4 475 476#if FULL_SYSTEM 477 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 478#else 479 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 480 { 481 if (IMMED_23_0) 482 xc->syscall(IMMED_23_0); 483 else 484 xc->syscall(R7); 485 } 486 }}); 487#endif // FULL_SYSTEM 488 } // OPCODE_24 489 490} 491} 492 493