arm.isa revision 6412
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40 41decode ENCODING default Unknown::unknown() { 42format DataOp { 43 0x0: decode SEVEN_AND_FOUR { 44 1: decode MISC_OPCODE { 45 0x9: decode PREPOST { 46 0: decode OPCODE { 47 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 48 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 49 0x2: WarnUnimpl::umall(); 50 0x4: umull({{ 51 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 52 Rd = (uint32_t)(resTemp & 0xffffffff); 53 Rn = (uint32_t)(resTemp >> 32); 54 }}); 55 0x5: WarnUnimpl::smlal(); 56 0x6: smull({{ 57 resTemp = ((int64_t)(int32_t)Rm)* 58 ((int64_t)(int32_t)Rs); 59 Rd = (int32_t)(resTemp & 0xffffffff); 60 Rn = (int32_t)(resTemp >> 32); 61 }}); 62 0x7: umlal({{ 63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 64 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 65 Rd = (uint32_t)(resTemp & 0xffffffff); 66 Rn = (uint32_t)(resTemp >> 32); 67 }}); 68 } 69 1: decode PUBWL { 70 0x10: WarnUnimpl::swp(); 71 0x14: WarnUnimpl::swpb(); 72 0x18: WarnUnimpl::strex(); 73 0x19: WarnUnimpl::ldrex(); 74 } 75 } 76 format AddrMode3 { 77 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, 78 load, {{ Rd = Mem.uh; }}); 79 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); 80 Rdo = bits(Mem.ud, 63, 32); }}, 81 load, {{ Rd = Mem.sb; }}); 82 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | 83 (Rdo.ud << 32); }}, 84 load, {{ Rd = Mem.sh; }}); 85 } 86 } 87 0: decode IS_MISC { 88 0: decode OPCODE { 89 0x0: and({{ Rd = resTemp = Rn & op2; }}); 90 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 91 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); 92 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); 93 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); 94 0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }}, add); 95 0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }}, sub); 96 0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }}, rsb); 97 0x8: tst({{ resTemp = Rn & op2; }}); 98 0x9: teq({{ resTemp = Rn ^ op2; }}); 99 0xa: cmp({{ resTemp = Rn - op2; }}, sub); 100 0xb: cmn({{ resTemp = Rn + op2; }}, add); 101 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 102 0xd: mov({{ Rd = resTemp = op2; }}); 103 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 104 0xf: mvn({{ Rd = resTemp = ~op2; }}); 105 } 106 1: decode MISC_OPCODE { 107 0x0: decode OPCODE { 108 0x8: WarnUnimpl::mrs_cpsr(); 109 0x9: WarnUnimpl::msr_cpsr(); 110 0xa: WarnUnimpl::mrs_spsr(); 111 0xb: WarnUnimpl::msr_spsr(); 112 } 113 0x1: decode OPCODE { 114 0x9: BranchExchange::bx({{ }}); 115 0xb: PredOp::clz({{ 116 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 117 }}); 118 } 119 0x2: decode OPCODE { 120 0x9: WarnUnimpl::bxj(); 121 } 122 0x3: decode OPCODE { 123 0x9: BranchExchange::blx({{ }}, Link); 124 } 125 0x5: decode OPCODE { 126 0x8: WarnUnimpl::qadd(); 127 0x9: WarnUnimpl::qsub(); 128 0xa: WarnUnimpl::qdadd(); 129 0xb: WarnUnimpl::qdsub(); 130 } 131 0x8: decode OPCODE { 132 0x8: WarnUnimpl::smlabb(); 133 0x9: WarnUnimpl::smlalbb(); 134 0xa: WarnUnimpl::smlawb(); 135 0xb: WarnUnimpl::smulbb(); 136 } 137 0xa: decode OPCODE { 138 0x8: WarnUnimpl::smlatb(); 139 0x9: WarnUnimpl::smulwb(); 140 0xa: WarnUnimpl::smlaltb(); 141 0xb: WarnUnimpl::smultb(); 142 } 143 0xc: decode OPCODE { 144 0x8: WarnUnimpl::smlabt(); 145 0x9: WarnUnimpl::smlawt(); 146 0xa: WarnUnimpl::smlalbt(); 147 0xb: WarnUnimpl::smulbt(); 148 } 149 0xe: decode OPCODE { 150 0x8: WarnUnimpl::smlatt(); 151 0x9: WarnUnimpl::smulwt(); 152 0xa: WarnUnimpl::smlaltt(); 153 0xb: WarnUnimpl::smultt(); 154 } 155 } 156 } 157 } 158 0x1: decode IS_MISC { 159 0: decode OPCODE { 160 format DataImmOp { 161 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 162 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 163 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); 164 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); 165 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); 166 0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }}, add); 167 0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }}, sub); 168 0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}}, rsb); 169 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 170 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 171 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); 172 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); 173 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 174 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 175 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 176 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 177 } 178 } 179 1: decode OPCODE { 180 // The following two instructions aren't supposed to be defined 181 0x8: WarnUnimpl::undefined_instruction(); 182 0x9: WarnUnimpl::undefined_instruction(); 183 184 0xa: WarnUnimpl::mrs_i_cpsr(); 185 0xb: WarnUnimpl::mrs_i_spsr(); 186 } 187 } 188 0x2: AddrMode2::addrMode2(Disp, disp); 189 0x3: decode OPCODE_4 { 190 0: AddrMode2::addrMode2(Shift, Rm_Imm); 191 1: decode MEDIA_OPCODE { 192 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 193 0x8: decode MISC_OPCODE { 194 0x1, 0x9: WarnUnimpl::pkhbt(); 195 0x7: WarnUnimpl::sxtab16(); 196 0xb: WarnUnimpl::sel(); 197 0x5, 0xd: WarnUnimpl::pkhtb(); 198 0x3: WarnUnimpl::sign_zero_extend_add(); 199 } 200 0xa, 0xb: decode SHIFT { 201 0x0, 0x2: WarnUnimpl::ssat(); 202 0x1: WarnUnimpl::ssat16(); 203 } 204 0xe, 0xf: decode SHIFT { 205 0x0, 0x2: WarnUnimpl::usat(); 206 0x1: WarnUnimpl::usat16(); 207 } 208 0x10: decode RN { 209 0xf: decode MISC_OPCODE { 210 0x1: WarnUnimpl::smuad(); 211 0x3: WarnUnimpl::smuadx(); 212 0x5: WarnUnimpl::smusd(); 213 0x7: WarnUnimpl::smusdx(); 214 } 215 default: decode MISC_OPCODE { 216 0x1: WarnUnimpl::smlad(); 217 0x3: WarnUnimpl::smladx(); 218 0x5: WarnUnimpl::smlsd(); 219 0x7: WarnUnimpl::smlsdx(); 220 } 221 } 222 0x14: decode MISC_OPCODE { 223 0x1: WarnUnimpl::smlald(); 224 0x3: WarnUnimpl::smlaldx(); 225 0x5: WarnUnimpl::smlsld(); 226 0x7: WarnUnimpl::smlsldx(); 227 } 228 0x15: decode RN { 229 0xf: decode MISC_OPCODE { 230 0x1: WarnUnimpl::smmul(); 231 0x3: WarnUnimpl::smmulr(); 232 } 233 default: decode MISC_OPCODE { 234 0x1: WarnUnimpl::smmla(); 235 0x3: WarnUnimpl::smmlar(); 236 0xd: WarnUnimpl::smmls(); 237 0xf: WarnUnimpl::smmlsr(); 238 } 239 } 240 0x18: decode RN { 241 0xf: WarnUnimpl::usada8(); 242 default: WarnUnimpl::usad8(); 243 } 244 } 245 } 246 0x4: decode PUSWL { 247 // Right now we only handle cases when S (PSRUSER) is not set 248 default: ArmMacroStore::ldmstm({{ }}); 249 } 250 0x5: decode OPCODE_24 { 251 // Branch (and Link) Instructions 252 0: Branch::b({{ }}); 253 1: Branch::bl({{ }}, Link); 254 } 255 0x6: decode CPNUM { 256 0x1: decode PUNWL { 257 0x02,0x0a: decode OPCODE_15 { 258 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 259 Rn = Rn + disp8; }}, 260 {{ EA = Rn; }}); 261 1: ArmMacroFPAOp::stfd_({{ }}); 262 } 263 0x03,0x0b: decode OPCODE_15 { 264 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 265 Rn = Rn + disp8; }}, 266 {{ EA = Rn; }}); 267 1: ArmMacroFPAOp::ldfd_({{ }}); 268 } 269 0x06,0x0e: decode OPCODE_15 { 270 0: ArmMacroFPAOp::stfe_nw({{ }}); 271 } 272 0x07,0x0f: decode OPCODE_15 { 273 0: ArmMacroFPAOp::ldfe_nw({{ }}); 274 } 275 0x10,0x18: decode OPCODE_15 { 276 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 277 {{ EA = Rn + disp8; }}); 278 1: ArmMacroFPAOp::stfd_p({{ }}); 279 } 280 0x11,0x19: decode OPCODE_15 { 281 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 282 {{ EA = Rn + disp8; }}); 283 1: ArmMacroFPAOp::ldfd_p({{ }}); 284 } 285 0x12,0x1a: decode OPCODE_15 { 286 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 287 Rn = Rn + disp8; }}, 288 {{ EA = Rn + disp8; }}); 289 1: ArmMacroFPAOp::stfd_pw({{ }}); 290 } 291 0x13,0x1b: decode OPCODE_15 { 292 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 293 Rn = Rn + disp8; }}, 294 {{ EA = Rn + disp8; }}); 295 1: ArmMacroFPAOp::ldfd_pw({{ }}); 296 } 297 0x14,0x1c: decode OPCODE_15 { 298 0: ArmMacroFPAOp::stfe_pn({{ }}); 299 } 300 0x15,0x1d: decode OPCODE_15 { 301 0: ArmMacroFPAOp::ldfe_pn({{ }}); 302 } 303 0x16,0x1e: decode OPCODE_15 { 304 0: ArmMacroFPAOp::stfe_pnw({{ }}); 305 } 306 0x17,0x1f: decode OPCODE_15 { 307 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 308 } 309 } 310 0x2: decode PUNWL { 311 // could really just decode as a single instruction 312 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 313 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 314 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 315 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 316 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 317 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 318 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 319 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 320 } 321 0xb: decode LOADOP { 322 0x0: WarnUnimpl::fstmx(); 323 0x1: WarnUnimpl::fldmx(); 324 } 325 } 326 0x7: decode OPCODE_24 { 327 0: decode CPNUM { 328 // Coprocessor Instructions 329 0x1: decode OPCODE_4 { 330 format FloatOp { 331 // Basic FPA Instructions 332 0: decode OPCODE_23_20 { 333 0x0: decode OPCODE_15 { 334 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 335 1: mvf({{ Fd.sf = Fm.sf; }}); 336 } 337 0x1: decode OPCODE_15 { 338 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 339 1: mnf({{ Fd.sf = -Fm.sf; }}); 340 } 341 0x2: decode OPCODE_15 { 342 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 343 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 344 } 345 0x3: decode OPCODE_15 { 346 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 347 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 348 } 349 0x4: decode OPCODE_15 { 350 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 351 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 352 } 353 0x5: decode OPCODE_15 { 354 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 355 1: log({{ Fd.sf = log10(Fm.sf); }}); 356 } 357 0x6: decode OPCODE_15 { 358 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 359 1: lgn({{ Fd.sf = log(Fm.sf); }}); 360 } 361 0x7: decode OPCODE_15 { 362 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 363 1: exp({{ Fd.sf = exp(Fm.sf); }}); 364 } 365 0x8: decode OPCODE_15 { 366 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 367 1: sin({{ Fd.sf = sin(Fm.sf); }}); 368 } 369 0x9: decode OPCODE_15 { 370 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 371 1: cos({{ Fd.sf = cos(Fm.sf); }}); 372 } 373 0xa: decode OPCODE_15 { 374 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 375 1: tan({{ Fd.sf = tan(Fm.sf); }}); 376 } 377 0xb: decode OPCODE_15 { 378 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 379 1: asn({{ Fd.sf = asin(Fm.sf); }}); 380 } 381 0xc: decode OPCODE_15 { 382 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 383 1: acs({{ Fd.sf = acos(Fm.sf); }}); 384 } 385 0xd: decode OPCODE_15 { 386 1: atn({{ Fd.sf = atan(Fm.sf); }}); 387 } 388 0xe: decode OPCODE_15 { 389 // Unnormalised Round 390 1: FailUnimpl::urd(); 391 } 392 0xf: decode OPCODE_15 { 393 // Normalise 394 1: FailUnimpl::nrm(); 395 } 396 } 397 1: decode OPCODE_15_12 { 398 0xf: decode OPCODE_23_21 { 399 format FloatCmp { 400 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 401 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 402 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 403 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 404 } 405 } 406 default: decode OPCODE_23_20 { 407 0x0: decode OPCODE_7 { 408 0: flts({{ Fn.sf = (float) Rd.sw; }}); 409 1: fltd({{ Fn.df = (double) Rd.sw; }}); 410 } 411 0x1: decode OPCODE_7 { 412 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 413 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 414 } 415 0x2: wfs({{ Fpsr = Rd; }}); 416 0x3: rfs({{ Rd = Fpsr; }}); 417 0x4: FailUnimpl::wfc(); 418 0x5: FailUnimpl::rfc(); 419 } 420 } 421 } 422 } 423 0xa: decode MISC_OPCODE { 424 0x1: decode MEDIA_OPCODE { 425 0xf: decode RN { 426 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 427 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 428 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 429 } 430 0xe: decode RN { 431 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 432 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 433 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 434 } 435 } 436 } 437 } 438 format PredOp { 439 // ARM System Call (SoftWare Interrupt) 440 1: swi({{ if (testPredicate(Cpsr, condCode)) 441 { 442 if (IMMED_23_0) 443 xc->syscall(IMMED_23_0); 444 else 445 xc->syscall(R7); 446 } 447 }}); 448 } 449 } 450} 451} 452 453