arm.isa revision 6310
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40 41decode ENCODING default Unknown::unknown() { 42format DataOp { 43 0x0: decode SEVEN_AND_FOUR { 44 1: decode MISC_OPCODE { 45 0x9: decode PREPOST { 46 0: decode OPCODE { 47 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 48 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 49 0x2: WarnUnimpl::umall(); 50 0x4: umull({{ 51 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 52 Rd = (uint32_t)(resTemp & 0xffffffff); 53 Rn = (uint32_t)(resTemp >> 32); 54 }}); 55 0x5: WarnUnimpl::smlal(); 56 0x6: smull({{ 57 resTemp = ((int64_t)(int32_t)Rm)* 58 ((int64_t)(int32_t)Rs); 59 Rd = (int32_t)(resTemp & 0xffffffff); 60 Rn = (int32_t)(resTemp >> 32); 61 }}); 62 0x7: umlal({{ 63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 64 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 65 Rd = (uint32_t)(resTemp & 0xffffffff); 66 Rn = (uint32_t)(resTemp >> 32); 67 }}); 68 } 69 1: decode PUBWL { 70 0x10: WarnUnimpl::swp(); 71 0x14: WarnUnimpl::swpb(); 72 0x18: WarnUnimpl::strex(); 73 0x19: WarnUnimpl::ldrex(); 74 } 75 } 76 format AddrMode3 { 77 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, 78 load, {{ Rd = Mem.uh; }}); 79 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); 80 Rdo = bits(Mem.ud, 63, 32); }}, 81 load, {{ Rd = Mem.sb; }}); 82 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | 83 (Rdo.ud << 32); }}, 84 load, {{ Rd = Mem.sh; }}); 85 } 86 } 87 0: decode IS_MISC { 88 0: decode OPCODE { 89 0x0: and({{ Rd = resTemp = Rn & op2; }}); 90 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 91 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); 92 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); 93 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); 94 0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }}, add); 95 0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }}, sub); 96 0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }}, rsb); 97 0x8: tst({{ resTemp = Rn & op2; }}); 98 0x9: teq({{ resTemp = Rn ^ op2; }}); 99 0xa: cmp({{ resTemp = Rn - op2; }}, sub); 100 0xb: cmn({{ resTemp = Rn + op2; }}, add); 101 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 102 0xd: mov({{ Rd = resTemp = op2; }}); 103 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 104 0xf: mvn({{ Rd = resTemp = ~op2; }}); 105 } 106 1: decode MISC_OPCODE { 107 0x0: decode OPCODE { 108 0x8: WarnUnimpl::mrs_cpsr(); 109 0x9: WarnUnimpl::msr_cpsr(); 110 0xa: WarnUnimpl::mrs_spsr(); 111 0xb: WarnUnimpl::msr_spsr(); 112 } 113 0x1: decode OPCODE { 114 0x9: BranchExchange::bx({{ }}); 115 0xb: PredOp::clz({{ 116 unsigned lsb = findLsbSet(Rm); 117 Rd = (lsb > 31) ? 32 : lsb; 118 }}); 119 } 120 0x2: decode OPCODE { 121 0x9: WarnUnimpl::bxj(); 122 } 123 0x3: decode OPCODE { 124 0x9: BranchExchange::blx({{ }}, Link); 125 } 126 0x5: decode OPCODE { 127 0x8: WarnUnimpl::qadd(); 128 0x9: WarnUnimpl::qsub(); 129 0xa: WarnUnimpl::qdadd(); 130 0xb: WarnUnimpl::qdsub(); 131 } 132 0x8: decode OPCODE { 133 0x8: WarnUnimpl::smlabb(); 134 0x9: WarnUnimpl::smlalbb(); 135 0xa: WarnUnimpl::smlawb(); 136 0xb: WarnUnimpl::smulbb(); 137 } 138 0xa: decode OPCODE { 139 0x8: WarnUnimpl::smlatb(); 140 0x9: WarnUnimpl::smulwb(); 141 0xa: WarnUnimpl::smlaltb(); 142 0xb: WarnUnimpl::smultb(); 143 } 144 0xc: decode OPCODE { 145 0x8: WarnUnimpl::smlabt(); 146 0x9: WarnUnimpl::smlawt(); 147 0xa: WarnUnimpl::smlalbt(); 148 0xb: WarnUnimpl::smulbt(); 149 } 150 0xe: decode OPCODE { 151 0x8: WarnUnimpl::smlatt(); 152 0x9: WarnUnimpl::smulwt(); 153 0xa: WarnUnimpl::smlaltt(); 154 0xb: WarnUnimpl::smultt(); 155 } 156 } 157 } 158 } 159 0x1: decode IS_MISC { 160 0: decode OPCODE { 161 format DataImmOp { 162 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 163 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 164 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); 165 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); 166 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); 167 0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }}, add); 168 0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }}, sub); 169 0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}}, rsb); 170 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 171 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 172 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); 173 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); 174 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 175 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 176 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 177 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 178 } 179 } 180 1: decode OPCODE { 181 // The following two instructions aren't supposed to be defined 182 0x8: WarnUnimpl::undefined_instruction(); 183 0x9: WarnUnimpl::undefined_instruction(); 184 185 0xa: WarnUnimpl::mrs_i_cpsr(); 186 0xb: WarnUnimpl::mrs_i_spsr(); 187 } 188 } 189 0x2: AddrMode2::addrMode2(Disp, disp); 190 0x3: decode OPCODE_4 { 191 0: AddrMode2::addrMode2(Shift, Rm_Imm); 192 1: decode MEDIA_OPCODE { 193 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 194 0x8: decode MISC_OPCODE { 195 0x1, 0x9: WarnUnimpl::pkhbt(); 196 0x7: WarnUnimpl::sxtab16(); 197 0xb: WarnUnimpl::sel(); 198 0x5, 0xd: WarnUnimpl::pkhtb(); 199 0x3: WarnUnimpl::sign_zero_extend_add(); 200 } 201 0xa, 0xb: decode SHIFT { 202 0x0, 0x2: WarnUnimpl::ssat(); 203 0x1: WarnUnimpl::ssat16(); 204 } 205 0xe, 0xf: decode SHIFT { 206 0x0, 0x2: WarnUnimpl::usat(); 207 0x1: WarnUnimpl::usat16(); 208 } 209 0x10: decode RN { 210 0xf: decode MISC_OPCODE { 211 0x1: WarnUnimpl::smuad(); 212 0x3: WarnUnimpl::smuadx(); 213 0x5: WarnUnimpl::smusd(); 214 0x7: WarnUnimpl::smusdx(); 215 } 216 default: decode MISC_OPCODE { 217 0x1: WarnUnimpl::smlad(); 218 0x3: WarnUnimpl::smladx(); 219 0x5: WarnUnimpl::smlsd(); 220 0x7: WarnUnimpl::smlsdx(); 221 } 222 } 223 0x14: decode MISC_OPCODE { 224 0x1: WarnUnimpl::smlald(); 225 0x3: WarnUnimpl::smlaldx(); 226 0x5: WarnUnimpl::smlsld(); 227 0x7: WarnUnimpl::smlsldx(); 228 } 229 0x15: decode RN { 230 0xf: decode MISC_OPCODE { 231 0x1: WarnUnimpl::smmul(); 232 0x3: WarnUnimpl::smmulr(); 233 } 234 default: decode MISC_OPCODE { 235 0x1: WarnUnimpl::smmla(); 236 0x3: WarnUnimpl::smmlar(); 237 0xd: WarnUnimpl::smmls(); 238 0xf: WarnUnimpl::smmlsr(); 239 } 240 } 241 0x18: decode RN { 242 0xf: WarnUnimpl::usada8(); 243 default: WarnUnimpl::usad8(); 244 } 245 } 246 } 247 0x4: decode PUSWL { 248 // Right now we only handle cases when S (PSRUSER) is not set 249 default: ArmMacroStore::ldmstm({{ }}); 250 } 251 0x5: decode OPCODE_24 { 252 // Branch (and Link) Instructions 253 0: Branch::b({{ }}); 254 1: Branch::bl({{ }}, Link); 255 } 256 0x6: decode CPNUM { 257 0x1: decode PUNWL { 258 0x02,0x0a: decode OPCODE_15 { 259 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 260 Rn = Rn + disp8; }}, 261 {{ EA = Rn; }}); 262 1: ArmMacroFPAOp::stfd_({{ }}); 263 } 264 0x03,0x0b: decode OPCODE_15 { 265 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 266 Rn = Rn + disp8; }}, 267 {{ EA = Rn; }}); 268 1: ArmMacroFPAOp::ldfd_({{ }}); 269 } 270 0x06,0x0e: decode OPCODE_15 { 271 0: ArmMacroFPAOp::stfe_nw({{ }}); 272 } 273 0x07,0x0f: decode OPCODE_15 { 274 0: ArmMacroFPAOp::ldfe_nw({{ }}); 275 } 276 0x10,0x18: decode OPCODE_15 { 277 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 278 {{ EA = Rn + disp8; }}); 279 1: ArmMacroFPAOp::stfd_p({{ }}); 280 } 281 0x11,0x19: decode OPCODE_15 { 282 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 283 {{ EA = Rn + disp8; }}); 284 1: ArmMacroFPAOp::ldfd_p({{ }}); 285 } 286 0x12,0x1a: decode OPCODE_15 { 287 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 288 Rn = Rn + disp8; }}, 289 {{ EA = Rn + disp8; }}); 290 1: ArmMacroFPAOp::stfd_pw({{ }}); 291 } 292 0x13,0x1b: decode OPCODE_15 { 293 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 294 Rn = Rn + disp8; }}, 295 {{ EA = Rn + disp8; }}); 296 1: ArmMacroFPAOp::ldfd_pw({{ }}); 297 } 298 0x14,0x1c: decode OPCODE_15 { 299 0: ArmMacroFPAOp::stfe_pn({{ }}); 300 } 301 0x15,0x1d: decode OPCODE_15 { 302 0: ArmMacroFPAOp::ldfe_pn({{ }}); 303 } 304 0x16,0x1e: decode OPCODE_15 { 305 0: ArmMacroFPAOp::stfe_pnw({{ }}); 306 } 307 0x17,0x1f: decode OPCODE_15 { 308 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 309 } 310 } 311 0x2: decode PUNWL { 312 // could really just decode as a single instruction 313 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 314 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 315 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 316 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 317 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 318 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 319 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 320 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 321 } 322 } 323 0x7: decode OPCODE_24 { 324 0: decode CPNUM { 325 // Coprocessor Instructions 326 0x1: decode OPCODE_4 { 327 format FloatOp { 328 // Basic FPA Instructions 329 0: decode OPCODE_23_20 { 330 0x0: decode OPCODE_15 { 331 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 332 1: mvf({{ Fd.sf = Fm.sf; }}); 333 } 334 0x1: decode OPCODE_15 { 335 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 336 1: mnf({{ Fd.sf = -Fm.sf; }}); 337 } 338 0x2: decode OPCODE_15 { 339 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 340 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 341 } 342 0x3: decode OPCODE_15 { 343 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 344 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 345 } 346 0x4: decode OPCODE_15 { 347 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 348 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 349 } 350 0x5: decode OPCODE_15 { 351 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 352 1: log({{ Fd.sf = log10(Fm.sf); }}); 353 } 354 0x6: decode OPCODE_15 { 355 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 356 1: lgn({{ Fd.sf = log(Fm.sf); }}); 357 } 358 0x7: decode OPCODE_15 { 359 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 360 1: exp({{ Fd.sf = exp(Fm.sf); }}); 361 } 362 0x8: decode OPCODE_15 { 363 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 364 1: sin({{ Fd.sf = sin(Fm.sf); }}); 365 } 366 0x9: decode OPCODE_15 { 367 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 368 1: cos({{ Fd.sf = cos(Fm.sf); }}); 369 } 370 0xa: decode OPCODE_15 { 371 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 372 1: tan({{ Fd.sf = tan(Fm.sf); }}); 373 } 374 0xb: decode OPCODE_15 { 375 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 376 1: asn({{ Fd.sf = asin(Fm.sf); }}); 377 } 378 0xc: decode OPCODE_15 { 379 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 380 1: acs({{ Fd.sf = acos(Fm.sf); }}); 381 } 382 0xd: decode OPCODE_15 { 383 1: atn({{ Fd.sf = atan(Fm.sf); }}); 384 } 385 0xe: decode OPCODE_15 { 386 // Unnormalised Round 387 1: FailUnimpl::urd(); 388 } 389 0xf: decode OPCODE_15 { 390 // Normalise 391 1: FailUnimpl::nrm(); 392 } 393 } 394 1: decode OPCODE_15_12 { 395 0xf: decode OPCODE_23_21 { 396 format FloatCmp { 397 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 398 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 399 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 400 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 401 } 402 } 403 default: decode OPCODE_23_20 { 404 0x0: decode OPCODE_7 { 405 0: flts({{ Fn.sf = (float) Rd.sw; }}); 406 1: fltd({{ Fn.df = (double) Rd.sw; }}); 407 } 408 0x1: decode OPCODE_7 { 409 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 410 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 411 } 412 0x2: wfs({{ Fpsr = Rd; }}); 413 0x3: rfs({{ Rd = Fpsr; }}); 414 0x4: FailUnimpl::wfc(); 415 0x5: FailUnimpl::rfc(); 416 } 417 } 418 } 419 } 420 } 421 format PredOp { 422 // ARM System Call (SoftWare Interrupt) 423 1: swi({{ if (testPredicate(Cpsr, condCode)) 424 { 425 xc->syscall(IMMED_23_0); 426 } 427 }}); 428 } 429 } 430} 431} 432 433