arm.isa revision 6273
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual ARM ISA decoder 34// -------------------------- 35// The following instructions are specified in the ARM ISA 36// Specification. Decoding closely follows the style specified 37// in the ARM ISA specification document starting with Table B.1 or 3-1 38// 39// 40decode COND_CODE default Unknown::unknown() { 41 0xf: decode COND_CODE { 42 0x0: decode OPCODE { 43 // Just a simple trick to allow us to specify our new uops here 44 0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }}, 45 'IsMicroop'); 46 0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }}, 47 'IsMicroop'); 48 0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }}, 49 {{ EA = Raddr + disp; }}, 50 inst_flags = [IsMicroop]); 51 0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }}, 52 {{ EA = Raddr + disp; }}, 53 inst_flags = [IsMicroop]); 54 0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }}, 55 'IsMicroop'); 56 0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }}, 57 'IsMicroop'); 58 } 59 0x1: decode OPCODE { 60 0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }}, 61 'IsMicroop'); 62 0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff; 63 Rlo = Fd.ud & 0xffffffff; }}, 64 'IsMicroop'); 65 0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }}, 66 {{ EA = Rn + disp; }}, 67 inst_flags = [IsMicroop]); 68 0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }}, 69 {{ EA = Rn + disp; }}, 70 inst_flags = [IsMicroop]); 71 0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }}, 72 {{ EA = Rn + disp; }}, 73 inst_flags = [IsMicroop]); 74 0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }}, 75 {{ EA = Rn + disp; }}, 76 inst_flags = [IsMicroop]); 77 } 78 default: Unknown::unknown(); // TODO: Ignore other NV space for now 79 } 80default: decode ENCODING { 81format DataOp { 82 0x0: decode SEVEN_AND_FOUR { 83 1: decode MISC_OPCODE { 84 0x9: decode PREPOST { 85 0: decode OPCODE { 86 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, 87 {{ Cpsr<29:> }}, 88 {{ Cpsr<28:> }}); 89 0x1: mla({{ Rn = resTemp = Rm * Rs; }}, 90 {{ Cpsr<29:> }}, 91 {{ Cpsr<28:> }}); 92 0x2: WarnUnimpl::umall(); 93 0x4: umull({{ 94 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 95 Rd = (uint32_t)(resTemp & 0xffffffff); 96 Rn = (uint32_t)(resTemp >> 32); 97 }}, {{ 1 }}, {{ 1 }}); 98 0x5: WarnUnimpl::smlal(); 99 0x6: smull({{ 100 resTemp = ((int64_t)(int32_t)Rm)* 101 ((int64_t)(int32_t)Rs); 102 Rd = (int32_t)(resTemp & 0xffffffff); 103 Rn = (int32_t)(resTemp >> 32); 104 }}, {{ 1 }}, {{ 1 }}); 105 0x7: umlal({{ 106 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 107 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 108 Rd = (uint32_t)(resTemp & 0xffffffff); 109 Rn = (uint32_t)(resTemp >> 32); 110 }}, {{ 1 }}, {{ 1 }}); 111 } 112 1: decode PUBWL { 113 0x10: WarnUnimpl::swp(); 114 0x14: WarnUnimpl::swpb(); 115 0x18: WarnUnimpl::strex(); 116 0x19: WarnUnimpl::ldrex(); 117 } 118 } 119 0xb: decode PUBWL { 120 format ArmStoreMemory { 121 0x0, 0x8: strh_({{ Mem.uh = Rd.uh; 122 Rn = Rn + Rm; }}, 123 {{ EA = Rn; }}); 124 0x4, 0xc: strh_il({{ Mem.uh = Rd.uh; 125 Rn = Rn + hilo; }}, 126 {{ EA = Rn; }}); 127 0x10, 0x18: strh_p({{ Mem.uh = Rd.uh; }}, 128 {{ EA = Rn + Rm; }}); 129 0x12, 0x1a: strh_pw({{ Mem.uh = Rd.uh; 130 Rn = Rn + Rm; }}, 131 {{ EA = Rn + Rm; }}); 132 0x14, 0x1c: strh_pil({{ Mem.uh = Rd.uh; }}, 133 {{ EA = Rn + hilo; }}); 134 0x16, 0x1e: strh_piwl({{ Mem.uh = Rd.uh; 135 Rn = Rn + hilo; }}, 136 {{ EA = Rn + hilo; }}); 137 } 138 format ArmLoadMemory { 139 0x1, 0x9: ldrh_l({{ Rd.uh = Mem.uh; 140 Rn = Rn + Rm; }}, 141 {{ EA = Rn; }}); 142 0x5, 0xd: ldrh_il({{ Rd.uh = Mem.uh; 143 Rn = Rn + hilo; }}, 144 {{ EA = Rn; }}); 145 0x11, 0x19: ldrh_pl({{ Rd.uh = Mem.uh; }}, 146 {{ EA = Rn + Rm; }}); 147 0x13, 0x1b: ldrh_pwl({{ Rd.uh = Mem.uh; 148 Rn = Rn + Rm; }}, 149 {{ EA = Rn + Rm; }}); 150 0x15, 0x1d: ldrh_pil({{ Rd.uh = Mem.uh; }}, 151 {{ EA = Rn + hilo; }}); 152 0x17, 0x1f: ldrh_piwl({{ Rd.uh = Mem.uh; 153 Rn = Rn + hilo; }}, 154 {{ EA = Rn + hilo; }}); 155 } 156 } 157 format ArmLoadMemory { 158 0xd: decode PUBWL { 159 0x1: ldrsb_l({{ Rd = Mem.sb; 160 Rn = Rn + Rm; }}, 161 {{ EA = Rn; }}); 162 0x5: ldrsb_il({{ Rd = Mem.sb; 163 Rn = Rn + hilo; }}, 164 {{ EA = Rn; }}); 165 0x9: ldrsb_ul({{ Rd = Mem.sb; 166 Rn = Rn - Rm; }}, 167 {{ EA = Rn; }}); 168 0xd: ldrsb_uil({{ Rd = Mem.sb; 169 Rn = Rn - hilo; }}, 170 {{ EA = Rn; }}); 171 0x11: ldrsb_pl({{ Rd = Mem.sb; }}, 172 {{ EA = Rn + Rm; }}); 173 0x13: ldrsb_pwl({{ Rd = Mem.sb; 174 Rn = Rn + Rm; }}, 175 {{ EA = Rn + Rm; }}); 176 0x15: ldrsb_pil({{ Rd = Mem.sb; }}, 177 {{ EA = Rn + hilo; }}); 178 0x17: ldrsb_piwl({{ Rd = Mem.sb; 179 Rn = Rn + hilo; }}, 180 {{ EA = Rn + hilo; }}); 181 0x19: ldrsb_pul({{ Rd = Mem.sb; }}, 182 {{ EA = Rn - Rm; }}); 183 0x1b: ldrsb_puwl({{ Rd = Mem.sb; 184 Rn = Rn - Rm; }}, 185 {{ EA = Rn - Rm; }}); 186 0x1d: ldrsb_puil({{ Rd = Mem.sb; }}, 187 {{ EA = Rn - hilo; }}); 188 0x1f: ldrsb_puiwl({{ Rd = Mem.sb; 189 Rn = Rn - hilo; }}, 190 {{ EA = Rn - hilo; }}); 191 } 192 0xf: decode PUBWL { 193 0x1: ldrsh_l({{ Rd = Mem.sh; 194 Rn = Rn + Rm; }}, 195 {{ EA = Rn; }}); 196 0x5: ldrsh_il({{ Rd = Mem.sh; 197 Rn = Rn + hilo; }}, 198 {{ EA = Rn; }}); 199 0x9: ldrsh_ul({{ Rd = Mem.sh; 200 Rn = Rn - Rm; }}, 201 {{ EA = Rn; }}); 202 0xd: ldrsh_uil({{ Rd = Mem.sh; 203 Rn = Rn - hilo; }}, 204 {{ EA = Rn; }}); 205 0x11: ldrsh_pl({{ Rd = Mem.sh; }}, 206 {{ EA = Rn + Rm; }}); 207 0x13: ldrsh_pwl({{ Rd = Mem.sh; 208 Rn = Rn + Rm; }}, 209 {{ EA = Rn + Rm; }}); 210 0x15: ldrsh_pil({{ Rd = Mem.sh; }}, 211 {{ EA = Rn + hilo; }}); 212 0x17: ldrsh_piwl({{ Rd = Mem.sh; 213 Rn = Rn + hilo; }}, 214 {{ EA = Rn + hilo; }}); 215 0x19: ldrsh_pul({{ Rd = Mem.sh; }}, 216 {{ EA = Rn - Rm; }}); 217 0x1b: ldrsh_puwl({{ Rd = Mem.sh; 218 Rn = Rn - Rm; }}, 219 {{ EA = Rn - Rm; }}); 220 0x1d: ldrsh_puil({{ Rd = Mem.sh; }}, 221 {{ EA = Rn - hilo; }}); 222 0x1f: ldrsh_puiwl({{ Rd = Mem.sh; 223 Rn = Rn - hilo; }}, 224 {{ EA = Rn - hilo; }}); 225 } 226 } 227 } 228 0: decode IS_MISC { 229 0: decode OPCODE { 230 0x0: and({{ Rd = resTemp = Rn & op2; }}); 231 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 232 0x2: sub({{ Rd = resTemp = Rn - op2; }}, 233 {{ arm_sub_carry(resTemp, Rn, op2) }}, 234 {{ arm_sub_overflow(resTemp, Rn, op2) }}); 235 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, 236 {{ arm_sub_carry(resTemp, op2, Rn) }}, 237 {{ arm_sub_overflow(resTemp, op2, Rn) }}); 238 0x4: add({{ Rd = resTemp = Rn + op2; }}, 239 {{ arm_add_carry(resTemp, Rn, op2) }}, 240 {{ arm_add_overflow(resTemp, Rn, op2) }}); 241 0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }}, 242 {{ arm_add_carry(resTemp, Rn, op2) }}, 243 {{ arm_add_overflow(resTemp, Rn, op2) }}); 244 0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }}, 245 {{ arm_sub_carry(resTemp, Rn, op2) }}, 246 {{ arm_sub_overflow(resTemp, Rn, op2) }}); 247 0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }}, 248 {{ arm_sub_carry(resTemp, op2, Rn) }}, 249 {{ arm_sub_overflow(resTemp, op2, Rn) }}); 250 0x8: tst({{ resTemp = Rn & op2; }}); 251 0x9: teq({{ resTemp = Rn ^ op2; }}); 252 0xa: cmp({{ resTemp = Rn - op2; }}, 253 {{ arm_sub_carry(resTemp, Rn, op2) }}, 254 {{ arm_sub_overflow(resTemp, Rn, op2) }}); 255 0xb: cmn({{ resTemp = Rn + op2; }}, 256 {{ arm_add_carry(resTemp, Rn, op2) }}, 257 {{ arm_add_overflow(resTemp, Rn, op2) }}); 258 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 259 0xd: mov({{ Rd = resTemp = op2; }}); 260 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 261 0xf: mvn({{ Rd = resTemp = ~op2; }}); 262 } 263 1: decode MISC_OPCODE { 264 0x0: decode OPCODE { 265 0x8: WarnUnimpl::mrs_cpsr(); 266 0x9: WarnUnimpl::msr_cpsr(); 267 0xa: WarnUnimpl::mrs_spsr(); 268 0xb: WarnUnimpl::msr_spsr(); 269 } 270 0x1: decode OPCODE { 271 0x9: BranchExchange::bx({{ }}); 272 0xb: PredOp::clz({{ 273 if (Rm == 0) 274 Rd = 32; 275 else 276 { 277 int i; 278 for (i = 0; i < 32; i++) 279 { 280 if (Rm & (1<<(31-i))) 281 break; 282 } 283 Rd = i; 284 } 285 }}); 286 } 287 0x2: decode OPCODE { 288 0x9: WarnUnimpl::bxj(); 289 } 290 0x3: decode OPCODE { 291 0x9: BranchExchange::blx({{ }}, Link); 292 } 293 0x5: decode OPCODE { 294 0x8: WarnUnimpl::qadd(); 295 0x9: WarnUnimpl::qsub(); 296 0xa: WarnUnimpl::qdadd(); 297 0xb: WarnUnimpl::qdsub(); 298 } 299 0x8: decode OPCODE { 300 0x8: WarnUnimpl::smlabb(); 301 0x9: WarnUnimpl::smlalbb(); 302 0xa: WarnUnimpl::smlawb(); 303 0xb: WarnUnimpl::smulbb(); 304 } 305 0xa: decode OPCODE { 306 0x8: WarnUnimpl::smlatb(); 307 0x9: WarnUnimpl::smulwb(); 308 0xa: WarnUnimpl::smlaltb(); 309 0xb: WarnUnimpl::smultb(); 310 } 311 0xc: decode OPCODE { 312 0x8: WarnUnimpl::smlabt(); 313 0x9: WarnUnimpl::smlawt(); 314 0xa: WarnUnimpl::smlalbt(); 315 0xb: WarnUnimpl::smulbt(); 316 } 317 0xe: decode OPCODE { 318 0x8: WarnUnimpl::smlatt(); 319 0x9: WarnUnimpl::smulwt(); 320 0xa: WarnUnimpl::smlaltt(); 321 0xb: WarnUnimpl::smultt(); 322 } 323 } 324 } 325 } 326 0x1: decode IS_MISC { 327 0: decode OPCODE { 328 format DataImmOp { 329 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 330 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 331 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, 332 {{ arm_sub_carry(resTemp, Rn, rotated_imm) }}, 333 {{ arm_sub_overflow(resTemp, Rn, rotated_imm) }}); 334 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, 335 {{ arm_sub_carry(resTemp, rotated_imm, Rn) }}, 336 {{ arm_sub_overflow(resTemp, rotated_imm, Rn) }}); 337 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, 338 {{ arm_add_carry(resTemp, Rn, rotated_imm) }}, 339 {{ arm_add_overflow(resTemp, Rn, rotated_imm) }}); 340 0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }}, 341 {{ arm_add_carry(resTemp, Rn, rotated_imm) }}, 342 {{ arm_add_overflow(resTemp, Rn, rotated_imm) }}); 343 0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }}, 344 {{ arm_sub_carry(resTemp, Rn, rotated_imm) }}, 345 {{ arm_sub_overflow(resTemp, Rn, rotated_imm) }}); 346 0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}}, 347 {{ arm_sub_carry(resTemp, rotated_imm, Rn) }}, 348 {{ arm_sub_overflow(resTemp, rotated_imm, Rn) }}); 349 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 350 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 351 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, 352 {{ arm_sub_carry(resTemp, Rn, rotated_imm) }}, 353 {{ arm_sub_overflow(resTemp, Rn, rotated_imm) }}); 354 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, 355 {{ arm_add_carry(resTemp, Rn, rotated_imm) }}, 356 {{ arm_add_overflow(resTemp, Rn, rotated_imm) }}); 357 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 358 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 359 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 360 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 361 } 362 } 363 1: decode OPCODE { 364 // The following two instructions aren't supposed to be defined 365 0x8: WarnUnimpl::undefined_instruction(); 366 0x9: WarnUnimpl::undefined_instruction(); 367 368 0xa: WarnUnimpl::mrs_i_cpsr(); 369 0xb: WarnUnimpl::mrs_i_spsr(); 370 } 371 } 372 0x2: decode PUBWL { 373 // CAREFUL: 374 // Can always do EA + disp, since we negate disp using the UP flag 375 // Post-indexed variants 376 0x00,0x08: ArmStoreMemory::str_({{ Mem = Rd; 377 Rn = Rn + disp; }}, 378 {{ EA = Rn; }}); 379 0x01,0x09: ArmLoadMemory::ldr_l({{ Rn = Rn + disp; 380 Rd = Mem; }}, 381 {{ EA = Rn; }}); 382 0x04,0x0c: ArmStoreMemory::strb_b({{ Mem.ub = Rd.ub; 383 Rn = Rn + disp; }}, 384 {{ EA = Rn; }}); 385 0x05,0x0d: ArmLoadMemory::ldrb_bl({{ Rn = Rn + disp; 386 Rd.ub = Mem.ub; }}, 387 {{ EA = Rn; }}); 388 // Pre-indexed variants 389 0x10,0x18: ArmStoreMemory::str_p({{ Mem = Rd; }}); 390 0x11,0x19: ArmLoadMemory::ldr_pl({{ Rd = Mem; }}); 391 0x12,0x1a: ArmStoreMemory::str_pw({{ Mem = Rd; 392 Rn = Rn + disp; }}); 393 0x13,0x1b: ArmLoadMemory::ldr_pwl({{ Rn = Rn + disp; 394 Rd = Mem; }}); 395 0x14,0x1c: ArmStoreMemory::strb_pb({{ Mem.ub = Rd.ub; }}); 396 0x15,0x1d: ArmLoadMemory::ldrb_pbl({{ Rd.ub = Mem.ub; }}); 397 0x16,0x1e: ArmStoreMemory::strb_pbw({{ Mem.ub = Rd.ub; 398 Rn = Rn + disp; }}); 399 0x17,0x1f: ArmLoadMemory::ldrb_pbwl({{ Rn = Rn + disp; 400 Rd.ub = Mem.ub; }}); 401 } 402 0x3: decode OPCODE_4 { 403 0: decode PUBWL { 404 0x00,0x08: ArmStoreMemory::strr_({{ 405 Mem = Rd; 406 Rn = Rn + Rm_Imm; }}, 407 {{ EA = Rn; }}); 408 0x01,0x09: ArmLoadMemory::ldrr_l({{ 409 Rd = Mem; 410 Rn = Rn + Rm_Imm; }}, 411 {{ EA = Rn; }}); 412 0x04,0x0c: ArmStoreMemory::strr_b({{ 413 Mem.ub = Rd.ub; 414 Rn = Rn + Rm_Imm; }}, 415 {{ EA = Rn; }}); 416 0x05,0x0d: ArmLoadMemory::ldrr_bl({{ 417 Rd.ub = Mem.ub; 418 Rn = Rn + Rm_Imm; }}, 419 {{ EA = Rn; }}); 420 0x10,0x18: ArmStoreMemory::strr_p({{ 421 Mem = Rd; }}, 422 {{ EA = Rn + Rm_Imm; }}); 423 0x11,0x19: ArmLoadMemory::ldrr_pl({{ 424 Rd = Mem; }}, 425 {{ EA = Rn + Rm_Imm; }}); 426 0x12,0x1a: ArmStoreMemory::strr_pw({{ 427 Mem = Rd; 428 Rn = Rn + Rm_Imm; }}, 429 {{ EA = Rn + Rm_Imm; }}); 430 0x13,0x1b: ArmLoadMemory::ldrr_pwl({{ 431 Rd = Mem; 432 Rn = Rn + Rm_Imm; }}, 433 {{ EA = Rn + Rm_Imm; }}); 434 0x14,0x1c: ArmStoreMemory::strr_pb({{ 435 Mem.ub = Rd.ub; }}, 436 {{ EA = Rn + Rm_Imm; }}); 437 0x15,0x1d: ArmLoadMemory::ldrr_pbl({{ 438 Rd.ub = Mem.ub; }}, 439 {{ EA = Rn + Rm_Imm; }}); 440 0x16,0x1e: ArmStoreMemory::strr_pbw({{ 441 Mem.ub = Rd.ub; 442 Rn = Rn + Rm_Imm; }}, 443 {{ EA = Rn + Rm_Imm; }}); 444 0x17,0x1f: ArmLoadMemory::ldrr_pbwl({{ 445 Rd.ub = Mem.ub; 446 Rn = Rn + Rm_Imm; }}, 447 {{ EA = Rn + Rm_Imm; }}); 448 } 449 1: decode MEDIA_OPCODE { 450 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 451 0x8: decode MISC_OPCODE { 452 0x1, 0x9: WarnUnimpl::pkhbt(); 453 0x7: WarnUnimpl::sxtab16(); 454 0xb: WarnUnimpl::sel(); 455 0x5, 0xd: WarnUnimpl::pkhtb(); 456 0x3: WarnUnimpl::sign_zero_extend_add(); 457 } 458 0xa, 0xb: decode SHIFT { 459 0x0, 0x2: WarnUnimpl::ssat(); 460 0x1: WarnUnimpl::ssat16(); 461 } 462 0xe, 0xf: decode SHIFT { 463 0x0, 0x2: WarnUnimpl::usat(); 464 0x1: WarnUnimpl::usat16(); 465 } 466 0x10: decode RN { 467 0xf: decode MISC_OPCODE { 468 0x1: WarnUnimpl::smuad(); 469 0x3: WarnUnimpl::smuadx(); 470 0x5: WarnUnimpl::smusd(); 471 0x7: WarnUnimpl::smusdx(); 472 } 473 default: decode MISC_OPCODE { 474 0x1: WarnUnimpl::smlad(); 475 0x3: WarnUnimpl::smladx(); 476 0x5: WarnUnimpl::smlsd(); 477 0x7: WarnUnimpl::smlsdx(); 478 } 479 } 480 0x14: decode MISC_OPCODE { 481 0x1: WarnUnimpl::smlald(); 482 0x3: WarnUnimpl::smlaldx(); 483 0x5: WarnUnimpl::smlsld(); 484 0x7: WarnUnimpl::smlsldx(); 485 } 486 0x15: decode RN { 487 0xf: decode MISC_OPCODE { 488 0x1: WarnUnimpl::smmul(); 489 0x3: WarnUnimpl::smmulr(); 490 } 491 default: decode MISC_OPCODE { 492 0x1: WarnUnimpl::smmla(); 493 0x3: WarnUnimpl::smmlar(); 494 0xd: WarnUnimpl::smmls(); 495 0xf: WarnUnimpl::smmlsr(); 496 } 497 } 498 0x18: decode RN { 499 0xf: WarnUnimpl::usada8(); 500 default: WarnUnimpl::usad8(); 501 } 502 } 503 } 504 0x4: decode PUSWL { 505 // Right now we only handle cases when S (PSRUSER) is not set 506 default: ArmMacroStore::ldmstm({{ }}); 507 } 508 0x5: decode OPCODE_24 { 509 // Branch (and Link) Instructions 510 0: Branch::b({{ }}); 511 1: Branch::bl({{ }}, Link); 512 } 513 0x6: decode CPNUM { 514 0x1: decode PUNWL { 515 0x02,0x0a: decode OPCODE_15 { 516 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 517 Rn = Rn + disp8; }}, 518 {{ EA = Rn; }}); 519 1: ArmMacroFPAOp::stfd_({{ }}); 520 } 521 0x03,0x0b: decode OPCODE_15 { 522 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 523 Rn = Rn + disp8; }}, 524 {{ EA = Rn; }}); 525 1: ArmMacroFPAOp::ldfd_({{ }}); 526 } 527 0x06,0x0e: decode OPCODE_15 { 528 0: ArmMacroFPAOp::stfe_nw({{ }}); 529 } 530 0x07,0x0f: decode OPCODE_15 { 531 0: ArmMacroFPAOp::ldfe_nw({{ }}); 532 } 533 0x10,0x18: decode OPCODE_15 { 534 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 535 {{ EA = Rn + disp8; }}); 536 1: ArmMacroFPAOp::stfd_p({{ }}); 537 } 538 0x11,0x19: decode OPCODE_15 { 539 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 540 {{ EA = Rn + disp8; }}); 541 1: ArmMacroFPAOp::ldfd_p({{ }}); 542 } 543 0x12,0x1a: decode OPCODE_15 { 544 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 545 Rn = Rn + disp8; }}, 546 {{ EA = Rn + disp8; }}); 547 1: ArmMacroFPAOp::stfd_pw({{ }}); 548 } 549 0x13,0x1b: decode OPCODE_15 { 550 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 551 Rn = Rn + disp8; }}, 552 {{ EA = Rn + disp8; }}); 553 1: ArmMacroFPAOp::ldfd_pw({{ }}); 554 } 555 0x14,0x1c: decode OPCODE_15 { 556 0: ArmMacroFPAOp::stfe_pn({{ }}); 557 } 558 0x15,0x1d: decode OPCODE_15 { 559 0: ArmMacroFPAOp::ldfe_pn({{ }}); 560 } 561 0x16,0x1e: decode OPCODE_15 { 562 0: ArmMacroFPAOp::stfe_pnw({{ }}); 563 } 564 0x17,0x1f: decode OPCODE_15 { 565 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 566 } 567 } 568 0x2: decode PUNWL { 569 // could really just decode as a single instruction 570 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 571 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 572 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 573 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 574 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 575 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 576 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 577 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 578 } 579 } 580 0x7: decode OPCODE_24 { 581 0: decode CPNUM { 582 // Coprocessor Instructions 583 0x1: decode OPCODE_4 { 584 format FloatOp { 585 // Basic FPA Instructions 586 0: decode OPCODE_23_20 { 587 0x0: decode OPCODE_15 { 588 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 589 1: mvf({{ Fd.sf = Fm.sf; }}); 590 } 591 0x1: decode OPCODE_15 { 592 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 593 1: mnf({{ Fd.sf = -Fm.sf; }}); 594 } 595 0x2: decode OPCODE_15 { 596 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 597 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 598 } 599 0x3: decode OPCODE_15 { 600 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 601 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 602 } 603 0x4: decode OPCODE_15 { 604 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 605 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 606 } 607 0x5: decode OPCODE_15 { 608 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 609 1: log({{ Fd.sf = log10(Fm.sf); }}); 610 } 611 0x6: decode OPCODE_15 { 612 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 613 1: lgn({{ Fd.sf = log(Fm.sf); }}); 614 } 615 0x7: decode OPCODE_15 { 616 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 617 1: exp({{ Fd.sf = exp(Fm.sf); }}); 618 } 619 0x8: decode OPCODE_15 { 620 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 621 1: sin({{ Fd.sf = sin(Fm.sf); }}); 622 } 623 0x9: decode OPCODE_15 { 624 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 625 1: cos({{ Fd.sf = cos(Fm.sf); }}); 626 } 627 0xa: decode OPCODE_15 { 628 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 629 1: tan({{ Fd.sf = tan(Fm.sf); }}); 630 } 631 0xb: decode OPCODE_15 { 632 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 633 1: asn({{ Fd.sf = asin(Fm.sf); }}); 634 } 635 0xc: decode OPCODE_15 { 636 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 637 1: acs({{ Fd.sf = acos(Fm.sf); }}); 638 } 639 0xd: decode OPCODE_15 { 640 1: atn({{ Fd.sf = atan(Fm.sf); }}); 641 } 642 0xe: decode OPCODE_15 { 643 // Unnormalised Round 644 1: FailUnimpl::urd(); 645 } 646 0xf: decode OPCODE_15 { 647 // Normalise 648 1: FailUnimpl::nrm(); 649 } 650 } 651 1: decode OPCODE_15_12 { 652 0xf: decode OPCODE_23_21 { 653 format FloatCmp { 654 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 655 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 656 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 657 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 658 } 659 } 660 default: decode OPCODE_23_20 { 661 0x0: decode OPCODE_7 { 662 0: flts({{ Fn.sf = (float) Rd.sw; }}); 663 1: fltd({{ Fn.df = (double) Rd.sw; }}); 664 } 665 0x1: decode OPCODE_7 { 666 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 667 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 668 } 669 0x2: wfs({{ Fpsr = Rd; }}); 670 0x3: rfs({{ Rd = Fpsr; }}); 671 0x4: FailUnimpl::wfc(); 672 0x5: FailUnimpl::rfc(); 673 } 674 } 675 } 676 } 677 } 678 format PredOp { 679 // ARM System Call (SoftWare Interrupt) 680 1: swi({{ if (testPredicate(Cpsr, condCode)) 681 { 682 xc->syscall(IMMED_23_0); 683 } 684 }}); 685 } 686 } 687} 688} 689} 690 691