isa.cc revision 9050
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/system.hh" 43#include "cpu/checker/cpu.hh" 44#include "debug/Arm.hh" 45#include "debug/MiscRegs.hh" 46#include "sim/faults.hh" 47#include "sim/stat_control.hh" 48#include "sim/system.hh" 49 50namespace ArmISA 51{ 52 53void 54ISA::clear() 55{ 56 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 57 uint32_t midr = miscRegs[MISCREG_MIDR]; 58 memset(miscRegs, 0, sizeof(miscRegs)); 59 CPSR cpsr = 0; 60 cpsr.mode = MODE_USER; 61 miscRegs[MISCREG_CPSR] = cpsr; 62 updateRegMap(cpsr); 63 64 SCTLR sctlr = 0; 65 sctlr.te = (bool)sctlr_rst.te; 66 sctlr.nmfi = (bool)sctlr_rst.nmfi; 67 sctlr.v = (bool)sctlr_rst.v; 68 sctlr.u = 1; 69 sctlr.xp = 1; 70 sctlr.rao2 = 1; 71 sctlr.rao3 = 1; 72 sctlr.rao4 = 1; 73 miscRegs[MISCREG_SCTLR] = sctlr; 74 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 75 76 // Preserve MIDR across reset 77 miscRegs[MISCREG_MIDR] = midr; 78 79 /* Start with an event in the mailbox */ 80 miscRegs[MISCREG_SEV_MAILBOX] = 1; 81 82 // Separate Instruction and Data TLBs. 83 miscRegs[MISCREG_TLBTR] = 1; 84 85 MVFR0 mvfr0 = 0; 86 mvfr0.advSimdRegisters = 2; 87 mvfr0.singlePrecision = 2; 88 mvfr0.doublePrecision = 2; 89 mvfr0.vfpExceptionTrapping = 0; 90 mvfr0.divide = 1; 91 mvfr0.squareRoot = 1; 92 mvfr0.shortVectors = 1; 93 mvfr0.roundingModes = 1; 94 miscRegs[MISCREG_MVFR0] = mvfr0; 95 96 MVFR1 mvfr1 = 0; 97 mvfr1.flushToZero = 1; 98 mvfr1.defaultNaN = 1; 99 mvfr1.advSimdLoadStore = 1; 100 mvfr1.advSimdInteger = 1; 101 mvfr1.advSimdSinglePrecision = 1; 102 mvfr1.advSimdHalfPrecision = 1; 103 mvfr1.vfpHalfPrecision = 1; 104 miscRegs[MISCREG_MVFR1] = mvfr1; 105 106 // Reset values of PRRR and NMRR are implementation dependent 107 108 miscRegs[MISCREG_PRRR] = 109 (1 << 19) | // 19 110 (0 << 18) | // 18 111 (0 << 17) | // 17 112 (1 << 16) | // 16 113 (2 << 14) | // 15:14 114 (0 << 12) | // 13:12 115 (2 << 10) | // 11:10 116 (2 << 8) | // 9:8 117 (2 << 6) | // 7:6 118 (2 << 4) | // 5:4 119 (1 << 2) | // 3:2 120 0; // 1:0 121 miscRegs[MISCREG_NMRR] = 122 (1 << 30) | // 31:30 123 (0 << 26) | // 27:26 124 (0 << 24) | // 25:24 125 (3 << 22) | // 23:22 126 (2 << 20) | // 21:20 127 (0 << 18) | // 19:18 128 (0 << 16) | // 17:16 129 (1 << 14) | // 15:14 130 (0 << 12) | // 13:12 131 (2 << 10) | // 11:10 132 (0 << 8) | // 9:8 133 (3 << 6) | // 7:6 134 (2 << 4) | // 5:4 135 (0 << 2) | // 3:2 136 0; // 1:0 137 138 miscRegs[MISCREG_CPACR] = 0; 139 miscRegs[MISCREG_FPSID] = 0x410430A0; 140 141 // See section B4.1.84 of ARM ARM 142 // All values are latest for ARMv7-A profile 143 miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 144 miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 145 miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 146 miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 147 miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 148 miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 149 150 //XXX We need to initialize the rest of the state. 151} 152 153MiscReg 154ISA::readMiscRegNoEffect(int misc_reg) 155{ 156 assert(misc_reg < NumMiscRegs); 157 158 int flat_idx; 159 if (misc_reg == MISCREG_SPSR) 160 flat_idx = flattenMiscIndex(misc_reg); 161 else 162 flat_idx = misc_reg; 163 MiscReg val = miscRegs[flat_idx]; 164 165 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 166 misc_reg, flat_idx, val); 167 return val; 168} 169 170 171MiscReg 172ISA::readMiscReg(int misc_reg, ThreadContext *tc) 173{ 174 ArmSystem *arm_sys; 175 176 if (misc_reg == MISCREG_CPSR) { 177 CPSR cpsr = miscRegs[misc_reg]; 178 PCState pc = tc->pcState(); 179 cpsr.j = pc.jazelle() ? 1 : 0; 180 cpsr.t = pc.thumb() ? 1 : 0; 181 return cpsr; 182 } 183 if (misc_reg >= MISCREG_CP15_UNIMP_START) 184 panic("Unimplemented CP15 register %s read.\n", 185 miscRegName[misc_reg]); 186 187 switch (misc_reg) { 188 case MISCREG_MPIDR: 189 arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 190 assert(arm_sys); 191 192 if (arm_sys->multiProc) { 193 return 0x80000000 | // multiprocessor extensions available 194 tc->cpuId(); 195 } else { 196 return 0x80000000 | // multiprocessor extensions available 197 0x40000000 | // in up system 198 tc->cpuId(); 199 } 200 break; 201 case MISCREG_ID_MMFR0: 202 return 0x03; // VMSAv7 support 203 case MISCREG_ID_MMFR2: 204 return 0x01230000; // no HW access | WFI stalling | ISB and DSB 205 // | all TLB maintenance | no Harvard 206 case MISCREG_ID_MMFR3: 207 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 208 // BP Maint | Cache Maint Set/way | Cache Maint MVA 209 case MISCREG_CLIDR: 210 warn_once("The clidr register always reports 0 caches.\n"); 211 warn_once("clidr LoUIS field of 0b001 to match current " 212 "ARM implementations.\n"); 213 return 0x00200000; 214 case MISCREG_CCSIDR: 215 warn_once("The ccsidr register isn't implemented and " 216 "always reads as 0.\n"); 217 break; 218 case MISCREG_ID_PFR0: 219 warn("Returning thumbEE disabled for now since we don't support CP14" 220 "config registers and jumping to ThumbEE vectors\n"); 221 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 222 case MISCREG_ID_PFR1: 223 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 224 case MISCREG_CTR: 225 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 226 case MISCREG_ACTLR: 227 warn("Not doing anything for miscreg ACTLR\n"); 228 break; 229 case MISCREG_PMCR: 230 case MISCREG_PMCCNTR: 231 case MISCREG_PMSELR: 232 warn("Not doing anything for read to miscreg %s\n", 233 miscRegName[misc_reg]); 234 break; 235 case MISCREG_CPSR_Q: 236 panic("shouldn't be reading this register seperately\n"); 237 case MISCREG_FPSCR_QC: 238 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 239 case MISCREG_FPSCR_EXC: 240 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 241 case MISCREG_L2CTLR: 242 { 243 // mostly unimplemented, just set NumCPUs field from sim and return 244 L2CTLR l2ctlr = 0; 245 // b00:1CPU to b11:4CPUs 246 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 247 return l2ctlr; 248 } 249 case MISCREG_DBGDIDR: 250 /* For now just implement the version number. 251 * Return 0 as we don't support debug architecture yet. 252 */ 253 return 0; 254 case MISCREG_DBGDSCR_INT: 255 return 0; 256 } 257 return readMiscRegNoEffect(misc_reg); 258} 259 260void 261ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 262{ 263 assert(misc_reg < NumMiscRegs); 264 265 int flat_idx; 266 if (misc_reg == MISCREG_SPSR) 267 flat_idx = flattenMiscIndex(misc_reg); 268 else 269 flat_idx = misc_reg; 270 miscRegs[flat_idx] = val; 271 272 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 273 flat_idx, val); 274} 275 276void 277ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 278{ 279 280 MiscReg newVal = val; 281 int x; 282 System *sys; 283 ThreadContext *oc; 284 285 if (misc_reg == MISCREG_CPSR) { 286 updateRegMap(val); 287 288 289 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 290 int old_mode = old_cpsr.mode; 291 CPSR cpsr = val; 292 if (old_mode != cpsr.mode) { 293 tc->getITBPtr()->invalidateMiscReg(); 294 tc->getDTBPtr()->invalidateMiscReg(); 295 } 296 297 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 298 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 299 PCState pc = tc->pcState(); 300 pc.nextThumb(cpsr.t); 301 pc.nextJazelle(cpsr.j); 302 303 // Follow slightly different semantics if a CheckerCPU object 304 // is connected 305 CheckerCPU *checker = tc->getCheckerCpuPtr(); 306 if (checker) { 307 tc->pcStateNoRecord(pc); 308 } else { 309 tc->pcState(pc); 310 } 311 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 312 misc_reg < MISCREG_CP15_END) { 313 panic("Unimplemented CP15 register %s wrote with %#x.\n", 314 miscRegName[misc_reg], val); 315 } else { 316 switch (misc_reg) { 317 case MISCREG_CPACR: 318 { 319 320 const uint32_t ones = (uint32_t)(-1); 321 CPACR cpacrMask = 0; 322 // Only cp10, cp11, and ase are implemented, nothing else should 323 // be writable 324 cpacrMask.cp10 = ones; 325 cpacrMask.cp11 = ones; 326 cpacrMask.asedis = ones; 327 newVal &= cpacrMask; 328 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 329 miscRegName[misc_reg], newVal); 330 } 331 break; 332 case MISCREG_CSSELR: 333 warn_once("The csselr register isn't implemented.\n"); 334 return; 335 case MISCREG_FPSCR: 336 { 337 const uint32_t ones = (uint32_t)(-1); 338 FPSCR fpscrMask = 0; 339 fpscrMask.ioc = ones; 340 fpscrMask.dzc = ones; 341 fpscrMask.ofc = ones; 342 fpscrMask.ufc = ones; 343 fpscrMask.ixc = ones; 344 fpscrMask.idc = ones; 345 fpscrMask.len = ones; 346 fpscrMask.stride = ones; 347 fpscrMask.rMode = ones; 348 fpscrMask.fz = ones; 349 fpscrMask.dn = ones; 350 fpscrMask.ahp = ones; 351 fpscrMask.qc = ones; 352 fpscrMask.v = ones; 353 fpscrMask.c = ones; 354 fpscrMask.z = ones; 355 fpscrMask.n = ones; 356 newVal = (newVal & (uint32_t)fpscrMask) | 357 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 358 } 359 break; 360 case MISCREG_CPSR_Q: 361 { 362 assert(!(newVal & ~CpsrMaskQ)); 363 newVal = miscRegs[MISCREG_CPSR] | newVal; 364 misc_reg = MISCREG_CPSR; 365 } 366 break; 367 case MISCREG_FPSCR_QC: 368 { 369 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 370 misc_reg = MISCREG_FPSCR; 371 } 372 break; 373 case MISCREG_FPSCR_EXC: 374 { 375 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 376 misc_reg = MISCREG_FPSCR; 377 } 378 break; 379 case MISCREG_FPEXC: 380 { 381 // vfpv3 architecture, section B.6.1 of DDI04068 382 // bit 29 - valid only if fpexc[31] is 0 383 const uint32_t fpexcMask = 0x60000000; 384 newVal = (newVal & fpexcMask) | 385 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 386 } 387 break; 388 case MISCREG_SCTLR: 389 { 390 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 391 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 392 SCTLR new_sctlr = newVal; 393 new_sctlr.nmfi = (bool)sctlr.nmfi; 394 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 395 tc->getITBPtr()->invalidateMiscReg(); 396 tc->getDTBPtr()->invalidateMiscReg(); 397 398 // Check if all CPUs are booted with caches enabled 399 // so we can stop enforcing coherency of some kernel 400 // structures manually. 401 sys = tc->getSystemPtr(); 402 for (x = 0; x < sys->numContexts(); x++) { 403 oc = sys->getThreadContext(x); 404 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 405 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 406 return; 407 } 408 409 for (x = 0; x < sys->numContexts(); x++) { 410 oc = sys->getThreadContext(x); 411 oc->getDTBPtr()->allCpusCaching(); 412 oc->getITBPtr()->allCpusCaching(); 413 414 // If CheckerCPU is connected, need to notify it. 415 CheckerCPU *checker = oc->getCheckerCpuPtr(); 416 if (checker) { 417 checker->getDTBPtr()->allCpusCaching(); 418 checker->getITBPtr()->allCpusCaching(); 419 } 420 } 421 return; 422 } 423 case MISCREG_TLBTR: 424 case MISCREG_MVFR0: 425 case MISCREG_MVFR1: 426 case MISCREG_MPIDR: 427 case MISCREG_FPSID: 428 return; 429 case MISCREG_TLBIALLIS: 430 case MISCREG_TLBIALL: 431 sys = tc->getSystemPtr(); 432 for (x = 0; x < sys->numContexts(); x++) { 433 oc = sys->getThreadContext(x); 434 assert(oc->getITBPtr() && oc->getDTBPtr()); 435 oc->getITBPtr()->flushAll(); 436 oc->getDTBPtr()->flushAll(); 437 438 // If CheckerCPU is connected, need to notify it of a flush 439 CheckerCPU *checker = oc->getCheckerCpuPtr(); 440 if (checker) { 441 checker->getITBPtr()->flushAll(); 442 checker->getDTBPtr()->flushAll(); 443 } 444 } 445 return; 446 case MISCREG_ITLBIALL: 447 tc->getITBPtr()->flushAll(); 448 return; 449 case MISCREG_DTLBIALL: 450 tc->getDTBPtr()->flushAll(); 451 return; 452 case MISCREG_TLBIMVAIS: 453 case MISCREG_TLBIMVA: 454 sys = tc->getSystemPtr(); 455 for (x = 0; x < sys->numContexts(); x++) { 456 oc = sys->getThreadContext(x); 457 assert(oc->getITBPtr() && oc->getDTBPtr()); 458 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 459 bits(newVal, 7,0)); 460 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 461 bits(newVal, 7,0)); 462 463 CheckerCPU *checker = oc->getCheckerCpuPtr(); 464 if (checker) { 465 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 466 bits(newVal, 7,0)); 467 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 468 bits(newVal, 7,0)); 469 } 470 } 471 return; 472 case MISCREG_TLBIASIDIS: 473 case MISCREG_TLBIASID: 474 sys = tc->getSystemPtr(); 475 for (x = 0; x < sys->numContexts(); x++) { 476 oc = sys->getThreadContext(x); 477 assert(oc->getITBPtr() && oc->getDTBPtr()); 478 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 479 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 480 CheckerCPU *checker = oc->getCheckerCpuPtr(); 481 if (checker) { 482 checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 483 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 484 } 485 } 486 return; 487 case MISCREG_TLBIMVAAIS: 488 case MISCREG_TLBIMVAA: 489 sys = tc->getSystemPtr(); 490 for (x = 0; x < sys->numContexts(); x++) { 491 oc = sys->getThreadContext(x); 492 assert(oc->getITBPtr() && oc->getDTBPtr()); 493 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 494 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 495 496 CheckerCPU *checker = oc->getCheckerCpuPtr(); 497 if (checker) { 498 checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 499 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 500 } 501 } 502 return; 503 case MISCREG_ITLBIMVA: 504 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 505 bits(newVal, 7,0)); 506 return; 507 case MISCREG_DTLBIMVA: 508 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 509 bits(newVal, 7,0)); 510 return; 511 case MISCREG_ITLBIASID: 512 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 513 return; 514 case MISCREG_DTLBIASID: 515 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 516 return; 517 case MISCREG_ACTLR: 518 warn("Not doing anything for write of miscreg ACTLR\n"); 519 break; 520 case MISCREG_PMCR: 521 { 522 // Performance counters not implemented. Instead, interpret 523 // a reset command to this register to reset the simulator 524 // statistics. 525 // PMCR_E | PMCR_P | PMCR_C 526 const int ResetAndEnableCounters = 0x7; 527 if (newVal == ResetAndEnableCounters) { 528 inform("Resetting all simobject stats\n"); 529 Stats::schedStatEvent(false, true); 530 break; 531 } 532 } 533 case MISCREG_PMCCNTR: 534 case MISCREG_PMSELR: 535 warn("Not doing anything for write to miscreg %s\n", 536 miscRegName[misc_reg]); 537 break; 538 case MISCREG_V2PCWPR: 539 case MISCREG_V2PCWPW: 540 case MISCREG_V2PCWUR: 541 case MISCREG_V2PCWUW: 542 case MISCREG_V2POWPR: 543 case MISCREG_V2POWPW: 544 case MISCREG_V2POWUR: 545 case MISCREG_V2POWUW: 546 { 547 RequestPtr req = new Request; 548 unsigned flags; 549 BaseTLB::Mode mode; 550 Fault fault; 551 switch(misc_reg) { 552 case MISCREG_V2PCWPR: 553 flags = TLB::MustBeOne; 554 mode = BaseTLB::Read; 555 break; 556 case MISCREG_V2PCWPW: 557 flags = TLB::MustBeOne; 558 mode = BaseTLB::Write; 559 break; 560 case MISCREG_V2PCWUR: 561 flags = TLB::MustBeOne | TLB::UserMode; 562 mode = BaseTLB::Read; 563 break; 564 case MISCREG_V2PCWUW: 565 flags = TLB::MustBeOne | TLB::UserMode; 566 mode = BaseTLB::Write; 567 break; 568 default: 569 panic("Security Extensions not implemented!"); 570 } 571 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 572 req->setVirt(0, val, 1, flags, tc->pcState().pc(), 573 Request::funcMasterId); 574 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 575 if (fault == NoFault) { 576 miscRegs[MISCREG_PAR] = 577 (req->getPaddr() & 0xfffff000) | 578 (tc->getDTBPtr()->getAttr() ); 579 DPRINTF(MiscRegs, 580 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 581 val, miscRegs[MISCREG_PAR]); 582 } 583 else { 584 // Set fault bit and FSR 585 FSR fsr = miscRegs[MISCREG_DFSR]; 586 miscRegs[MISCREG_PAR] = 587 (fsr.ext << 6) | 588 (fsr.fsHigh << 5) | 589 (fsr.fsLow << 1) | 590 0x1; // F bit 591 } 592 return; 593 } 594 case MISCREG_CONTEXTIDR: 595 case MISCREG_PRRR: 596 case MISCREG_NMRR: 597 case MISCREG_DACR: 598 tc->getITBPtr()->invalidateMiscReg(); 599 tc->getDTBPtr()->invalidateMiscReg(); 600 break; 601 case MISCREG_CPSR_MODE: 602 // This miscreg is used by copy*Regs to set the CPSR mode 603 // without updating other CPSR variables. It's used to 604 // make sure the register map is in such a state that we can 605 // see all of the registers for the copy. 606 updateRegMap(val); 607 return; 608 case MISCREG_L2CTLR: 609 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 610 miscRegName[misc_reg], uint32_t(val)); 611 } 612 } 613 setMiscRegNoEffect(misc_reg, newVal); 614} 615 616} 617