isa.cc revision 8870
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "config/use_checker.hh" 43#include "debug/Arm.hh" 44#include "debug/MiscRegs.hh" 45#include "sim/faults.hh" 46#include "sim/stat_control.hh" 47#include "sim/system.hh" 48 49#if USE_CHECKER 50#include "cpu/checker/cpu.hh" 51#endif 52 53namespace ArmISA 54{ 55 56void 57ISA::clear() 58{ 59 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 60 uint32_t midr = miscRegs[MISCREG_MIDR]; 61 memset(miscRegs, 0, sizeof(miscRegs)); 62 CPSR cpsr = 0; 63 cpsr.mode = MODE_USER; 64 miscRegs[MISCREG_CPSR] = cpsr; 65 updateRegMap(cpsr); 66 67 SCTLR sctlr = 0; 68 sctlr.te = (bool)sctlr_rst.te; 69 sctlr.nmfi = (bool)sctlr_rst.nmfi; 70 sctlr.v = (bool)sctlr_rst.v; 71 sctlr.u = 1; 72 sctlr.xp = 1; 73 sctlr.rao2 = 1; 74 sctlr.rao3 = 1; 75 sctlr.rao4 = 1; 76 miscRegs[MISCREG_SCTLR] = sctlr; 77 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 78 79 // Preserve MIDR accross reset 80 miscRegs[MISCREG_MIDR] = midr; 81 82 /* Start with an event in the mailbox */ 83 miscRegs[MISCREG_SEV_MAILBOX] = 1; 84 85 // Separate Instruction and Data TLBs. 86 miscRegs[MISCREG_TLBTR] = 1; 87 88 MVFR0 mvfr0 = 0; 89 mvfr0.advSimdRegisters = 2; 90 mvfr0.singlePrecision = 2; 91 mvfr0.doublePrecision = 2; 92 mvfr0.vfpExceptionTrapping = 0; 93 mvfr0.divide = 1; 94 mvfr0.squareRoot = 1; 95 mvfr0.shortVectors = 1; 96 mvfr0.roundingModes = 1; 97 miscRegs[MISCREG_MVFR0] = mvfr0; 98 99 MVFR1 mvfr1 = 0; 100 mvfr1.flushToZero = 1; 101 mvfr1.defaultNaN = 1; 102 mvfr1.advSimdLoadStore = 1; 103 mvfr1.advSimdInteger = 1; 104 mvfr1.advSimdSinglePrecision = 1; 105 mvfr1.advSimdHalfPrecision = 1; 106 mvfr1.vfpHalfPrecision = 1; 107 miscRegs[MISCREG_MVFR1] = mvfr1; 108 109 miscRegs[MISCREG_MPIDR] = 0; 110 111 // Reset values of PRRR and NMRR are implementation dependent 112 113 miscRegs[MISCREG_PRRR] = 114 (1 << 19) | // 19 115 (0 << 18) | // 18 116 (0 << 17) | // 17 117 (1 << 16) | // 16 118 (2 << 14) | // 15:14 119 (0 << 12) | // 13:12 120 (2 << 10) | // 11:10 121 (2 << 8) | // 9:8 122 (2 << 6) | // 7:6 123 (2 << 4) | // 5:4 124 (1 << 2) | // 3:2 125 0; // 1:0 126 miscRegs[MISCREG_NMRR] = 127 (1 << 30) | // 31:30 128 (0 << 26) | // 27:26 129 (0 << 24) | // 25:24 130 (3 << 22) | // 23:22 131 (2 << 20) | // 21:20 132 (0 << 18) | // 19:18 133 (0 << 16) | // 17:16 134 (1 << 14) | // 15:14 135 (0 << 12) | // 13:12 136 (2 << 10) | // 11:10 137 (0 << 8) | // 9:8 138 (3 << 6) | // 7:6 139 (2 << 4) | // 5:4 140 (0 << 2) | // 3:2 141 0; // 1:0 142 143 miscRegs[MISCREG_CPACR] = 0; 144 miscRegs[MISCREG_FPSID] = 0x410430A0; 145 146 // See section B4.1.84 of ARM ARM 147 // All values are latest for ARMv7-A profile 148 miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 149 miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 150 miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 151 miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 152 miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 153 miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 154 155 //XXX We need to initialize the rest of the state. 156} 157 158MiscReg 159ISA::readMiscRegNoEffect(int misc_reg) 160{ 161 assert(misc_reg < NumMiscRegs); 162 163 int flat_idx; 164 if (misc_reg == MISCREG_SPSR) 165 flat_idx = flattenMiscIndex(misc_reg); 166 else 167 flat_idx = misc_reg; 168 MiscReg val = miscRegs[flat_idx]; 169 170 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 171 misc_reg, flat_idx, val); 172 return val; 173} 174 175 176MiscReg 177ISA::readMiscReg(int misc_reg, ThreadContext *tc) 178{ 179 if (misc_reg == MISCREG_CPSR) { 180 CPSR cpsr = miscRegs[misc_reg]; 181 PCState pc = tc->pcState(); 182 cpsr.j = pc.jazelle() ? 1 : 0; 183 cpsr.t = pc.thumb() ? 1 : 0; 184 return cpsr; 185 } 186 if (misc_reg >= MISCREG_CP15_UNIMP_START) 187 panic("Unimplemented CP15 register %s read.\n", 188 miscRegName[misc_reg]); 189 190 switch (misc_reg) { 191 case MISCREG_MPIDR: 192 return tc->cpuId(); 193 break; 194 case MISCREG_ID_MMFR0: 195 return 0x03; // VMSAv7 support 196 case MISCREG_ID_MMFR2: 197 return 0x01230000; // no HW access | WFI stalling | ISB and DSB 198 // | all TLB maintenance | no Harvard 199 case MISCREG_ID_MMFR3: 200 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 201 // BP Maint | Cache Maint Set/way | Cache Maint MVA 202 case MISCREG_CLIDR: 203 warn_once("The clidr register always reports 0 caches.\n"); 204 warn_once("clidr LoUIS field of 0b001 to match current " 205 "ARM implementations.\n"); 206 return 0x00200000; 207 case MISCREG_CCSIDR: 208 warn_once("The ccsidr register isn't implemented and " 209 "always reads as 0.\n"); 210 break; 211 case MISCREG_ID_PFR0: 212 warn("Returning thumbEE disabled for now since we don't support CP14" 213 "config registers and jumping to ThumbEE vectors\n"); 214 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 215 case MISCREG_ID_PFR1: 216 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 217 case MISCREG_CTR: 218 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 219 case MISCREG_ACTLR: 220 warn("Not doing anything for miscreg ACTLR\n"); 221 break; 222 case MISCREG_PMCR: 223 case MISCREG_PMCCNTR: 224 case MISCREG_PMSELR: 225 warn("Not doing anything for read to miscreg %s\n", 226 miscRegName[misc_reg]); 227 break; 228 case MISCREG_CPSR_Q: 229 panic("shouldn't be reading this register seperately\n"); 230 case MISCREG_FPSCR_QC: 231 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 232 case MISCREG_FPSCR_EXC: 233 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 234 case MISCREG_L2CTLR: 235 { 236 // mostly unimplemented, just set NumCPUs field from sim and return 237 L2CTLR l2ctlr = 0; 238 // b00:1CPU to b11:4CPUs 239 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 240 return l2ctlr; 241 } 242 case MISCREG_DBGDIDR: 243 /* For now just implement the version number. 244 * Return 0 as we don't support debug architecture yet. 245 */ 246 return 0; 247 case MISCREG_DBGDSCR_INT: 248 return 0; 249 } 250 return readMiscRegNoEffect(misc_reg); 251} 252 253void 254ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 255{ 256 assert(misc_reg < NumMiscRegs); 257 258 int flat_idx; 259 if (misc_reg == MISCREG_SPSR) 260 flat_idx = flattenMiscIndex(misc_reg); 261 else 262 flat_idx = misc_reg; 263 miscRegs[flat_idx] = val; 264 265 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 266 flat_idx, val); 267} 268 269void 270ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 271{ 272 273 MiscReg newVal = val; 274 int x; 275 System *sys; 276 ThreadContext *oc; 277 278 if (misc_reg == MISCREG_CPSR) { 279 updateRegMap(val); 280 281 282 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 283 int old_mode = old_cpsr.mode; 284 CPSR cpsr = val; 285 if (old_mode != cpsr.mode) { 286 tc->getITBPtr()->invalidateMiscReg(); 287 tc->getDTBPtr()->invalidateMiscReg(); 288 } 289 290 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 291 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 292 PCState pc = tc->pcState(); 293 pc.nextThumb(cpsr.t); 294 pc.nextJazelle(cpsr.j); 295#if USE_CHECKER 296 tc->pcStateNoRecord(pc); 297#else 298 tc->pcState(pc); 299#endif //USE_CHECKER 300 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 301 misc_reg < MISCREG_CP15_END) { 302 panic("Unimplemented CP15 register %s wrote with %#x.\n", 303 miscRegName[misc_reg], val); 304 } else { 305 switch (misc_reg) { 306 case MISCREG_CPACR: 307 { 308 309 const uint32_t ones = (uint32_t)(-1); 310 CPACR cpacrMask = 0; 311 // Only cp10, cp11, and ase are implemented, nothing else should 312 // be writable 313 cpacrMask.cp10 = ones; 314 cpacrMask.cp11 = ones; 315 cpacrMask.asedis = ones; 316 newVal &= cpacrMask; 317 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 318 miscRegName[misc_reg], newVal); 319 } 320 break; 321 case MISCREG_CSSELR: 322 warn_once("The csselr register isn't implemented.\n"); 323 return; 324 case MISCREG_FPSCR: 325 { 326 const uint32_t ones = (uint32_t)(-1); 327 FPSCR fpscrMask = 0; 328 fpscrMask.ioc = ones; 329 fpscrMask.dzc = ones; 330 fpscrMask.ofc = ones; 331 fpscrMask.ufc = ones; 332 fpscrMask.ixc = ones; 333 fpscrMask.idc = ones; 334 fpscrMask.len = ones; 335 fpscrMask.stride = ones; 336 fpscrMask.rMode = ones; 337 fpscrMask.fz = ones; 338 fpscrMask.dn = ones; 339 fpscrMask.ahp = ones; 340 fpscrMask.qc = ones; 341 fpscrMask.v = ones; 342 fpscrMask.c = ones; 343 fpscrMask.z = ones; 344 fpscrMask.n = ones; 345 newVal = (newVal & (uint32_t)fpscrMask) | 346 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 347 } 348 break; 349 case MISCREG_CPSR_Q: 350 { 351 assert(!(newVal & ~CpsrMaskQ)); 352 newVal = miscRegs[MISCREG_CPSR] | newVal; 353 misc_reg = MISCREG_CPSR; 354 } 355 break; 356 case MISCREG_FPSCR_QC: 357 { 358 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 359 misc_reg = MISCREG_FPSCR; 360 } 361 break; 362 case MISCREG_FPSCR_EXC: 363 { 364 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 365 misc_reg = MISCREG_FPSCR; 366 } 367 break; 368 case MISCREG_FPEXC: 369 { 370 // vfpv3 architecture, section B.6.1 of DDI04068 371 // bit 29 - valid only if fpexc[31] is 0 372 const uint32_t fpexcMask = 0x60000000; 373 newVal = (newVal & fpexcMask) | 374 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 375 } 376 break; 377 case MISCREG_SCTLR: 378 { 379 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 380 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 381 SCTLR new_sctlr = newVal; 382 new_sctlr.nmfi = (bool)sctlr.nmfi; 383 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 384 tc->getITBPtr()->invalidateMiscReg(); 385 tc->getDTBPtr()->invalidateMiscReg(); 386 387 // Check if all CPUs are booted with caches enabled 388 // so we can stop enforcing coherency of some kernel 389 // structures manually. 390 sys = tc->getSystemPtr(); 391 for (x = 0; x < sys->numContexts(); x++) { 392 oc = sys->getThreadContext(x); 393 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 394 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 395 return; 396 } 397 398 for (x = 0; x < sys->numContexts(); x++) { 399 oc = sys->getThreadContext(x); 400 oc->getDTBPtr()->allCpusCaching(); 401 oc->getITBPtr()->allCpusCaching(); 402#if USE_CHECKER 403 CheckerCPU *checker = 404 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 405 if (checker) { 406 checker->getDTBPtr()->allCpusCaching(); 407 checker->getITBPtr()->allCpusCaching(); 408 } 409#endif 410 } 411 return; 412 } 413 case MISCREG_TLBTR: 414 case MISCREG_MVFR0: 415 case MISCREG_MVFR1: 416 case MISCREG_MPIDR: 417 case MISCREG_FPSID: 418 return; 419 case MISCREG_TLBIALLIS: 420 case MISCREG_TLBIALL: 421 sys = tc->getSystemPtr(); 422 for (x = 0; x < sys->numContexts(); x++) { 423 oc = sys->getThreadContext(x); 424 assert(oc->getITBPtr() && oc->getDTBPtr()); 425 oc->getITBPtr()->flushAll(); 426 oc->getDTBPtr()->flushAll(); 427#if USE_CHECKER 428 CheckerCPU *checker = 429 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 430 if (checker) { 431 checker->getITBPtr()->flushAll(); 432 checker->getDTBPtr()->flushAll(); 433 } 434#endif 435 } 436 return; 437 case MISCREG_ITLBIALL: 438 tc->getITBPtr()->flushAll(); 439 return; 440 case MISCREG_DTLBIALL: 441 tc->getDTBPtr()->flushAll(); 442 return; 443 case MISCREG_TLBIMVAIS: 444 case MISCREG_TLBIMVA: 445 sys = tc->getSystemPtr(); 446 for (x = 0; x < sys->numContexts(); x++) { 447 oc = sys->getThreadContext(x); 448 assert(oc->getITBPtr() && oc->getDTBPtr()); 449 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 450 bits(newVal, 7,0)); 451 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 452 bits(newVal, 7,0)); 453#if USE_CHECKER 454 CheckerCPU *checker = 455 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 456 if (checker) { 457 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 458 bits(newVal, 7,0)); 459 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 460 bits(newVal, 7,0)); 461 } 462#endif 463 } 464 return; 465 case MISCREG_TLBIASIDIS: 466 case MISCREG_TLBIASID: 467 sys = tc->getSystemPtr(); 468 for (x = 0; x < sys->numContexts(); x++) { 469 oc = sys->getThreadContext(x); 470 assert(oc->getITBPtr() && oc->getDTBPtr()); 471 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 472 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 473#if USE_CHECKER 474 CheckerCPU *checker = 475 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 476 if (checker) { 477 checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 478 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 479 } 480#endif 481 } 482 return; 483 case MISCREG_TLBIMVAAIS: 484 case MISCREG_TLBIMVAA: 485 sys = tc->getSystemPtr(); 486 for (x = 0; x < sys->numContexts(); x++) { 487 oc = sys->getThreadContext(x); 488 assert(oc->getITBPtr() && oc->getDTBPtr()); 489 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 490 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 491#if USE_CHECKER 492 CheckerCPU *checker = 493 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 494 if (checker) { 495 checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 496 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 497 } 498#endif 499 } 500 return; 501 case MISCREG_ITLBIMVA: 502 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 503 bits(newVal, 7,0)); 504 return; 505 case MISCREG_DTLBIMVA: 506 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 507 bits(newVal, 7,0)); 508 return; 509 case MISCREG_ITLBIASID: 510 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 511 return; 512 case MISCREG_DTLBIASID: 513 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 514 return; 515 case MISCREG_ACTLR: 516 warn("Not doing anything for write of miscreg ACTLR\n"); 517 break; 518 case MISCREG_PMCR: 519 { 520 // Performance counters not implemented. Instead, interpret 521 // a reset command to this register to reset the simulator 522 // statistics. 523 // PMCR_E | PMCR_P | PMCR_C 524 const int ResetAndEnableCounters = 0x7; 525 if (newVal == ResetAndEnableCounters) { 526 inform("Resetting all simobject stats\n"); 527 Stats::schedStatEvent(false, true); 528 break; 529 } 530 } 531 case MISCREG_PMCCNTR: 532 case MISCREG_PMSELR: 533 warn("Not doing anything for write to miscreg %s\n", 534 miscRegName[misc_reg]); 535 break; 536 case MISCREG_V2PCWPR: 537 case MISCREG_V2PCWPW: 538 case MISCREG_V2PCWUR: 539 case MISCREG_V2PCWUW: 540 case MISCREG_V2POWPR: 541 case MISCREG_V2POWPW: 542 case MISCREG_V2POWUR: 543 case MISCREG_V2POWUW: 544 { 545 RequestPtr req = new Request; 546 unsigned flags; 547 BaseTLB::Mode mode; 548 Fault fault; 549 switch(misc_reg) { 550 case MISCREG_V2PCWPR: 551 flags = TLB::MustBeOne; 552 mode = BaseTLB::Read; 553 break; 554 case MISCREG_V2PCWPW: 555 flags = TLB::MustBeOne; 556 mode = BaseTLB::Write; 557 break; 558 case MISCREG_V2PCWUR: 559 flags = TLB::MustBeOne | TLB::UserMode; 560 mode = BaseTLB::Read; 561 break; 562 case MISCREG_V2PCWUW: 563 flags = TLB::MustBeOne | TLB::UserMode; 564 mode = BaseTLB::Write; 565 break; 566 default: 567 panic("Security Extensions not implemented!"); 568 } 569 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 570 req->setVirt(0, val, 1, flags, tc->pcState().pc(), 571 Request::funcMasterId); 572 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 573 if (fault == NoFault) { 574 miscRegs[MISCREG_PAR] = 575 (req->getPaddr() & 0xfffff000) | 576 (tc->getDTBPtr()->getAttr() ); 577 DPRINTF(MiscRegs, 578 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 579 val, miscRegs[MISCREG_PAR]); 580 } 581 else { 582 // Set fault bit and FSR 583 FSR fsr = miscRegs[MISCREG_DFSR]; 584 miscRegs[MISCREG_PAR] = 585 (fsr.ext << 6) | 586 (fsr.fsHigh << 5) | 587 (fsr.fsLow << 1) | 588 0x1; // F bit 589 } 590 return; 591 } 592 case MISCREG_CONTEXTIDR: 593 case MISCREG_PRRR: 594 case MISCREG_NMRR: 595 case MISCREG_DACR: 596 tc->getITBPtr()->invalidateMiscReg(); 597 tc->getDTBPtr()->invalidateMiscReg(); 598 break; 599 case MISCREG_CPSR_MODE: 600 // This miscreg is used by copy*Regs to set the CPSR mode 601 // without updating other CPSR variables. It's used to 602 // make sure the register map is in such a state that we can 603 // see all of the registers for the copy. 604 updateRegMap(val); 605 return; 606 case MISCREG_L2CTLR: 607 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 608 miscRegName[misc_reg], uint32_t(val)); 609 } 610 } 611 setMiscRegNoEffect(misc_reg, newVal); 612} 613 614} 615