isa.cc revision 8832
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "config/use_checker.hh"
43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
49#if USE_CHECKER
50#include "cpu/checker/cpu.hh"
51#endif
52
53namespace ArmISA
54{
55
56void
57ISA::clear()
58{
59    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
60    uint32_t midr = miscRegs[MISCREG_MIDR];
61    memset(miscRegs, 0, sizeof(miscRegs));
62    CPSR cpsr = 0;
63    cpsr.mode = MODE_USER;
64    miscRegs[MISCREG_CPSR] = cpsr;
65    updateRegMap(cpsr);
66
67    SCTLR sctlr = 0;
68    sctlr.te = (bool)sctlr_rst.te;
69    sctlr.nmfi = (bool)sctlr_rst.nmfi;
70    sctlr.v = (bool)sctlr_rst.v;
71    sctlr.u    = 1;
72    sctlr.xp = 1;
73    sctlr.rao2 = 1;
74    sctlr.rao3 = 1;
75    sctlr.rao4 = 1;
76    miscRegs[MISCREG_SCTLR] = sctlr;
77    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
78
79    // Preserve MIDR accross reset
80    miscRegs[MISCREG_MIDR] = midr;
81
82    /* Start with an event in the mailbox */
83    miscRegs[MISCREG_SEV_MAILBOX] = 1;
84
85    // Separate Instruction and Data TLBs.
86    miscRegs[MISCREG_TLBTR] = 1;
87
88    MVFR0 mvfr0 = 0;
89    mvfr0.advSimdRegisters = 2;
90    mvfr0.singlePrecision = 2;
91    mvfr0.doublePrecision = 2;
92    mvfr0.vfpExceptionTrapping = 0;
93    mvfr0.divide = 1;
94    mvfr0.squareRoot = 1;
95    mvfr0.shortVectors = 1;
96    mvfr0.roundingModes = 1;
97    miscRegs[MISCREG_MVFR0] = mvfr0;
98
99    MVFR1 mvfr1 = 0;
100    mvfr1.flushToZero = 1;
101    mvfr1.defaultNaN = 1;
102    mvfr1.advSimdLoadStore = 1;
103    mvfr1.advSimdInteger = 1;
104    mvfr1.advSimdSinglePrecision = 1;
105    mvfr1.advSimdHalfPrecision = 1;
106    mvfr1.vfpHalfPrecision = 1;
107    miscRegs[MISCREG_MVFR1] = mvfr1;
108
109    miscRegs[MISCREG_MPIDR] = 0;
110
111    // Reset values of PRRR and NMRR are implementation dependent
112
113    miscRegs[MISCREG_PRRR] =
114        (1 << 19) | // 19
115        (0 << 18) | // 18
116        (0 << 17) | // 17
117        (1 << 16) | // 16
118        (2 << 14) | // 15:14
119        (0 << 12) | // 13:12
120        (2 << 10) | // 11:10
121        (2 << 8)  | // 9:8
122        (2 << 6)  | // 7:6
123        (2 << 4)  | // 5:4
124        (1 << 2)  | // 3:2
125        0;          // 1:0
126    miscRegs[MISCREG_NMRR] =
127        (1 << 30) | // 31:30
128        (0 << 26) | // 27:26
129        (0 << 24) | // 25:24
130        (3 << 22) | // 23:22
131        (2 << 20) | // 21:20
132        (0 << 18) | // 19:18
133        (0 << 16) | // 17:16
134        (1 << 14) | // 15:14
135        (0 << 12) | // 13:12
136        (2 << 10) | // 11:10
137        (0 << 8)  | // 9:8
138        (3 << 6)  | // 7:6
139        (2 << 4)  | // 5:4
140        (0 << 2)  | // 3:2
141        0;          // 1:0
142
143    miscRegs[MISCREG_CPACR] = 0;
144    miscRegs[MISCREG_FPSID] = 0x410430A0;
145
146    // See section B4.1.84 of ARM ARM
147    // All values are latest for ARMv7-A profile
148    miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
149    miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
150    miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
151    miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
152    miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
153    miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
154
155    //XXX We need to initialize the rest of the state.
156}
157
158MiscReg
159ISA::readMiscRegNoEffect(int misc_reg)
160{
161    assert(misc_reg < NumMiscRegs);
162
163    int flat_idx;
164    if (misc_reg == MISCREG_SPSR)
165        flat_idx = flattenMiscIndex(misc_reg);
166    else
167        flat_idx = misc_reg;
168    MiscReg val = miscRegs[flat_idx];
169
170    DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
171            misc_reg, flat_idx, val);
172    return val;
173}
174
175
176MiscReg
177ISA::readMiscReg(int misc_reg, ThreadContext *tc)
178{
179    if (misc_reg == MISCREG_CPSR) {
180        CPSR cpsr = miscRegs[misc_reg];
181        PCState pc = tc->pcState();
182        cpsr.j = pc.jazelle() ? 1 : 0;
183        cpsr.t = pc.thumb() ? 1 : 0;
184        return cpsr;
185    }
186    if (misc_reg >= MISCREG_CP15_UNIMP_START)
187        panic("Unimplemented CP15 register %s read.\n",
188              miscRegName[misc_reg]);
189
190    switch (misc_reg) {
191      case MISCREG_MPIDR:
192        return tc->cpuId();
193        break;
194      case MISCREG_ID_MMFR0:
195        return 0x03; // VMSAv7 support
196      case MISCREG_ID_MMFR2:
197        return 0x01230000; // no HW access | WFI stalling | ISB and DSB
198                           // | all TLB maintenance | no Harvard
199      case MISCREG_ID_MMFR3:
200        return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
201                           // BP Maint | Cache Maint Set/way | Cache Maint MVA
202      case MISCREG_CLIDR:
203        warn_once("The clidr register always reports 0 caches.\n");
204        warn_once("clidr LoUIS field of 0b001 to match current "
205                  "ARM implementations.\n");
206        return 0x00200000;
207      case MISCREG_CCSIDR:
208        warn_once("The ccsidr register isn't implemented and "
209                "always reads as 0.\n");
210        break;
211      case MISCREG_ID_PFR0:
212        warn("Returning thumbEE disabled for now since we don't support CP14"
213             "config registers and jumping to ThumbEE vectors\n");
214        return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
215      case MISCREG_ID_PFR1:
216        warn("reading unimplmented register ID_PFR1");
217        return 0;
218      case MISCREG_CTR:
219        return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
220      case MISCREG_ACTLR:
221        warn("Not doing anything for miscreg ACTLR\n");
222        break;
223      case MISCREG_PMCR:
224      case MISCREG_PMCCNTR:
225      case MISCREG_PMSELR:
226        warn("Not doing anything for read to miscreg %s\n",
227                miscRegName[misc_reg]);
228        break;
229      case MISCREG_CPSR_Q:
230        panic("shouldn't be reading this register seperately\n");
231      case MISCREG_FPSCR_QC:
232        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
233      case MISCREG_FPSCR_EXC:
234        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
235      case MISCREG_L2CTLR:
236        // mostly unimplemented, just set NumCPUs field from sim and return
237        L2CTLR l2ctlr = 0;
238        // b00:1CPU to b11:4CPUs
239        l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
240        return l2ctlr;
241    }
242    return readMiscRegNoEffect(misc_reg);
243}
244
245void
246ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
247{
248    assert(misc_reg < NumMiscRegs);
249
250    int flat_idx;
251    if (misc_reg == MISCREG_SPSR)
252        flat_idx = flattenMiscIndex(misc_reg);
253    else
254        flat_idx = misc_reg;
255    miscRegs[flat_idx] = val;
256
257    DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
258            flat_idx, val);
259}
260
261void
262ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
263{
264
265    MiscReg newVal = val;
266    int x;
267    System *sys;
268    ThreadContext *oc;
269
270    if (misc_reg == MISCREG_CPSR) {
271        updateRegMap(val);
272
273
274        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
275        int old_mode = old_cpsr.mode;
276        CPSR cpsr = val;
277        if (old_mode != cpsr.mode) {
278            tc->getITBPtr()->invalidateMiscReg();
279            tc->getDTBPtr()->invalidateMiscReg();
280        }
281
282        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
283                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
284        PCState pc = tc->pcState();
285        pc.nextThumb(cpsr.t);
286        pc.nextJazelle(cpsr.j);
287#if USE_CHECKER
288        tc->pcStateNoRecord(pc);
289#else
290        tc->pcState(pc);
291#endif //USE_CHECKER
292    } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
293        misc_reg < MISCREG_CP15_END) {
294        panic("Unimplemented CP15 register %s wrote with %#x.\n",
295              miscRegName[misc_reg], val);
296    } else {
297        switch (misc_reg) {
298          case MISCREG_CPACR:
299            {
300
301                const uint32_t ones = (uint32_t)(-1);
302                CPACR cpacrMask = 0;
303                // Only cp10, cp11, and ase are implemented, nothing else should
304                // be writable
305                cpacrMask.cp10 = ones;
306                cpacrMask.cp11 = ones;
307                cpacrMask.asedis = ones;
308                newVal &= cpacrMask;
309                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
310                        miscRegName[misc_reg], newVal);
311            }
312            break;
313          case MISCREG_CSSELR:
314            warn_once("The csselr register isn't implemented.\n");
315            return;
316          case MISCREG_FPSCR:
317            {
318                const uint32_t ones = (uint32_t)(-1);
319                FPSCR fpscrMask = 0;
320                fpscrMask.ioc = ones;
321                fpscrMask.dzc = ones;
322                fpscrMask.ofc = ones;
323                fpscrMask.ufc = ones;
324                fpscrMask.ixc = ones;
325                fpscrMask.idc = ones;
326                fpscrMask.len = ones;
327                fpscrMask.stride = ones;
328                fpscrMask.rMode = ones;
329                fpscrMask.fz = ones;
330                fpscrMask.dn = ones;
331                fpscrMask.ahp = ones;
332                fpscrMask.qc = ones;
333                fpscrMask.v = ones;
334                fpscrMask.c = ones;
335                fpscrMask.z = ones;
336                fpscrMask.n = ones;
337                newVal = (newVal & (uint32_t)fpscrMask) |
338                         (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
339            }
340            break;
341          case MISCREG_CPSR_Q:
342            {
343                assert(!(newVal & ~CpsrMaskQ));
344                newVal = miscRegs[MISCREG_CPSR] | newVal;
345                misc_reg = MISCREG_CPSR;
346            }
347            break;
348          case MISCREG_FPSCR_QC:
349            {
350                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
351                misc_reg = MISCREG_FPSCR;
352            }
353            break;
354          case MISCREG_FPSCR_EXC:
355            {
356                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
357                misc_reg = MISCREG_FPSCR;
358            }
359            break;
360          case MISCREG_FPEXC:
361            {
362                // vfpv3 architecture, section B.6.1 of DDI04068
363                // bit 29 - valid only if fpexc[31] is 0
364                const uint32_t fpexcMask = 0x60000000;
365                newVal = (newVal & fpexcMask) |
366                         (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
367            }
368            break;
369          case MISCREG_SCTLR:
370            {
371                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
372                SCTLR sctlr = miscRegs[MISCREG_SCTLR];
373                SCTLR new_sctlr = newVal;
374                new_sctlr.nmfi =  (bool)sctlr.nmfi;
375                miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
376                tc->getITBPtr()->invalidateMiscReg();
377                tc->getDTBPtr()->invalidateMiscReg();
378
379                // Check if all CPUs are booted with caches enabled
380                // so we can stop enforcing coherency of some kernel
381                // structures manually.
382                sys = tc->getSystemPtr();
383                for (x = 0; x < sys->numContexts(); x++) {
384                    oc = sys->getThreadContext(x);
385                    SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
386                    if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
387                        return;
388                }
389
390                for (x = 0; x < sys->numContexts(); x++) {
391                    oc = sys->getThreadContext(x);
392                    oc->getDTBPtr()->allCpusCaching();
393                    oc->getITBPtr()->allCpusCaching();
394#if USE_CHECKER
395                    CheckerCPU *checker =
396                        dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
397                    if (checker) {
398                        checker->getDTBPtr()->allCpusCaching();
399                        checker->getITBPtr()->allCpusCaching();
400                    }
401#endif
402                }
403                return;
404            }
405          case MISCREG_TLBTR:
406          case MISCREG_MVFR0:
407          case MISCREG_MVFR1:
408          case MISCREG_MPIDR:
409          case MISCREG_FPSID:
410            return;
411          case MISCREG_TLBIALLIS:
412          case MISCREG_TLBIALL:
413            sys = tc->getSystemPtr();
414            for (x = 0; x < sys->numContexts(); x++) {
415                oc = sys->getThreadContext(x);
416                assert(oc->getITBPtr() && oc->getDTBPtr());
417                oc->getITBPtr()->flushAll();
418                oc->getDTBPtr()->flushAll();
419#if USE_CHECKER
420                CheckerCPU *checker =
421                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
422                if (checker) {
423                    checker->getITBPtr()->flushAll();
424                    checker->getDTBPtr()->flushAll();
425                }
426#endif
427            }
428            return;
429          case MISCREG_ITLBIALL:
430            tc->getITBPtr()->flushAll();
431            return;
432          case MISCREG_DTLBIALL:
433            tc->getDTBPtr()->flushAll();
434            return;
435          case MISCREG_TLBIMVAIS:
436          case MISCREG_TLBIMVA:
437            sys = tc->getSystemPtr();
438            for (x = 0; x < sys->numContexts(); x++) {
439                oc = sys->getThreadContext(x);
440                assert(oc->getITBPtr() && oc->getDTBPtr());
441                oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
442                        bits(newVal, 7,0));
443                oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
444                        bits(newVal, 7,0));
445#if USE_CHECKER
446                CheckerCPU *checker =
447                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
448                if (checker) {
449                    checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
450                            bits(newVal, 7,0));
451                    checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
452                            bits(newVal, 7,0));
453                }
454#endif
455            }
456            return;
457          case MISCREG_TLBIASIDIS:
458          case MISCREG_TLBIASID:
459            sys = tc->getSystemPtr();
460            for (x = 0; x < sys->numContexts(); x++) {
461                oc = sys->getThreadContext(x);
462                assert(oc->getITBPtr() && oc->getDTBPtr());
463                oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
464                oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
465#if USE_CHECKER
466                CheckerCPU *checker =
467                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
468                if (checker) {
469                    checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
470                    checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
471                }
472#endif
473            }
474            return;
475          case MISCREG_TLBIMVAAIS:
476          case MISCREG_TLBIMVAA:
477            sys = tc->getSystemPtr();
478            for (x = 0; x < sys->numContexts(); x++) {
479                oc = sys->getThreadContext(x);
480                assert(oc->getITBPtr() && oc->getDTBPtr());
481                oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
482                oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
483#if USE_CHECKER
484                CheckerCPU *checker =
485                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
486                if (checker) {
487                    checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
488                    checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
489                }
490#endif
491            }
492            return;
493          case MISCREG_ITLBIMVA:
494            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
495                    bits(newVal, 7,0));
496            return;
497          case MISCREG_DTLBIMVA:
498            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
499                    bits(newVal, 7,0));
500            return;
501          case MISCREG_ITLBIASID:
502            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
503            return;
504          case MISCREG_DTLBIASID:
505            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
506            return;
507          case MISCREG_ACTLR:
508            warn("Not doing anything for write of miscreg ACTLR\n");
509            break;
510          case MISCREG_PMCR:
511            {
512              // Performance counters not implemented.  Instead, interpret
513              //   a reset command to this register to reset the simulator
514              //   statistics.
515              // PMCR_E | PMCR_P | PMCR_C
516              const int ResetAndEnableCounters = 0x7;
517              if (newVal == ResetAndEnableCounters) {
518                  inform("Resetting all simobject stats\n");
519                  Stats::schedStatEvent(false, true);
520                  break;
521              }
522            }
523          case MISCREG_PMCCNTR:
524          case MISCREG_PMSELR:
525            warn("Not doing anything for write to miscreg %s\n",
526                    miscRegName[misc_reg]);
527            break;
528          case MISCREG_V2PCWPR:
529          case MISCREG_V2PCWPW:
530          case MISCREG_V2PCWUR:
531          case MISCREG_V2PCWUW:
532          case MISCREG_V2POWPR:
533          case MISCREG_V2POWPW:
534          case MISCREG_V2POWUR:
535          case MISCREG_V2POWUW:
536            {
537              RequestPtr req = new Request;
538              unsigned flags;
539              BaseTLB::Mode mode;
540              Fault fault;
541              switch(misc_reg) {
542                  case MISCREG_V2PCWPR:
543                      flags = TLB::MustBeOne;
544                      mode = BaseTLB::Read;
545                      break;
546                  case MISCREG_V2PCWPW:
547                      flags = TLB::MustBeOne;
548                      mode = BaseTLB::Write;
549                      break;
550                  case MISCREG_V2PCWUR:
551                      flags = TLB::MustBeOne | TLB::UserMode;
552                      mode = BaseTLB::Read;
553                      break;
554                  case MISCREG_V2PCWUW:
555                      flags = TLB::MustBeOne | TLB::UserMode;
556                      mode = BaseTLB::Write;
557                      break;
558                  default:
559                      panic("Security Extensions not implemented!");
560              }
561              warn("Translating via MISCREG in atomic mode! Fix Me!\n");
562              req->setVirt(0, val, 1, flags, tc->pcState().pc(),
563                      Request::funcMasterId);
564              fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
565              if (fault == NoFault) {
566                  miscRegs[MISCREG_PAR] =
567                      (req->getPaddr() & 0xfffff000) |
568                      (tc->getDTBPtr()->getAttr() );
569                  DPRINTF(MiscRegs,
570                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
571                          val, miscRegs[MISCREG_PAR]);
572              }
573              else {
574                  // Set fault bit and FSR
575                  FSR fsr = miscRegs[MISCREG_DFSR];
576                  miscRegs[MISCREG_PAR] =
577                      (fsr.ext << 6) |
578                      (fsr.fsHigh << 5) |
579                      (fsr.fsLow << 1) |
580                      0x1; // F bit
581              }
582              return;
583            }
584          case MISCREG_CONTEXTIDR:
585          case MISCREG_PRRR:
586          case MISCREG_NMRR:
587          case MISCREG_DACR:
588            tc->getITBPtr()->invalidateMiscReg();
589            tc->getDTBPtr()->invalidateMiscReg();
590            break;
591          case MISCREG_CPSR_MODE:
592            // This miscreg is used by copy*Regs to set the CPSR mode
593            // without updating other CPSR variables. It's used to
594            // make sure the register map is in such a state that we can
595            // see all of the registers for the copy.
596            updateRegMap(val);
597            return;
598          case MISCREG_L2CTLR:
599            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
600                 miscRegName[misc_reg], uint32_t(val));
601        }
602    }
603    setMiscRegNoEffect(misc_reg, newVal);
604}
605
606}
607