isa.cc revision 8549
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "debug/Arm.hh" 43#include "debug/MiscRegs.hh" 44#include "sim/faults.hh" 45#include "sim/stat_control.hh" 46#include "sim/system.hh" 47 48namespace ArmISA 49{ 50 51void 52ISA::clear() 53{ 54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 55 uint32_t midr = miscRegs[MISCREG_MIDR]; 56 memset(miscRegs, 0, sizeof(miscRegs)); 57 CPSR cpsr = 0; 58 cpsr.mode = MODE_USER; 59 miscRegs[MISCREG_CPSR] = cpsr; 60 updateRegMap(cpsr); 61 62 SCTLR sctlr = 0; 63 sctlr.te = (bool)sctlr_rst.te; 64 sctlr.nmfi = (bool)sctlr_rst.nmfi; 65 sctlr.v = (bool)sctlr_rst.v; 66 sctlr.u = 1; 67 sctlr.xp = 1; 68 sctlr.rao2 = 1; 69 sctlr.rao3 = 1; 70 sctlr.rao4 = 1; 71 miscRegs[MISCREG_SCTLR] = sctlr; 72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 73 74 // Preserve MIDR accross reset 75 miscRegs[MISCREG_MIDR] = midr; 76 77 /* Start with an event in the mailbox */ 78 miscRegs[MISCREG_SEV_MAILBOX] = 1; 79 80 // Separate Instruction and Data TLBs. 81 miscRegs[MISCREG_TLBTR] = 1; 82 83 MVFR0 mvfr0 = 0; 84 mvfr0.advSimdRegisters = 2; 85 mvfr0.singlePrecision = 2; 86 mvfr0.doublePrecision = 2; 87 mvfr0.vfpExceptionTrapping = 0; 88 mvfr0.divide = 1; 89 mvfr0.squareRoot = 1; 90 mvfr0.shortVectors = 1; 91 mvfr0.roundingModes = 1; 92 miscRegs[MISCREG_MVFR0] = mvfr0; 93 94 MVFR1 mvfr1 = 0; 95 mvfr1.flushToZero = 1; 96 mvfr1.defaultNaN = 1; 97 mvfr1.advSimdLoadStore = 1; 98 mvfr1.advSimdInteger = 1; 99 mvfr1.advSimdSinglePrecision = 1; 100 mvfr1.advSimdHalfPrecision = 1; 101 mvfr1.vfpHalfPrecision = 1; 102 miscRegs[MISCREG_MVFR1] = mvfr1; 103 104 miscRegs[MISCREG_MPIDR] = 0; 105 106 // Reset values of PRRR and NMRR are implementation dependent 107 108 miscRegs[MISCREG_PRRR] = 109 (1 << 19) | // 19 110 (0 << 18) | // 18 111 (0 << 17) | // 17 112 (1 << 16) | // 16 113 (2 << 14) | // 15:14 114 (0 << 12) | // 13:12 115 (2 << 10) | // 11:10 116 (2 << 8) | // 9:8 117 (2 << 6) | // 7:6 118 (2 << 4) | // 5:4 119 (1 << 2) | // 3:2 120 0; // 1:0 121 miscRegs[MISCREG_NMRR] = 122 (1 << 30) | // 31:30 123 (0 << 26) | // 27:26 124 (0 << 24) | // 25:24 125 (3 << 22) | // 23:22 126 (2 << 20) | // 21:20 127 (0 << 18) | // 19:18 128 (0 << 16) | // 17:16 129 (1 << 14) | // 15:14 130 (0 << 12) | // 13:12 131 (2 << 10) | // 11:10 132 (0 << 8) | // 9:8 133 (3 << 6) | // 7:6 134 (2 << 4) | // 5:4 135 (0 << 2) | // 3:2 136 0; // 1:0 137 138 miscRegs[MISCREG_CPACR] = 0; 139 miscRegs[MISCREG_FPSID] = 0x410430A0; 140 141 // See section B4.1.84 of ARM ARM 142 // All values are latest for ARMv7-A profile 143 miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 144 miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 145 miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 146 miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 147 miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 148 miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 149 150 //XXX We need to initialize the rest of the state. 151} 152 153MiscReg 154ISA::readMiscRegNoEffect(int misc_reg) 155{ 156 assert(misc_reg < NumMiscRegs); 157 158 int flat_idx; 159 if (misc_reg == MISCREG_SPSR) 160 flat_idx = flattenMiscIndex(misc_reg); 161 else 162 flat_idx = misc_reg; 163 MiscReg val = miscRegs[flat_idx]; 164 165 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 166 misc_reg, flat_idx, val); 167 return val; 168} 169 170 171MiscReg 172ISA::readMiscReg(int misc_reg, ThreadContext *tc) 173{ 174 if (misc_reg == MISCREG_CPSR) { 175 CPSR cpsr = miscRegs[misc_reg]; 176 PCState pc = tc->pcState(); 177 cpsr.j = pc.jazelle() ? 1 : 0; 178 cpsr.t = pc.thumb() ? 1 : 0; 179 return cpsr; 180 } 181 if (misc_reg >= MISCREG_CP15_UNIMP_START) 182 panic("Unimplemented CP15 register %s read.\n", 183 miscRegName[misc_reg]); 184 185 switch (misc_reg) { 186 case MISCREG_MPIDR: 187 return tc->cpuId(); 188 break; 189 case MISCREG_ID_MMFR0: 190 return 0x03; // VMSAv7 support 191 case MISCREG_ID_MMFR2: 192 return 0x01230000; // no HW access | WFI stalling | ISB and DSB 193 // | all TLB maintenance | no Harvard 194 case MISCREG_ID_MMFR3: 195 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 196 // BP Maint | Cache Maint Set/way | Cache Maint MVA 197 case MISCREG_CLIDR: 198 warn_once("The clidr register always reports 0 caches.\n"); 199 warn_once("clidr LoUIS field of 0b001 to match current " 200 "ARM implementations.\n"); 201 return 0x00200000; 202 case MISCREG_CCSIDR: 203 warn_once("The ccsidr register isn't implemented and " 204 "always reads as 0.\n"); 205 break; 206 case MISCREG_ID_PFR0: 207 warn("Returning thumbEE disabled for now since we don't support CP14" 208 "config registers and jumping to ThumbEE vectors\n"); 209 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 210 case MISCREG_ID_PFR1: 211 warn("reading unimplmented register ID_PFR1"); 212 return 0; 213 case MISCREG_CTR: 214 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 215 case MISCREG_ACTLR: 216 warn("Not doing anything for miscreg ACTLR\n"); 217 break; 218 case MISCREG_PMCR: 219 case MISCREG_PMCCNTR: 220 case MISCREG_PMSELR: 221 warn("Not doing anything for read to miscreg %s\n", 222 miscRegName[misc_reg]); 223 break; 224 case MISCREG_CPSR_Q: 225 panic("shouldn't be reading this register seperately\n"); 226 case MISCREG_FPSCR_QC: 227 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 228 case MISCREG_FPSCR_EXC: 229 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 230 case MISCREG_L2CTLR: 231 // mostly unimplemented, just set NumCPUs field from sim and return 232 L2CTLR l2ctlr = 0; 233 // b00:1CPU to b11:4CPUs 234 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 235 return l2ctlr; 236 } 237 return readMiscRegNoEffect(misc_reg); 238} 239 240void 241ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 242{ 243 assert(misc_reg < NumMiscRegs); 244 245 int flat_idx; 246 if (misc_reg == MISCREG_SPSR) 247 flat_idx = flattenMiscIndex(misc_reg); 248 else 249 flat_idx = misc_reg; 250 miscRegs[flat_idx] = val; 251 252 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 253 flat_idx, val); 254} 255 256void 257ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 258{ 259 260 MiscReg newVal = val; 261 int x; 262 System *sys; 263 ThreadContext *oc; 264 265 if (misc_reg == MISCREG_CPSR) { 266 updateRegMap(val); 267 268 269 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 270 int old_mode = old_cpsr.mode; 271 CPSR cpsr = val; 272 if (old_mode != cpsr.mode) { 273 tc->getITBPtr()->invalidateMiscReg(); 274 tc->getDTBPtr()->invalidateMiscReg(); 275 } 276 277 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 278 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 279 PCState pc = tc->pcState(); 280 pc.nextThumb(cpsr.t); 281 pc.nextJazelle(cpsr.j); 282 tc->pcState(pc); 283 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 284 misc_reg < MISCREG_CP15_END) { 285 panic("Unimplemented CP15 register %s wrote with %#x.\n", 286 miscRegName[misc_reg], val); 287 } else { 288 switch (misc_reg) { 289 case MISCREG_CPACR: 290 { 291 292 const uint32_t ones = (uint32_t)(-1); 293 CPACR cpacrMask = 0; 294 // Only cp10, cp11, and ase are implemented, nothing else should 295 // be writable 296 cpacrMask.cp10 = ones; 297 cpacrMask.cp11 = ones; 298 cpacrMask.asedis = ones; 299 newVal &= cpacrMask; 300 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 301 miscRegName[misc_reg], newVal); 302 } 303 break; 304 case MISCREG_CSSELR: 305 warn_once("The csselr register isn't implemented.\n"); 306 return; 307 case MISCREG_FPSCR: 308 { 309 const uint32_t ones = (uint32_t)(-1); 310 FPSCR fpscrMask = 0; 311 fpscrMask.ioc = ones; 312 fpscrMask.dzc = ones; 313 fpscrMask.ofc = ones; 314 fpscrMask.ufc = ones; 315 fpscrMask.ixc = ones; 316 fpscrMask.idc = ones; 317 fpscrMask.len = ones; 318 fpscrMask.stride = ones; 319 fpscrMask.rMode = ones; 320 fpscrMask.fz = ones; 321 fpscrMask.dn = ones; 322 fpscrMask.ahp = ones; 323 fpscrMask.qc = ones; 324 fpscrMask.v = ones; 325 fpscrMask.c = ones; 326 fpscrMask.z = ones; 327 fpscrMask.n = ones; 328 newVal = (newVal & (uint32_t)fpscrMask) | 329 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 330 } 331 break; 332 case MISCREG_CPSR_Q: 333 { 334 assert(!(newVal & ~CpsrMaskQ)); 335 newVal = miscRegs[MISCREG_CPSR] | newVal; 336 misc_reg = MISCREG_CPSR; 337 } 338 break; 339 case MISCREG_FPSCR_QC: 340 { 341 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 342 misc_reg = MISCREG_FPSCR; 343 } 344 break; 345 case MISCREG_FPSCR_EXC: 346 { 347 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 348 misc_reg = MISCREG_FPSCR; 349 } 350 break; 351 case MISCREG_FPEXC: 352 { 353 // vfpv3 architecture, section B.6.1 of DDI04068 354 // bit 29 - valid only if fpexc[31] is 0 355 const uint32_t fpexcMask = 0x60000000; 356 newVal = (newVal & fpexcMask) | 357 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 358 } 359 break; 360 case MISCREG_SCTLR: 361 { 362 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 363 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 364 SCTLR new_sctlr = newVal; 365 new_sctlr.nmfi = (bool)sctlr.nmfi; 366 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 367 tc->getITBPtr()->invalidateMiscReg(); 368 tc->getDTBPtr()->invalidateMiscReg(); 369 370 // Check if all CPUs are booted with caches enabled 371 // so we can stop enforcing coherency of some kernel 372 // structures manually. 373 sys = tc->getSystemPtr(); 374 for (x = 0; x < sys->numContexts(); x++) { 375 oc = sys->getThreadContext(x); 376 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 377 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 378 return; 379 } 380 381 for (x = 0; x < sys->numContexts(); x++) { 382 oc = sys->getThreadContext(x); 383 oc->getDTBPtr()->allCpusCaching(); 384 oc->getITBPtr()->allCpusCaching(); 385 } 386 return; 387 } 388 case MISCREG_TLBTR: 389 case MISCREG_MVFR0: 390 case MISCREG_MVFR1: 391 case MISCREG_MPIDR: 392 case MISCREG_FPSID: 393 return; 394 case MISCREG_TLBIALLIS: 395 case MISCREG_TLBIALL: 396 sys = tc->getSystemPtr(); 397 for (x = 0; x < sys->numContexts(); x++) { 398 oc = sys->getThreadContext(x); 399 assert(oc->getITBPtr() && oc->getDTBPtr()); 400 oc->getITBPtr()->flushAll(); 401 oc->getDTBPtr()->flushAll(); 402 } 403 return; 404 case MISCREG_ITLBIALL: 405 tc->getITBPtr()->flushAll(); 406 return; 407 case MISCREG_DTLBIALL: 408 tc->getDTBPtr()->flushAll(); 409 return; 410 case MISCREG_TLBIMVAIS: 411 case MISCREG_TLBIMVA: 412 sys = tc->getSystemPtr(); 413 for (x = 0; x < sys->numContexts(); x++) { 414 oc = sys->getThreadContext(x); 415 assert(oc->getITBPtr() && oc->getDTBPtr()); 416 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 417 bits(newVal, 7,0)); 418 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 419 bits(newVal, 7,0)); 420 } 421 return; 422 case MISCREG_TLBIASIDIS: 423 case MISCREG_TLBIASID: 424 sys = tc->getSystemPtr(); 425 for (x = 0; x < sys->numContexts(); x++) { 426 oc = sys->getThreadContext(x); 427 assert(oc->getITBPtr() && oc->getDTBPtr()); 428 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 429 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 430 } 431 return; 432 case MISCREG_TLBIMVAAIS: 433 case MISCREG_TLBIMVAA: 434 sys = tc->getSystemPtr(); 435 for (x = 0; x < sys->numContexts(); x++) { 436 oc = sys->getThreadContext(x); 437 assert(oc->getITBPtr() && oc->getDTBPtr()); 438 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 439 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 440 } 441 return; 442 case MISCREG_ITLBIMVA: 443 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 444 bits(newVal, 7,0)); 445 return; 446 case MISCREG_DTLBIMVA: 447 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 448 bits(newVal, 7,0)); 449 return; 450 case MISCREG_ITLBIASID: 451 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 452 return; 453 case MISCREG_DTLBIASID: 454 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 455 return; 456 case MISCREG_ACTLR: 457 warn("Not doing anything for write of miscreg ACTLR\n"); 458 break; 459 case MISCREG_PMCR: 460 { 461 // Performance counters not implemented. Instead, interpret 462 // a reset command to this register to reset the simulator 463 // statistics. 464 // PMCR_E | PMCR_P | PMCR_C 465 const int ResetAndEnableCounters = 0x7; 466 if (newVal == ResetAndEnableCounters) { 467 inform("Resetting all simobject stats\n"); 468 Stats::schedStatEvent(false, true); 469 break; 470 } 471 } 472 case MISCREG_PMCCNTR: 473 case MISCREG_PMSELR: 474 warn("Not doing anything for write to miscreg %s\n", 475 miscRegName[misc_reg]); 476 break; 477 case MISCREG_V2PCWPR: 478 case MISCREG_V2PCWPW: 479 case MISCREG_V2PCWUR: 480 case MISCREG_V2PCWUW: 481 case MISCREG_V2POWPR: 482 case MISCREG_V2POWPW: 483 case MISCREG_V2POWUR: 484 case MISCREG_V2POWUW: 485 { 486 RequestPtr req = new Request; 487 unsigned flags; 488 BaseTLB::Mode mode; 489 Fault fault; 490 switch(misc_reg) { 491 case MISCREG_V2PCWPR: 492 flags = TLB::MustBeOne; 493 mode = BaseTLB::Read; 494 break; 495 case MISCREG_V2PCWPW: 496 flags = TLB::MustBeOne; 497 mode = BaseTLB::Write; 498 break; 499 case MISCREG_V2PCWUR: 500 flags = TLB::MustBeOne | TLB::UserMode; 501 mode = BaseTLB::Read; 502 break; 503 case MISCREG_V2PCWUW: 504 flags = TLB::MustBeOne | TLB::UserMode; 505 mode = BaseTLB::Write; 506 break; 507 default: 508 panic("Security Extensions not implemented!"); 509 } 510 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 511 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 512 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 513 if (fault == NoFault) { 514 miscRegs[MISCREG_PAR] = 515 (req->getPaddr() & 0xfffff000) | 516 (tc->getDTBPtr()->getAttr() ); 517 DPRINTF(MiscRegs, 518 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 519 val, miscRegs[MISCREG_PAR]); 520 } 521 else { 522 // Set fault bit and FSR 523 FSR fsr = miscRegs[MISCREG_DFSR]; 524 miscRegs[MISCREG_PAR] = 525 (fsr.ext << 6) | 526 (fsr.fsHigh << 5) | 527 (fsr.fsLow << 1) | 528 0x1; // F bit 529 } 530 return; 531 } 532 case MISCREG_CONTEXTIDR: 533 case MISCREG_PRRR: 534 case MISCREG_NMRR: 535 case MISCREG_DACR: 536 tc->getITBPtr()->invalidateMiscReg(); 537 tc->getDTBPtr()->invalidateMiscReg(); 538 break; 539 case MISCREG_CPSR_MODE: 540 // This miscreg is used by copy*Regs to set the CPSR mode 541 // without updating other CPSR variables. It's used to 542 // make sure the register map is in such a state that we can 543 // see all of the registers for the copy. 544 updateRegMap(val); 545 return; 546 case MISCREG_L2CTLR: 547 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 548 miscRegName[misc_reg], uint32_t(val)); 549 } 550 } 551 setMiscRegNoEffect(misc_reg, newVal); 552} 553 554} 555