isa.cc revision 8302
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "debug/Arm.hh" 43#include "debug/MiscRegs.hh" 44#include "sim/faults.hh" 45#include "sim/stat_control.hh" 46#include "sim/system.hh" 47 48namespace ArmISA 49{ 50 51void 52ISA::clear() 53{ 54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 55 uint32_t midr = miscRegs[MISCREG_MIDR]; 56 memset(miscRegs, 0, sizeof(miscRegs)); 57 CPSR cpsr = 0; 58 cpsr.mode = MODE_USER; 59 miscRegs[MISCREG_CPSR] = cpsr; 60 updateRegMap(cpsr); 61 62 SCTLR sctlr = 0; 63 sctlr.te = (bool)sctlr_rst.te; 64 sctlr.nmfi = (bool)sctlr_rst.nmfi; 65 sctlr.v = (bool)sctlr_rst.v; 66 sctlr.u = 1; 67 sctlr.xp = 1; 68 sctlr.rao2 = 1; 69 sctlr.rao3 = 1; 70 sctlr.rao4 = 1; 71 miscRegs[MISCREG_SCTLR] = sctlr; 72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 73 74 // Preserve MIDR accross reset 75 miscRegs[MISCREG_MIDR] = midr; 76 77 /* Start with an event in the mailbox */ 78 miscRegs[MISCREG_SEV_MAILBOX] = 1; 79 80 // Separate Instruction and Data TLBs. 81 miscRegs[MISCREG_TLBTR] = 1; 82 83 MVFR0 mvfr0 = 0; 84 mvfr0.advSimdRegisters = 2; 85 mvfr0.singlePrecision = 2; 86 mvfr0.doublePrecision = 2; 87 mvfr0.vfpExceptionTrapping = 0; 88 mvfr0.divide = 1; 89 mvfr0.squareRoot = 1; 90 mvfr0.shortVectors = 1; 91 mvfr0.roundingModes = 1; 92 miscRegs[MISCREG_MVFR0] = mvfr0; 93 94 MVFR1 mvfr1 = 0; 95 mvfr1.flushToZero = 1; 96 mvfr1.defaultNaN = 1; 97 mvfr1.advSimdLoadStore = 1; 98 mvfr1.advSimdInteger = 1; 99 mvfr1.advSimdSinglePrecision = 1; 100 mvfr1.advSimdHalfPrecision = 1; 101 mvfr1.vfpHalfPrecision = 1; 102 miscRegs[MISCREG_MVFR1] = mvfr1; 103 104 miscRegs[MISCREG_MPIDR] = 0; 105 106 // Reset values of PRRR and NMRR are implementation dependent 107 108 miscRegs[MISCREG_PRRR] = 109 (1 << 19) | // 19 110 (0 << 18) | // 18 111 (0 << 17) | // 17 112 (1 << 16) | // 16 113 (2 << 14) | // 15:14 114 (0 << 12) | // 13:12 115 (2 << 10) | // 11:10 116 (2 << 8) | // 9:8 117 (2 << 6) | // 7:6 118 (2 << 4) | // 5:4 119 (1 << 2) | // 3:2 120 0; // 1:0 121 miscRegs[MISCREG_NMRR] = 122 (1 << 30) | // 31:30 123 (0 << 26) | // 27:26 124 (0 << 24) | // 25:24 125 (3 << 22) | // 23:22 126 (2 << 20) | // 21:20 127 (0 << 18) | // 19:18 128 (0 << 16) | // 17:16 129 (1 << 14) | // 15:14 130 (0 << 12) | // 13:12 131 (2 << 10) | // 11:10 132 (0 << 8) | // 9:8 133 (3 << 6) | // 7:6 134 (2 << 4) | // 5:4 135 (0 << 2) | // 3:2 136 0; // 1:0 137 138 miscRegs[MISCREG_CPACR] = 0; 139 miscRegs[MISCREG_FPSID] = 0x410430A0; 140 141 // See section B4.1.84 of ARM ARM 142 // All values are latest for ARMv7-A profile 143 miscRegs[MISCREG_ID_ISAR0] = 0x01101111; 144 miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 145 miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 146 miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 147 miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 148 miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 149 150 //XXX We need to initialize the rest of the state. 151} 152 153MiscReg 154ISA::readMiscRegNoEffect(int misc_reg) 155{ 156 assert(misc_reg < NumMiscRegs); 157 158 int flat_idx; 159 if (misc_reg == MISCREG_SPSR) 160 flat_idx = flattenMiscIndex(misc_reg); 161 else 162 flat_idx = misc_reg; 163 MiscReg val = miscRegs[flat_idx]; 164 165 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 166 misc_reg, flat_idx, val); 167 return val; 168} 169 170 171MiscReg 172ISA::readMiscReg(int misc_reg, ThreadContext *tc) 173{ 174 if (misc_reg == MISCREG_CPSR) { 175 CPSR cpsr = miscRegs[misc_reg]; 176 PCState pc = tc->pcState(); 177 cpsr.j = pc.jazelle() ? 1 : 0; 178 cpsr.t = pc.thumb() ? 1 : 0; 179 return cpsr; 180 } 181 if (misc_reg >= MISCREG_CP15_UNIMP_START) 182 panic("Unimplemented CP15 register %s read.\n", 183 miscRegName[misc_reg]); 184 185 switch (misc_reg) { 186 case MISCREG_MPIDR: 187 return tc->cpuId(); 188 break; 189 case MISCREG_ID_MMFR3: 190 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 191 // BP Maint | Cache Maint Set/way | Cache Maint MVA 192 case MISCREG_CLIDR: 193 warn_once("The clidr register always reports 0 caches.\n"); 194 break; 195 case MISCREG_CCSIDR: 196 warn_once("The ccsidr register isn't implemented and " 197 "always reads as 0.\n"); 198 break; 199 case MISCREG_ID_PFR0: 200 warn("Returning thumbEE disabled for now since we don't support CP14" 201 "config registers and jumping to ThumbEE vectors\n"); 202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 203 case MISCREG_ID_PFR1: 204 warn("reading unimplmented register ID_PFR1"); 205 return 0; 206 case MISCREG_ID_MMFR0: 207 return 0x03; //VMSAz7 208 case MISCREG_CTR: 209 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 210 case MISCREG_ACTLR: 211 warn("Not doing anything for miscreg ACTLR\n"); 212 break; 213 case MISCREG_PMCR: 214 case MISCREG_PMCCNTR: 215 case MISCREG_PMSELR: 216 warn("Not doing anything for read to miscreg %s\n", 217 miscRegName[misc_reg]); 218 break; 219 case MISCREG_CPSR_Q: 220 panic("shouldn't be reading this register seperately\n"); 221 case MISCREG_FPSCR_QC: 222 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 223 case MISCREG_FPSCR_EXC: 224 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 225 } 226 return readMiscRegNoEffect(misc_reg); 227} 228 229void 230ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 231{ 232 assert(misc_reg < NumMiscRegs); 233 234 int flat_idx; 235 if (misc_reg == MISCREG_SPSR) 236 flat_idx = flattenMiscIndex(misc_reg); 237 else 238 flat_idx = misc_reg; 239 miscRegs[flat_idx] = val; 240 241 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 242 flat_idx, val); 243} 244 245void 246ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 247{ 248 249 MiscReg newVal = val; 250 int x; 251 System *sys; 252 ThreadContext *oc; 253 254 if (misc_reg == MISCREG_CPSR) { 255 updateRegMap(val); 256 257 258 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 259 int old_mode = old_cpsr.mode; 260 CPSR cpsr = val; 261 if (old_mode != cpsr.mode) { 262 tc->getITBPtr()->invalidateMiscReg(); 263 tc->getDTBPtr()->invalidateMiscReg(); 264 } 265 266 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 267 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 268 PCState pc = tc->pcState(); 269 pc.nextThumb(cpsr.t); 270 pc.nextJazelle(cpsr.j); 271 tc->pcState(pc); 272 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 273 misc_reg < MISCREG_CP15_END) { 274 panic("Unimplemented CP15 register %s wrote with %#x.\n", 275 miscRegName[misc_reg], val); 276 } else { 277 switch (misc_reg) { 278 case MISCREG_CPACR: 279 { 280 281 const uint32_t ones = (uint32_t)(-1); 282 CPACR cpacrMask = 0; 283 // Only cp10, cp11, and ase are implemented, nothing else should 284 // be writable 285 cpacrMask.cp10 = ones; 286 cpacrMask.cp11 = ones; 287 cpacrMask.asedis = ones; 288 newVal &= cpacrMask; 289 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 290 miscRegName[misc_reg], newVal); 291 } 292 break; 293 case MISCREG_CSSELR: 294 warn_once("The csselr register isn't implemented.\n"); 295 return; 296 case MISCREG_FPSCR: 297 { 298 const uint32_t ones = (uint32_t)(-1); 299 FPSCR fpscrMask = 0; 300 fpscrMask.ioc = ones; 301 fpscrMask.dzc = ones; 302 fpscrMask.ofc = ones; 303 fpscrMask.ufc = ones; 304 fpscrMask.ixc = ones; 305 fpscrMask.idc = ones; 306 fpscrMask.len = ones; 307 fpscrMask.stride = ones; 308 fpscrMask.rMode = ones; 309 fpscrMask.fz = ones; 310 fpscrMask.dn = ones; 311 fpscrMask.ahp = ones; 312 fpscrMask.qc = ones; 313 fpscrMask.v = ones; 314 fpscrMask.c = ones; 315 fpscrMask.z = ones; 316 fpscrMask.n = ones; 317 newVal = (newVal & (uint32_t)fpscrMask) | 318 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 319 } 320 break; 321 case MISCREG_CPSR_Q: 322 { 323 assert(!(newVal & ~CpsrMaskQ)); 324 newVal = miscRegs[MISCREG_CPSR] | newVal; 325 misc_reg = MISCREG_CPSR; 326 } 327 break; 328 case MISCREG_FPSCR_QC: 329 { 330 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 331 misc_reg = MISCREG_FPSCR; 332 } 333 break; 334 case MISCREG_FPSCR_EXC: 335 { 336 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 337 misc_reg = MISCREG_FPSCR; 338 } 339 break; 340 case MISCREG_FPEXC: 341 { 342 // vfpv3 architecture, section B.6.1 of DDI04068 343 // bit 29 - valid only if fpexc[31] is 0 344 const uint32_t fpexcMask = 0x60000000; 345 newVal = (newVal & fpexcMask) | 346 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 347 } 348 break; 349 case MISCREG_SCTLR: 350 { 351 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 352 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 353 SCTLR new_sctlr = newVal; 354 new_sctlr.nmfi = (bool)sctlr.nmfi; 355 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 356 tc->getITBPtr()->invalidateMiscReg(); 357 tc->getDTBPtr()->invalidateMiscReg(); 358 return; 359 } 360 case MISCREG_TLBTR: 361 case MISCREG_MVFR0: 362 case MISCREG_MVFR1: 363 case MISCREG_MPIDR: 364 case MISCREG_FPSID: 365 return; 366 case MISCREG_TLBIALLIS: 367 case MISCREG_TLBIALL: 368 sys = tc->getSystemPtr(); 369 for (x = 0; x < sys->numContexts(); x++) { 370 oc = sys->getThreadContext(x); 371 assert(oc->getITBPtr() && oc->getDTBPtr()); 372 oc->getITBPtr()->flushAll(); 373 oc->getDTBPtr()->flushAll(); 374 } 375 return; 376 case MISCREG_ITLBIALL: 377 tc->getITBPtr()->flushAll(); 378 return; 379 case MISCREG_DTLBIALL: 380 tc->getDTBPtr()->flushAll(); 381 return; 382 case MISCREG_TLBIMVAIS: 383 case MISCREG_TLBIMVA: 384 sys = tc->getSystemPtr(); 385 for (x = 0; x < sys->numContexts(); x++) { 386 oc = sys->getThreadContext(x); 387 assert(oc->getITBPtr() && oc->getDTBPtr()); 388 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 389 bits(newVal, 7,0)); 390 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 391 bits(newVal, 7,0)); 392 } 393 return; 394 case MISCREG_TLBIASIDIS: 395 case MISCREG_TLBIASID: 396 sys = tc->getSystemPtr(); 397 for (x = 0; x < sys->numContexts(); x++) { 398 oc = sys->getThreadContext(x); 399 assert(oc->getITBPtr() && oc->getDTBPtr()); 400 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 401 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 402 } 403 return; 404 case MISCREG_TLBIMVAAIS: 405 case MISCREG_TLBIMVAA: 406 sys = tc->getSystemPtr(); 407 for (x = 0; x < sys->numContexts(); x++) { 408 oc = sys->getThreadContext(x); 409 assert(oc->getITBPtr() && oc->getDTBPtr()); 410 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 411 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 412 } 413 return; 414 case MISCREG_ITLBIMVA: 415 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 416 bits(newVal, 7,0)); 417 return; 418 case MISCREG_DTLBIMVA: 419 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 420 bits(newVal, 7,0)); 421 return; 422 case MISCREG_ITLBIASID: 423 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 424 return; 425 case MISCREG_DTLBIASID: 426 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 427 return; 428 case MISCREG_ACTLR: 429 warn("Not doing anything for write of miscreg ACTLR\n"); 430 break; 431 case MISCREG_PMCR: 432 { 433 // Performance counters not implemented. Instead, interpret 434 // a reset command to this register to reset the simulator 435 // statistics. 436 // PMCR_E | PMCR_P | PMCR_C 437 const int ResetAndEnableCounters = 0x7; 438 if (newVal == ResetAndEnableCounters) { 439 inform("Resetting all simobject stats\n"); 440 Stats::schedStatEvent(false, true); 441 break; 442 } 443 } 444 case MISCREG_PMCCNTR: 445 case MISCREG_PMSELR: 446 warn("Not doing anything for write to miscreg %s\n", 447 miscRegName[misc_reg]); 448 break; 449 case MISCREG_V2PCWPR: 450 case MISCREG_V2PCWPW: 451 case MISCREG_V2PCWUR: 452 case MISCREG_V2PCWUW: 453 case MISCREG_V2POWPR: 454 case MISCREG_V2POWPW: 455 case MISCREG_V2POWUR: 456 case MISCREG_V2POWUW: 457 { 458 RequestPtr req = new Request; 459 unsigned flags; 460 BaseTLB::Mode mode; 461 Fault fault; 462 switch(misc_reg) { 463 case MISCREG_V2PCWPR: 464 flags = TLB::MustBeOne; 465 mode = BaseTLB::Read; 466 break; 467 case MISCREG_V2PCWPW: 468 flags = TLB::MustBeOne; 469 mode = BaseTLB::Write; 470 break; 471 case MISCREG_V2PCWUR: 472 flags = TLB::MustBeOne | TLB::UserMode; 473 mode = BaseTLB::Read; 474 break; 475 case MISCREG_V2PCWUW: 476 flags = TLB::MustBeOne | TLB::UserMode; 477 mode = BaseTLB::Write; 478 break; 479 default: 480 panic("Security Extensions not implemented!"); 481 } 482 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 483 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 484 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 485 if (fault == NoFault) { 486 miscRegs[MISCREG_PAR] = 487 (req->getPaddr() & 0xfffff000) | 488 (tc->getDTBPtr()->getAttr() ); 489 DPRINTF(MiscRegs, 490 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 491 val, miscRegs[MISCREG_PAR]); 492 } 493 else { 494 // Set fault bit and FSR 495 FSR fsr = miscRegs[MISCREG_DFSR]; 496 miscRegs[MISCREG_PAR] = 497 (fsr.ext << 6) | 498 (fsr.fsHigh << 5) | 499 (fsr.fsLow << 1) | 500 0x1; // F bit 501 } 502 return; 503 } 504 case MISCREG_CONTEXTIDR: 505 case MISCREG_PRRR: 506 case MISCREG_NMRR: 507 case MISCREG_DACR: 508 tc->getITBPtr()->invalidateMiscReg(); 509 tc->getDTBPtr()->invalidateMiscReg(); 510 break; 511 case MISCREG_CPSR_MODE: 512 // This miscreg is used by copy*Regs to set the CPSR mode 513 // without updating other CPSR variables. It's used to 514 // make sure the register map is in such a state that we can 515 // see all of the registers for the copy. 516 updateRegMap(val); 517 return; 518 } 519 } 520 setMiscRegNoEffect(misc_reg, newVal); 521} 522 523} 524