isa.cc revision 8232
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "debug/Arm.hh"
43#include "debug/MiscRegs.hh"
44#include "sim/faults.hh"
45#include "sim/stat_control.hh"
46
47namespace ArmISA
48{
49
50void
51ISA::clear()
52{
53    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
54
55    memset(miscRegs, 0, sizeof(miscRegs));
56    CPSR cpsr = 0;
57    cpsr.mode = MODE_USER;
58    miscRegs[MISCREG_CPSR] = cpsr;
59    updateRegMap(cpsr);
60
61    SCTLR sctlr = 0;
62    sctlr.te = (bool)sctlr_rst.te;
63    sctlr.nmfi = (bool)sctlr_rst.nmfi;
64    sctlr.v = (bool)sctlr_rst.v;
65    sctlr.u    = 1;
66    sctlr.xp = 1;
67    sctlr.rao2 = 1;
68    sctlr.rao3 = 1;
69    sctlr.rao4 = 1;
70    miscRegs[MISCREG_SCTLR] = sctlr;
71    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
72
73    /* Start with an event in the mailbox */
74    miscRegs[MISCREG_SEV_MAILBOX] = 1;
75
76    /*
77     * Implemented = '5' from "M5",
78     * Variant = 0,
79     */
80    miscRegs[MISCREG_MIDR] =
81        (0x35 << 24) | // Implementor is '5' from "M5"
82        (0 << 20)    | // Variant
83        (0xf << 16)  | // Architecture from CPUID scheme
84        (0xf00 << 4) | // Primary part number
85        (0 << 0)     | // Revision
86        0;
87
88    // Separate Instruction and Data TLBs.
89    miscRegs[MISCREG_TLBTR] = 1;
90
91    MVFR0 mvfr0 = 0;
92    mvfr0.advSimdRegisters = 2;
93    mvfr0.singlePrecision = 2;
94    mvfr0.doublePrecision = 2;
95    mvfr0.vfpExceptionTrapping = 0;
96    mvfr0.divide = 1;
97    mvfr0.squareRoot = 1;
98    mvfr0.shortVectors = 1;
99    mvfr0.roundingModes = 1;
100    miscRegs[MISCREG_MVFR0] = mvfr0;
101
102    MVFR1 mvfr1 = 0;
103    mvfr1.flushToZero = 1;
104    mvfr1.defaultNaN = 1;
105    mvfr1.advSimdLoadStore = 1;
106    mvfr1.advSimdInteger = 1;
107    mvfr1.advSimdSinglePrecision = 1;
108    mvfr1.advSimdHalfPrecision = 1;
109    mvfr1.vfpHalfPrecision = 1;
110    miscRegs[MISCREG_MVFR1] = mvfr1;
111
112    miscRegs[MISCREG_MPIDR] = 0;
113
114    // Reset values of PRRR and NMRR are implementation dependent
115
116    miscRegs[MISCREG_PRRR] =
117        (1 << 19) | // 19
118        (0 << 18) | // 18
119        (0 << 17) | // 17
120        (1 << 16) | // 16
121        (2 << 14) | // 15:14
122        (0 << 12) | // 13:12
123        (2 << 10) | // 11:10
124        (2 << 8)  | // 9:8
125        (2 << 6)  | // 7:6
126        (2 << 4)  | // 5:4
127        (1 << 2)  | // 3:2
128        0;          // 1:0
129    miscRegs[MISCREG_NMRR] =
130        (1 << 30) | // 31:30
131        (0 << 26) | // 27:26
132        (0 << 24) | // 25:24
133        (3 << 22) | // 23:22
134        (2 << 20) | // 21:20
135        (0 << 18) | // 19:18
136        (0 << 16) | // 17:16
137        (1 << 14) | // 15:14
138        (0 << 12) | // 13:12
139        (2 << 10) | // 11:10
140        (0 << 8)  | // 9:8
141        (3 << 6)  | // 7:6
142        (2 << 4)  | // 5:4
143        (0 << 2)  | // 3:2
144        0;          // 1:0
145
146    miscRegs[MISCREG_CPACR] = 0;
147    miscRegs[MISCREG_FPSID] = 0x410430A0;
148
149    // See section B4.1.84 of ARM ARM
150    // All values are latest for ARMv7-A profile
151    miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
152    miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
153    miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
154    miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
155    miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
156    miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
157
158    //XXX We need to initialize the rest of the state.
159}
160
161MiscReg
162ISA::readMiscRegNoEffect(int misc_reg)
163{
164    assert(misc_reg < NumMiscRegs);
165
166    int flat_idx;
167    if (misc_reg == MISCREG_SPSR)
168        flat_idx = flattenMiscIndex(misc_reg);
169    else
170        flat_idx = misc_reg;
171    MiscReg val = miscRegs[flat_idx];
172
173    DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
174            misc_reg, flat_idx, val);
175    return val;
176}
177
178
179MiscReg
180ISA::readMiscReg(int misc_reg, ThreadContext *tc)
181{
182    if (misc_reg == MISCREG_CPSR) {
183        CPSR cpsr = miscRegs[misc_reg];
184        PCState pc = tc->pcState();
185        cpsr.j = pc.jazelle() ? 1 : 0;
186        cpsr.t = pc.thumb() ? 1 : 0;
187        return cpsr;
188    }
189    if (misc_reg >= MISCREG_CP15_UNIMP_START)
190        panic("Unimplemented CP15 register %s read.\n",
191              miscRegName[misc_reg]);
192
193    switch (misc_reg) {
194      case MISCREG_CLIDR:
195        warn_once("The clidr register always reports 0 caches.\n");
196        break;
197      case MISCREG_CCSIDR:
198        warn_once("The ccsidr register isn't implemented and "
199                "always reads as 0.\n");
200        break;
201      case MISCREG_ID_PFR0:
202        warn("Returning thumbEE disabled for now since we don't support CP14"
203             "config registers and jumping to ThumbEE vectors\n");
204        return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
205      case MISCREG_ID_MMFR0:
206        return 0x03; //VMSAz7
207      case MISCREG_CTR:
208        return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
209      case MISCREG_ACTLR:
210        warn("Not doing anything for miscreg ACTLR\n");
211        break;
212      case MISCREG_PMCR:
213      case MISCREG_PMCCNTR:
214      case MISCREG_PMSELR:
215        warn("Not doing anyhting for read to miscreg %s\n",
216                miscRegName[misc_reg]);
217        break;
218      case MISCREG_FPSCR_QC:
219        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
220      case MISCREG_FPSCR_EXC:
221        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
222    }
223    return readMiscRegNoEffect(misc_reg);
224}
225
226void
227ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
228{
229    assert(misc_reg < NumMiscRegs);
230
231    int flat_idx;
232    if (misc_reg == MISCREG_SPSR)
233        flat_idx = flattenMiscIndex(misc_reg);
234    else
235        flat_idx = misc_reg;
236    miscRegs[flat_idx] = val;
237
238    DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
239            flat_idx, val);
240}
241
242void
243ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
244{
245
246    MiscReg newVal = val;
247    if (misc_reg == MISCREG_CPSR) {
248        updateRegMap(val);
249
250
251        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
252        int old_mode = old_cpsr.mode;
253        CPSR cpsr = val;
254        if (old_mode != cpsr.mode) {
255            tc->getITBPtr()->invalidateMiscReg();
256            tc->getDTBPtr()->invalidateMiscReg();
257        }
258
259        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
260                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
261        PCState pc = tc->pcState();
262        pc.nextThumb(cpsr.t);
263        pc.nextJazelle(cpsr.j);
264        tc->pcState(pc);
265    } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
266        misc_reg < MISCREG_CP15_END) {
267        panic("Unimplemented CP15 register %s wrote with %#x.\n",
268              miscRegName[misc_reg], val);
269    } else {
270        switch (misc_reg) {
271          case MISCREG_CPACR:
272            {
273
274                const uint32_t ones = (uint32_t)(-1);
275                CPACR cpacrMask = 0;
276                // Only cp10, cp11, and ase are implemented, nothing else should
277                // be writable
278                cpacrMask.cp10 = ones;
279                cpacrMask.cp11 = ones;
280                cpacrMask.asedis = ones;
281                newVal &= cpacrMask;
282                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
283                        miscRegName[misc_reg], newVal);
284            }
285            break;
286          case MISCREG_CSSELR:
287            warn_once("The csselr register isn't implemented.\n");
288            return;
289          case MISCREG_FPSCR:
290            {
291                const uint32_t ones = (uint32_t)(-1);
292                FPSCR fpscrMask = 0;
293                fpscrMask.ioc = ones;
294                fpscrMask.dzc = ones;
295                fpscrMask.ofc = ones;
296                fpscrMask.ufc = ones;
297                fpscrMask.ixc = ones;
298                fpscrMask.idc = ones;
299                fpscrMask.len = ones;
300                fpscrMask.stride = ones;
301                fpscrMask.rMode = ones;
302                fpscrMask.fz = ones;
303                fpscrMask.dn = ones;
304                fpscrMask.ahp = ones;
305                fpscrMask.qc = ones;
306                fpscrMask.v = ones;
307                fpscrMask.c = ones;
308                fpscrMask.z = ones;
309                fpscrMask.n = ones;
310                newVal = (newVal & (uint32_t)fpscrMask) |
311                         (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
312            }
313            break;
314          case MISCREG_FPSCR_QC:
315            {
316                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
317                misc_reg = MISCREG_FPSCR;
318            }
319            break;
320          case MISCREG_FPSCR_EXC:
321            {
322                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
323                misc_reg = MISCREG_FPSCR;
324            }
325            break;
326          case MISCREG_FPEXC:
327            {
328                // vfpv3 architecture, section B.6.1 of DDI04068
329                // bit 29 - valid only if fpexc[31] is 0
330                const uint32_t fpexcMask = 0x60000000;
331                newVal = (newVal & fpexcMask) |
332                         (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
333            }
334            break;
335          case MISCREG_SCTLR:
336            {
337                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
338                SCTLR sctlr = miscRegs[MISCREG_SCTLR];
339                SCTLR new_sctlr = newVal;
340                new_sctlr.nmfi =  (bool)sctlr.nmfi;
341                miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
342                tc->getITBPtr()->invalidateMiscReg();
343                tc->getDTBPtr()->invalidateMiscReg();
344                return;
345            }
346          case MISCREG_TLBTR:
347          case MISCREG_MVFR0:
348          case MISCREG_MVFR1:
349          case MISCREG_MPIDR:
350          case MISCREG_FPSID:
351            return;
352          case MISCREG_TLBIALLIS:
353          case MISCREG_TLBIALL:
354            warn_once("Need to flush all TLBs in MP\n");
355            tc->getITBPtr()->flushAll();
356            tc->getDTBPtr()->flushAll();
357            return;
358          case MISCREG_ITLBIALL:
359            tc->getITBPtr()->flushAll();
360            return;
361          case MISCREG_DTLBIALL:
362            tc->getDTBPtr()->flushAll();
363            return;
364          case MISCREG_TLBIMVAIS:
365          case MISCREG_TLBIMVA:
366            warn_once("Need to flush all TLBs in MP\n");
367            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
368                    bits(newVal, 7,0));
369            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
370                    bits(newVal, 7,0));
371            return;
372          case MISCREG_TLBIASIDIS:
373          case MISCREG_TLBIASID:
374            warn_once("Need to flush all TLBs in MP\n");
375            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
376            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
377            return;
378          case MISCREG_TLBIMVAAIS:
379          case MISCREG_TLBIMVAA:
380            warn_once("Need to flush all TLBs in MP\n");
381            tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
382            tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
383            return;
384          case MISCREG_ITLBIMVA:
385            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
386                    bits(newVal, 7,0));
387            return;
388          case MISCREG_DTLBIMVA:
389            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
390                    bits(newVal, 7,0));
391            return;
392          case MISCREG_ITLBIASID:
393            tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
394            return;
395          case MISCREG_DTLBIASID:
396            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
397            return;
398          case MISCREG_ACTLR:
399            warn("Not doing anything for write of miscreg ACTLR\n");
400            break;
401          case MISCREG_PMCR:
402            {
403              // Performance counters not implemented.  Instead, interpret
404              //   a reset command to this register to reset the simulator
405              //   statistics.
406              // PMCR_E | PMCR_P | PMCR_C
407              const int ResetAndEnableCounters = 0x7;
408              if (newVal == ResetAndEnableCounters) {
409                  inform("Resetting all simobject stats\n");
410                  Stats::schedStatEvent(false, true);
411                  break;
412              }
413            }
414          case MISCREG_PMCCNTR:
415          case MISCREG_PMSELR:
416            warn("Not doing anything for write to miscreg %s\n",
417                    miscRegName[misc_reg]);
418            break;
419          case MISCREG_V2PCWPR:
420          case MISCREG_V2PCWPW:
421          case MISCREG_V2PCWUR:
422          case MISCREG_V2PCWUW:
423          case MISCREG_V2POWPR:
424          case MISCREG_V2POWPW:
425          case MISCREG_V2POWUR:
426          case MISCREG_V2POWUW:
427            {
428              RequestPtr req = new Request;
429              unsigned flags;
430              BaseTLB::Mode mode;
431              Fault fault;
432              switch(misc_reg) {
433                  case MISCREG_V2PCWPR:
434                      flags = TLB::MustBeOne;
435                      mode = BaseTLB::Read;
436                      break;
437                  case MISCREG_V2PCWPW:
438                      flags = TLB::MustBeOne;
439                      mode = BaseTLB::Write;
440                      break;
441                  case MISCREG_V2PCWUR:
442                      flags = TLB::MustBeOne | TLB::UserMode;
443                      mode = BaseTLB::Read;
444                      break;
445                  case MISCREG_V2PCWUW:
446                      flags = TLB::MustBeOne | TLB::UserMode;
447                      mode = BaseTLB::Write;
448                      break;
449                  default:
450                      panic("Security Extensions not implemented!");
451              }
452              warn("Translating via MISCREG in atomic mode! Fix Me!\n");
453              req->setVirt(0, val, 1, flags, tc->pcState().pc());
454              fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
455              if (fault == NoFault) {
456                  miscRegs[MISCREG_PAR] =
457                      (req->getPaddr() & 0xfffff000) |
458                      (tc->getDTBPtr()->getAttr() );
459                  DPRINTF(MiscRegs,
460                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
461                          val, miscRegs[MISCREG_PAR]);
462              }
463              else {
464                  // Set fault bit and FSR
465                  FSR fsr = miscRegs[MISCREG_DFSR];
466                  miscRegs[MISCREG_PAR] =
467                      (fsr.ext << 6) |
468                      (fsr.fsHigh << 5) |
469                      (fsr.fsLow << 1) |
470                      0x1; // F bit
471              }
472              return;
473            }
474          case MISCREG_CONTEXTIDR:
475          case MISCREG_PRRR:
476          case MISCREG_NMRR:
477          case MISCREG_DACR:
478            tc->getITBPtr()->invalidateMiscReg();
479            tc->getDTBPtr()->invalidateMiscReg();
480            break;
481          case MISCREG_CPSR_MODE:
482            // This miscreg is used by copy*Regs to set the CPSR mode
483            // without updating other CPSR variables. It's used to
484            // make sure the register map is in such a state that we can
485            // see all of the registers for the copy.
486            updateRegMap(val);
487            return;
488        }
489    }
490    setMiscRegNoEffect(misc_reg, newVal);
491}
492
493}
494