isa.cc revision 7749
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "sim/faults.hh" 43 44namespace ArmISA 45{ 46 47void 48ISA::clear() 49{ 50 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 51 52 memset(miscRegs, 0, sizeof(miscRegs)); 53 CPSR cpsr = 0; 54 cpsr.mode = MODE_USER; 55 miscRegs[MISCREG_CPSR] = cpsr; 56 updateRegMap(cpsr); 57 58 SCTLR sctlr = 0; 59 sctlr.te = (bool)sctlr_rst.te; 60 sctlr.nmfi = (bool)sctlr_rst.nmfi; 61 sctlr.v = (bool)sctlr_rst.v; 62 sctlr.u = 1; 63 sctlr.xp = 1; 64 sctlr.rao2 = 1; 65 sctlr.rao3 = 1; 66 sctlr.rao4 = 1; 67 miscRegs[MISCREG_SCTLR] = sctlr; 68 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 69 70 /* Start with an event in the mailbox */ 71 miscRegs[MISCREG_SEV_MAILBOX] = 1; 72 73 /* 74 * Implemented = '5' from "M5", 75 * Variant = 0, 76 */ 77 miscRegs[MISCREG_MIDR] = 78 (0x35 << 24) | // Implementor is '5' from "M5" 79 (0 << 20) | // Variant 80 (0xf << 16) | // Architecture from CPUID scheme 81 (0xf00 << 4) | // Primary part number 82 (0 << 0) | // Revision 83 0; 84 85 // Separate Instruction and Data TLBs. 86 miscRegs[MISCREG_TLBTR] = 1; 87 88 MVFR0 mvfr0 = 0; 89 mvfr0.advSimdRegisters = 2; 90 mvfr0.singlePrecision = 2; 91 mvfr0.doublePrecision = 2; 92 mvfr0.vfpExceptionTrapping = 0; 93 mvfr0.divide = 1; 94 mvfr0.squareRoot = 1; 95 mvfr0.shortVectors = 1; 96 mvfr0.roundingModes = 1; 97 miscRegs[MISCREG_MVFR0] = mvfr0; 98 99 MVFR1 mvfr1 = 0; 100 mvfr1.flushToZero = 1; 101 mvfr1.defaultNaN = 1; 102 mvfr1.advSimdLoadStore = 1; 103 mvfr1.advSimdInteger = 1; 104 mvfr1.advSimdSinglePrecision = 1; 105 mvfr1.advSimdHalfPrecision = 1; 106 mvfr1.vfpHalfPrecision = 1; 107 miscRegs[MISCREG_MVFR1] = mvfr1; 108 109 miscRegs[MISCREG_MPIDR] = 0; 110 111 // Reset values of PRRR and NMRR are implementation dependent 112 113 miscRegs[MISCREG_PRRR] = 114 (1 << 19) | // 19 115 (0 << 18) | // 18 116 (0 << 17) | // 17 117 (1 << 16) | // 16 118 (2 << 14) | // 15:14 119 (0 << 12) | // 13:12 120 (2 << 10) | // 11:10 121 (2 << 8) | // 9:8 122 (2 << 6) | // 7:6 123 (2 << 4) | // 5:4 124 (1 << 2) | // 3:2 125 0; // 1:0 126 miscRegs[MISCREG_NMRR] = 127 (1 << 30) | // 31:30 128 (0 << 26) | // 27:26 129 (0 << 24) | // 25:24 130 (3 << 22) | // 23:22 131 (2 << 20) | // 21:20 132 (0 << 18) | // 19:18 133 (0 << 16) | // 17:16 134 (1 << 14) | // 15:14 135 (0 << 12) | // 13:12 136 (2 << 10) | // 11:10 137 (0 << 8) | // 9:8 138 (3 << 6) | // 7:6 139 (2 << 4) | // 5:4 140 (0 << 2) | // 3:2 141 0; // 1:0 142 143 miscRegs[MISCREG_CPACR] = 0; 144 miscRegs[MISCREG_FPSID] = 0x410430A0; 145 //XXX We need to initialize the rest of the state. 146} 147 148MiscReg 149ISA::readMiscRegNoEffect(int misc_reg) 150{ 151 assert(misc_reg < NumMiscRegs); 152 153 int flat_idx; 154 if (misc_reg == MISCREG_SPSR) 155 flat_idx = flattenMiscIndex(misc_reg); 156 else 157 flat_idx = misc_reg; 158 MiscReg val = miscRegs[flat_idx]; 159 160 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 161 misc_reg, flat_idx, val); 162 return val; 163} 164 165 166MiscReg 167ISA::readMiscReg(int misc_reg, ThreadContext *tc) 168{ 169 if (misc_reg == MISCREG_CPSR) { 170 CPSR cpsr = miscRegs[misc_reg]; 171 PCState pc = tc->pcState(); 172 cpsr.j = pc.jazelle() ? 1 : 0; 173 cpsr.t = pc.thumb() ? 1 : 0; 174 return cpsr; 175 } 176 if (misc_reg >= MISCREG_CP15_UNIMP_START && 177 misc_reg < MISCREG_CP15_END) { 178 panic("Unimplemented CP15 register %s read.\n", 179 miscRegName[misc_reg]); 180 } 181 switch (misc_reg) { 182 case MISCREG_CLIDR: 183 warn_once("The clidr register always reports 0 caches.\n"); 184 break; 185 case MISCREG_CCSIDR: 186 warn_once("The ccsidr register isn't implemented and " 187 "always reads as 0.\n"); 188 break; 189 case MISCREG_ID_PFR0: 190 warn("Returning thumbEE disabled for now since we don't support CP14" 191 "config registers and jumping to ThumbEE vectors\n"); 192 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 193 case MISCREG_ID_MMFR0: 194 return 0x03; //VMSAz7 195 case MISCREG_CTR: 196 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 197 case MISCREG_ACTLR: 198 warn("Not doing anything for miscreg ACTLR\n"); 199 break; 200 case MISCREG_PMCR: 201 case MISCREG_PMCCNTR: 202 case MISCREG_PMSELR: 203 warn("Not doing anyhting for read to miscreg %s\n", 204 miscRegName[misc_reg]); 205 break; 206 207 } 208 return readMiscRegNoEffect(misc_reg); 209} 210 211void 212ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 213{ 214 assert(misc_reg < NumMiscRegs); 215 216 int flat_idx; 217 if (misc_reg == MISCREG_SPSR) 218 flat_idx = flattenMiscIndex(misc_reg); 219 else 220 flat_idx = misc_reg; 221 miscRegs[flat_idx] = val; 222 223 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 224 flat_idx, val); 225} 226 227void 228ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 229{ 230 231 MiscReg newVal = val; 232 if (misc_reg == MISCREG_CPSR) { 233 updateRegMap(val); 234 235 236 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 237 int old_mode = old_cpsr.mode; 238 CPSR cpsr = val; 239 if (old_mode != cpsr.mode) { 240 tc->getITBPtr()->invalidateMiscReg(); 241 tc->getDTBPtr()->invalidateMiscReg(); 242 } 243 244 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 245 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 246 PCState pc = tc->pcState(); 247 pc.nextThumb(cpsr.t); 248 pc.nextJazelle(cpsr.j); 249 tc->pcState(pc); 250 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 251 misc_reg < MISCREG_CP15_END) { 252 panic("Unimplemented CP15 register %s wrote with %#x.\n", 253 miscRegName[misc_reg], val); 254 } else { 255 switch (misc_reg) { 256 case MISCREG_ITSTATE: 257 { 258 ITSTATE itstate = newVal; 259 CPSR cpsr = miscRegs[MISCREG_CPSR]; 260 cpsr.it1 = itstate.bottom2; 261 cpsr.it2 = itstate.top6; 262 miscRegs[MISCREG_CPSR] = cpsr; 263 DPRINTF(MiscRegs, 264 "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 265 (uint8_t)itstate, (uint32_t)cpsr); 266 } 267 break; 268 case MISCREG_CPACR: 269 { 270 CPACR newCpacr = 0; 271 CPACR valCpacr = val; 272 newCpacr.cp10 = valCpacr.cp10; 273 newCpacr.cp11 = valCpacr.cp11; 274 //XXX d32dis isn't implemented. The manual says whether or not 275 //it works is implementation defined. 276 newCpacr.asedis = valCpacr.asedis; 277 newVal = newCpacr; 278 } 279 break; 280 case MISCREG_CSSELR: 281 warn_once("The csselr register isn't implemented.\n"); 282 break; 283 case MISCREG_FPSCR: 284 { 285 const uint32_t ones = (uint32_t)(-1); 286 FPSCR fpscrMask = 0; 287 fpscrMask.ioc = ones; 288 fpscrMask.dzc = ones; 289 fpscrMask.ofc = ones; 290 fpscrMask.ufc = ones; 291 fpscrMask.ixc = ones; 292 fpscrMask.idc = ones; 293 fpscrMask.len = ones; 294 fpscrMask.stride = ones; 295 fpscrMask.rMode = ones; 296 fpscrMask.fz = ones; 297 fpscrMask.dn = ones; 298 fpscrMask.ahp = ones; 299 fpscrMask.qc = ones; 300 fpscrMask.v = ones; 301 fpscrMask.c = ones; 302 fpscrMask.z = ones; 303 fpscrMask.n = ones; 304 newVal = (newVal & (uint32_t)fpscrMask) | 305 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 306 } 307 break; 308 case MISCREG_FPEXC: 309 { 310 const uint32_t fpexcMask = 0x60000000; 311 newVal = (newVal & fpexcMask) | 312 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 313 } 314 break; 315 case MISCREG_SCTLR: 316 { 317 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 318 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 319 SCTLR new_sctlr = newVal; 320 new_sctlr.nmfi = (bool)sctlr.nmfi; 321 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 322 tc->getITBPtr()->invalidateMiscReg(); 323 tc->getDTBPtr()->invalidateMiscReg(); 324 return; 325 } 326 case MISCREG_TLBTR: 327 case MISCREG_MVFR0: 328 case MISCREG_MVFR1: 329 case MISCREG_MPIDR: 330 case MISCREG_FPSID: 331 return; 332 case MISCREG_TLBIALLIS: 333 case MISCREG_TLBIALL: 334 warn_once("Need to flush all TLBs in MP\n"); 335 tc->getITBPtr()->flushAll(); 336 tc->getDTBPtr()->flushAll(); 337 return; 338 case MISCREG_ITLBIALL: 339 tc->getITBPtr()->flushAll(); 340 return; 341 case MISCREG_DTLBIALL: 342 tc->getDTBPtr()->flushAll(); 343 return; 344 case MISCREG_TLBIMVAIS: 345 case MISCREG_TLBIMVA: 346 warn_once("Need to flush all TLBs in MP\n"); 347 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 348 bits(newVal, 7,0)); 349 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 350 bits(newVal, 7,0)); 351 return; 352 case MISCREG_TLBIASIDIS: 353 case MISCREG_TLBIASID: 354 warn_once("Need to flush all TLBs in MP\n"); 355 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 356 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 357 return; 358 case MISCREG_TLBIMVAAIS: 359 case MISCREG_TLBIMVAA: 360 warn_once("Need to flush all TLBs in MP\n"); 361 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 362 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 363 return; 364 case MISCREG_ITLBIMVA: 365 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 366 bits(newVal, 7,0)); 367 return; 368 case MISCREG_DTLBIMVA: 369 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 370 bits(newVal, 7,0)); 371 return; 372 case MISCREG_ITLBIASID: 373 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 374 return; 375 case MISCREG_DTLBIASID: 376 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 377 return; 378 case MISCREG_ACTLR: 379 warn("Not doing anything for write of miscreg ACTLR\n"); 380 break; 381 case MISCREG_PMCR: 382 case MISCREG_PMCCNTR: 383 case MISCREG_PMSELR: 384 warn("Not doing anything for write to miscreg %s\n", 385 miscRegName[misc_reg]); 386 break; 387 case MISCREG_V2PCWPR: 388 case MISCREG_V2PCWPW: 389 case MISCREG_V2PCWUR: 390 case MISCREG_V2PCWUW: 391 case MISCREG_V2POWPR: 392 case MISCREG_V2POWPW: 393 case MISCREG_V2POWUR: 394 case MISCREG_V2POWUW: 395 { 396 RequestPtr req = new Request; 397 unsigned flags; 398 BaseTLB::Mode mode; 399 Fault fault; 400 switch(misc_reg) { 401 case MISCREG_V2PCWPR: 402 flags = TLB::MustBeOne; 403 mode = BaseTLB::Read; 404 break; 405 case MISCREG_V2PCWPW: 406 flags = TLB::MustBeOne; 407 mode = BaseTLB::Write; 408 break; 409 case MISCREG_V2PCWUR: 410 flags = TLB::MustBeOne | TLB::UserMode; 411 mode = BaseTLB::Read; 412 break; 413 case MISCREG_V2PCWUW: 414 flags = TLB::MustBeOne | TLB::UserMode; 415 mode = BaseTLB::Write; 416 break; 417 default: 418 panic("Security Extensions not implemented!"); 419 } 420 req->setVirt(0, val, 1, flags, tc->pcState().pc()); 421 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 422 if (fault == NoFault) { 423 miscRegs[MISCREG_PAR] = 424 (req->getPaddr() & 0xfffff000) | 425 (tc->getDTBPtr()->getAttr() ); 426 DPRINTF(MiscRegs, 427 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 428 val, miscRegs[MISCREG_PAR]); 429 } 430 else { 431 // Set fault bit and FSR 432 FSR fsr = miscRegs[MISCREG_DFSR]; 433 miscRegs[MISCREG_PAR] = 434 (fsr.ext << 6) | 435 (fsr.fsHigh << 5) | 436 (fsr.fsLow << 1) | 437 0x1; // F bit 438 } 439 return; 440 } 441 case MISCREG_CONTEXTIDR: 442 case MISCREG_PRRR: 443 case MISCREG_NMRR: 444 case MISCREG_DACR: 445 tc->getITBPtr()->invalidateMiscReg(); 446 tc->getDTBPtr()->invalidateMiscReg(); 447 break; 448 449 } 450 } 451 setMiscRegNoEffect(misc_reg, newVal); 452} 453 454} 455