isa.cc revision 7640
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42 43namespace ArmISA 44{ 45 46void 47ISA::clear() 48{ 49 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 50 51 memset(miscRegs, 0, sizeof(miscRegs)); 52 CPSR cpsr = 0; 53 cpsr.mode = MODE_USER; 54 miscRegs[MISCREG_CPSR] = cpsr; 55 updateRegMap(cpsr); 56 57 SCTLR sctlr = 0; 58 sctlr.te = (bool)sctlr_rst.te; 59 sctlr.nmfi = (bool)sctlr_rst.nmfi; 60 sctlr.v = (bool)sctlr_rst.v; 61 sctlr.u = 1; 62 sctlr.xp = 1; 63 sctlr.rao2 = 1; 64 sctlr.rao3 = 1; 65 sctlr.rao4 = 1; 66 miscRegs[MISCREG_SCTLR] = sctlr; 67 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 68 69 /* Start with an event in the mailbox */ 70 miscRegs[MISCREG_SEV_MAILBOX] = 1; 71 72 /* 73 * Implemented = '5' from "M5", 74 * Variant = 0, 75 */ 76 miscRegs[MISCREG_MIDR] = 77 (0x35 << 24) | //Implementor is '5' from "M5" 78 (0 << 20) | //Variant 79 (0xf << 16) | //Architecture from CPUID scheme 80 (0 << 4) | //Primary part number 81 (0 << 0) | //Revision 82 0; 83 84 // Separate Instruction and Data TLBs. 85 miscRegs[MISCREG_TLBTR] = 1; 86 87 MVFR0 mvfr0 = 0; 88 mvfr0.advSimdRegisters = 2; 89 mvfr0.singlePrecision = 2; 90 mvfr0.doublePrecision = 2; 91 mvfr0.vfpExceptionTrapping = 0; 92 mvfr0.divide = 1; 93 mvfr0.squareRoot = 1; 94 mvfr0.shortVectors = 1; 95 mvfr0.roundingModes = 1; 96 miscRegs[MISCREG_MVFR0] = mvfr0; 97 98 MVFR1 mvfr1 = 0; 99 mvfr1.flushToZero = 1; 100 mvfr1.defaultNaN = 1; 101 mvfr1.advSimdLoadStore = 1; 102 mvfr1.advSimdInteger = 1; 103 mvfr1.advSimdSinglePrecision = 1; 104 mvfr1.advSimdHalfPrecision = 1; 105 mvfr1.vfpHalfPrecision = 1; 106 miscRegs[MISCREG_MVFR1] = mvfr1; 107 108 miscRegs[MISCREG_MPIDR] = 0; 109 110 // Reset values of PRRR and NMRR are implementation dependent 111 112 miscRegs[MISCREG_PRRR] = 113 (1 << 19) | // 19 114 (0 << 18) | // 18 115 (0 << 17) | // 17 116 (1 << 16) | // 16 117 (2 << 14) | // 15:14 118 (0 << 12) | // 13:12 119 (2 << 10) | // 11:10 120 (2 << 8) | // 9:8 121 (2 << 6) | // 7:6 122 (2 << 4) | // 5:4 123 (1 << 2) | // 3:2 124 0; // 1:0 125 miscRegs[MISCREG_NMRR] = 126 (1 << 30) | // 31:30 127 (0 << 26) | // 27:26 128 (0 << 24) | // 25:24 129 (3 << 22) | // 23:22 130 (2 << 20) | // 21:20 131 (0 << 18) | // 19:18 132 (0 << 16) | // 17:16 133 (1 << 14) | // 15:14 134 (0 << 12) | // 13:12 135 (2 << 10) | // 11:10 136 (0 << 8) | // 9:8 137 (3 << 6) | // 7:6 138 (2 << 4) | // 5:4 139 (0 << 2) | // 3:2 140 0; // 1:0 141 142 //XXX We need to initialize the rest of the state. 143} 144 145MiscReg 146ISA::readMiscRegNoEffect(int misc_reg) 147{ 148 assert(misc_reg < NumMiscRegs); 149 150 int flat_idx; 151 if (misc_reg == MISCREG_SPSR) 152 flat_idx = flattenMiscIndex(misc_reg); 153 else 154 flat_idx = misc_reg; 155 MiscReg val = miscRegs[flat_idx]; 156 157 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 158 misc_reg, flat_idx, val); 159 return val; 160} 161 162 163MiscReg 164ISA::readMiscReg(int misc_reg, ThreadContext *tc) 165{ 166 if (misc_reg == MISCREG_CPSR) { 167 CPSR cpsr = miscRegs[misc_reg]; 168 Addr pc = tc->readPC(); 169 if (pc & (ULL(1) << PcJBitShift)) 170 cpsr.j = 1; 171 else 172 cpsr.j = 0; 173 if (pc & (ULL(1) << PcTBitShift)) 174 cpsr.t = 1; 175 else 176 cpsr.t = 0; 177 return cpsr; 178 } 179 if (misc_reg >= MISCREG_CP15_UNIMP_START && 180 misc_reg < MISCREG_CP15_END) { 181 panic("Unimplemented CP15 register %s read.\n", 182 miscRegName[misc_reg]); 183 } 184 switch (misc_reg) { 185 case MISCREG_CLIDR: 186 warn("The clidr register always reports 0 caches.\n"); 187 break; 188 case MISCREG_CCSIDR: 189 warn("The ccsidr register isn't implemented and " 190 "always reads as 0.\n"); 191 break; 192 case MISCREG_ID_PFR0: 193 warn("Returning thumbEE disabled for now since we don't support CP14" 194 "config registers and jumping to ThumbEE vectors\n"); 195 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 196 case MISCREG_ID_MMFR0: 197 return 0x03; //VMSAz7 198 case MISCREG_CTR: 199 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 200 case MISCREG_ACTLR: 201 warn("Not doing anything for miscreg ACTLR\n"); 202 break; 203 case MISCREG_PMCR: 204 case MISCREG_PMCCNTR: 205 case MISCREG_PMSELR: 206 warn("Not doing anyhting for read to miscreg %s\n", 207 miscRegName[misc_reg]); 208 break; 209 210 } 211 return readMiscRegNoEffect(misc_reg); 212} 213 214void 215ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 216{ 217 assert(misc_reg < NumMiscRegs); 218 219 int flat_idx; 220 if (misc_reg == MISCREG_SPSR) 221 flat_idx = flattenMiscIndex(misc_reg); 222 else 223 flat_idx = misc_reg; 224 miscRegs[flat_idx] = val; 225 226 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 227 flat_idx, val); 228} 229 230void 231ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 232{ 233 MiscReg newVal = val; 234 if (misc_reg == MISCREG_CPSR) { 235 updateRegMap(val); 236 CPSR cpsr = val; 237 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 238 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 239 Addr npc = tc->readNextPC() & ~PcModeMask; 240 if (cpsr.j) 241 npc = npc | (ULL(1) << PcJBitShift); 242 if (cpsr.t) 243 npc = npc | (ULL(1) << PcTBitShift); 244 245 tc->setNextPC(npc); 246 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 247 misc_reg < MISCREG_CP15_END) { 248 panic("Unimplemented CP15 register %s wrote with %#x.\n", 249 miscRegName[misc_reg], val); 250 } else { 251 switch (misc_reg) { 252 case MISCREG_ITSTATE: 253 { 254 ITSTATE itstate = newVal; 255 CPSR cpsr = miscRegs[MISCREG_CPSR]; 256 cpsr.it1 = itstate.bottom2; 257 cpsr.it2 = itstate.top6; 258 miscRegs[MISCREG_CPSR] = cpsr; 259 DPRINTF(MiscRegs, 260 "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 261 (uint8_t)itstate, (uint32_t)cpsr); 262 } 263 break; 264 case MISCREG_CPACR: 265 { 266 CPACR newCpacr = 0; 267 CPACR valCpacr = val; 268 newCpacr.cp10 = valCpacr.cp10; 269 newCpacr.cp11 = valCpacr.cp11; 270 //XXX d32dis isn't implemented. The manual says whether or not 271 //it works is implementation defined. 272 newCpacr.asedis = valCpacr.asedis; 273 newVal = newCpacr; 274 } 275 break; 276 case MISCREG_CSSELR: 277 warn("The csselr register isn't implemented.\n"); 278 break; 279 case MISCREG_FPSCR: 280 { 281 const uint32_t ones = (uint32_t)(-1); 282 FPSCR fpscrMask = 0; 283 fpscrMask.ioc = ones; 284 fpscrMask.dzc = ones; 285 fpscrMask.ofc = ones; 286 fpscrMask.ufc = ones; 287 fpscrMask.ixc = ones; 288 fpscrMask.idc = ones; 289 fpscrMask.len = ones; 290 fpscrMask.stride = ones; 291 fpscrMask.rMode = ones; 292 fpscrMask.fz = ones; 293 fpscrMask.dn = ones; 294 fpscrMask.ahp = ones; 295 fpscrMask.qc = ones; 296 fpscrMask.v = ones; 297 fpscrMask.c = ones; 298 fpscrMask.z = ones; 299 fpscrMask.n = ones; 300 newVal = (newVal & (uint32_t)fpscrMask) | 301 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 302 } 303 break; 304 case MISCREG_FPEXC: 305 { 306 const uint32_t fpexcMask = 0x60000000; 307 newVal = (newVal & fpexcMask) | 308 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 309 } 310 break; 311 case MISCREG_SCTLR: 312 { 313 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 314 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 315 SCTLR new_sctlr = newVal; 316 new_sctlr.nmfi = (bool)sctlr.nmfi; 317 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 318 return; 319 } 320 case MISCREG_TLBTR: 321 case MISCREG_MVFR0: 322 case MISCREG_MVFR1: 323 case MISCREG_MPIDR: 324 case MISCREG_FPSID: 325 return; 326 case MISCREG_TLBIALLIS: 327 case MISCREG_TLBIALL: 328 warn("Need to flush all TLBs in MP\n"); 329 tc->getITBPtr()->flushAll(); 330 tc->getDTBPtr()->flushAll(); 331 return; 332 case MISCREG_ITLBIALL: 333 tc->getITBPtr()->flushAll(); 334 return; 335 case MISCREG_DTLBIALL: 336 tc->getDTBPtr()->flushAll(); 337 return; 338 case MISCREG_TLBIMVAIS: 339 case MISCREG_TLBIMVA: 340 warn("Need to flush all TLBs in MP\n"); 341 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 342 bits(newVal, 7,0)); 343 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 344 bits(newVal, 7,0)); 345 return; 346 case MISCREG_TLBIASIDIS: 347 case MISCREG_TLBIASID: 348 warn("Need to flush all TLBs in MP\n"); 349 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 350 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 351 return; 352 case MISCREG_TLBIMVAAIS: 353 case MISCREG_TLBIMVAA: 354 warn("Need to flush all TLBs in MP\n"); 355 tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 356 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 357 return; 358 case MISCREG_ITLBIMVA: 359 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 360 bits(newVal, 7,0)); 361 return; 362 case MISCREG_DTLBIMVA: 363 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 364 bits(newVal, 7,0)); 365 return; 366 case MISCREG_ITLBIASID: 367 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 368 return; 369 case MISCREG_DTLBIASID: 370 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 371 return; 372 case MISCREG_ACTLR: 373 warn("Not doing anything for write of miscreg ACTLR\n"); 374 break; 375 case MISCREG_PMCR: 376 case MISCREG_PMCCNTR: 377 case MISCREG_PMSELR: 378 warn("Not doing anything for write to miscreg %s\n", 379 miscRegName[misc_reg]); 380 break; 381 case MISCREG_V2PCWPR: 382 case MISCREG_V2PCWPW: 383 case MISCREG_V2PCWUR: 384 case MISCREG_V2PCWUW: 385 case MISCREG_V2POWPR: 386 case MISCREG_V2POWPW: 387 case MISCREG_V2POWUR: 388 case MISCREG_V2POWUW: 389 { 390 RequestPtr req = new Request; 391 unsigned flags; 392 BaseTLB::Mode mode; 393 Fault fault; 394 switch(misc_reg) { 395 case MISCREG_V2PCWPR: 396 flags = TLB::MustBeOne; 397 mode = BaseTLB::Read; 398 break; 399 case MISCREG_V2PCWPW: 400 flags = TLB::MustBeOne; 401 mode = BaseTLB::Write; 402 break; 403 case MISCREG_V2PCWUR: 404 flags = TLB::MustBeOne | TLB::UserMode; 405 mode = BaseTLB::Read; 406 break; 407 case MISCREG_V2PCWUW: 408 flags = TLB::MustBeOne | TLB::UserMode; 409 mode = BaseTLB::Write; 410 break; 411 default: 412 panic("Security Extensions not implemented!"); 413 } 414 req->setVirt(0, val, 1, flags, tc->readPC()); 415 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 416 if (fault == NoFault) { 417 miscRegs[MISCREG_PAR] = 418 (req->getPaddr() & 0xfffff000) | 419 (tc->getDTBPtr()->getAttr() ); 420 DPRINTF(MiscRegs, 421 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 422 val, miscRegs[MISCREG_PAR]); 423 } 424 else { 425 // Set fault bit and FSR 426 FSR fsr = miscRegs[MISCREG_DFSR]; 427 miscRegs[MISCREG_PAR] = 428 (fsr.ext << 6) | 429 (fsr.fsHigh << 5) | 430 (fsr.fsLow << 1) | 431 0x1; // F bit 432 } 433 return; 434 } 435 } 436 } 437 setMiscRegNoEffect(misc_reg, newVal); 438} 439 440} 441