isa.cc revision 11772
1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers alias with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 65 */ 66const struct ISA::MiscRegInitializerEntry 67 ISA::MiscRegSwitch[] = { 68 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}}, 69 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}}, 70 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}}, 71 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}}, 72 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}}, 73 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 74 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}}, 75 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}}, 76 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}}, 77 // ESR_EL1 -> DFSR 78 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 79 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 80 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 81 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 82 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}}, 83 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 84 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}}, 85 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 86 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 87 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 88 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 89 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 90 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 91 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 92 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 93 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 94 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 96 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}}, 97 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}}, 98 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}}, 99 // RMR_EL1 -> RMR 100 // RMR_EL2 -> HRMR 101 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}}, 102 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}, 103 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}}, 104 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}}, 105 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}}, 106 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}}, 107 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}}, 108 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}}, 109 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}}, 110 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}}, 111 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}}, 112 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 113 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 114 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 115 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 116 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 117 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */ 118 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 119 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 120 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}}, 121 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */ 122 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}}, 123 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */ 124 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 125 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */ 126 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 127 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */ 128 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */ 129 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}}, 130 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}}, 131 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}}, 132 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}}, 133 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}}, 134 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}}, 135 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}}, 136 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}}, 137 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}}, 138 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}}, 139 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}}, 140 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}}, 141 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}}, 142 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}}, 143 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}}, 144 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 145 // DBGDTRRX_EL0 -> DBGDTRRXint 146 // DBGDTRTX_EL0 -> DBGDTRRXint 147 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}}, 148 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}}, 149 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}}, 150 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}}, 151 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}}, 152 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}}, 153 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}}, 154 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}}, 155 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}}, 156 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}}, 157 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}}, 158 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}}, 159 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}}, 160 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}}, 161 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}}, 162 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}}, 163 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}}, 164 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}}, 165 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}}, 166 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}}, 167 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}}, 168 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}}, 169 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}}, 170 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}}, 171 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}}, 172 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}}, 173/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}}, 174 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}}, 175 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}}, 176 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}}, 177 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}}, 178 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}}, 179 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}}, 180 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}}, 181 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}}, 182 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}}, 183 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}}, 184 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */ 185 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}}, 186 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}}, 187// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}}, 188 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}}, 189 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}}, 190 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}}, 191 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}}, 192 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}}, 193 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}}, 194 195 // from ARM DDI 0487A.i, template text 196 // "AArch64 System register ___ can be mapped to 197 // AArch32 System register ___, but this is not 198 // architecturally mandated." 199 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005 200 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 201 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1 202 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2 203 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3 204}; 205 206 207ISA::ISA(Params *p) 208 : SimObject(p), 209 system(NULL), 210 _decoderFlavour(p->decoderFlavour), 211 pmu(p->pmu), 212 lookUpMiscReg(NUM_MISCREGS, {0,0}) 213{ 214 miscRegs[MISCREG_SCTLR_RST] = 0; 215 216 // Hook up a dummy device if we haven't been configured with a 217 // real PMU. By using a dummy device, we don't need to check that 218 // the PMU exist every time we try to access a PMU register. 219 if (!pmu) 220 pmu = &dummyDevice; 221 222 // Give all ISA devices a pointer to this ISA 223 pmu->setISA(this); 224 225 system = dynamic_cast<ArmSystem *>(p->system); 226 227 // Cache system-level properties 228 if (FullSystem && system) { 229 highestELIs64 = system->highestELIs64(); 230 haveSecurity = system->haveSecurity(); 231 haveLPAE = system->haveLPAE(); 232 haveVirtualization = system->haveVirtualization(); 233 haveLargeAsid64 = system->haveLargeAsid64(); 234 physAddrRange64 = system->physAddrRange64(); 235 } else { 236 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 237 haveSecurity = haveLPAE = haveVirtualization = false; 238 haveLargeAsid64 = false; 239 physAddrRange64 = 32; // dummy value 240 } 241 242 /** Fill in the miscReg translation table */ 243 for (auto sw : MiscRegSwitch) { 244 lookUpMiscReg[sw.index] = sw.entry; 245 } 246 247 preUnflattenMiscReg(); 248 249 clear(); 250} 251 252const ArmISAParams * 253ISA::params() const 254{ 255 return dynamic_cast<const Params *>(_params); 256} 257 258void 259ISA::clear() 260{ 261 const Params *p(params()); 262 263 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 264 memset(miscRegs, 0, sizeof(miscRegs)); 265 266 // Initialize configurable default values 267 miscRegs[MISCREG_MIDR] = p->midr; 268 miscRegs[MISCREG_MIDR_EL1] = p->midr; 269 miscRegs[MISCREG_VPIDR] = p->midr; 270 271 if (FullSystem && system->highestELIs64()) { 272 // Initialize AArch64 state 273 clear64(p); 274 return; 275 } 276 277 // Initialize AArch32 state... 278 279 CPSR cpsr = 0; 280 cpsr.mode = MODE_USER; 281 miscRegs[MISCREG_CPSR] = cpsr; 282 updateRegMap(cpsr); 283 284 SCTLR sctlr = 0; 285 sctlr.te = (bool) sctlr_rst.te; 286 sctlr.nmfi = (bool) sctlr_rst.nmfi; 287 sctlr.v = (bool) sctlr_rst.v; 288 sctlr.u = 1; 289 sctlr.xp = 1; 290 sctlr.rao2 = 1; 291 sctlr.rao3 = 1; 292 sctlr.rao4 = 0xf; // SCTLR[6:3] 293 sctlr.uci = 1; 294 sctlr.dze = 1; 295 miscRegs[MISCREG_SCTLR_NS] = sctlr; 296 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 297 miscRegs[MISCREG_HCPTR] = 0; 298 299 // Start with an event in the mailbox 300 miscRegs[MISCREG_SEV_MAILBOX] = 1; 301 302 // Separate Instruction and Data TLBs 303 miscRegs[MISCREG_TLBTR] = 1; 304 305 MVFR0 mvfr0 = 0; 306 mvfr0.advSimdRegisters = 2; 307 mvfr0.singlePrecision = 2; 308 mvfr0.doublePrecision = 2; 309 mvfr0.vfpExceptionTrapping = 0; 310 mvfr0.divide = 1; 311 mvfr0.squareRoot = 1; 312 mvfr0.shortVectors = 1; 313 mvfr0.roundingModes = 1; 314 miscRegs[MISCREG_MVFR0] = mvfr0; 315 316 MVFR1 mvfr1 = 0; 317 mvfr1.flushToZero = 1; 318 mvfr1.defaultNaN = 1; 319 mvfr1.advSimdLoadStore = 1; 320 mvfr1.advSimdInteger = 1; 321 mvfr1.advSimdSinglePrecision = 1; 322 mvfr1.advSimdHalfPrecision = 1; 323 mvfr1.vfpHalfPrecision = 1; 324 miscRegs[MISCREG_MVFR1] = mvfr1; 325 326 // Reset values of PRRR and NMRR are implementation dependent 327 328 // @todo: PRRR and NMRR in secure state? 329 miscRegs[MISCREG_PRRR_NS] = 330 (1 << 19) | // 19 331 (0 << 18) | // 18 332 (0 << 17) | // 17 333 (1 << 16) | // 16 334 (2 << 14) | // 15:14 335 (0 << 12) | // 13:12 336 (2 << 10) | // 11:10 337 (2 << 8) | // 9:8 338 (2 << 6) | // 7:6 339 (2 << 4) | // 5:4 340 (1 << 2) | // 3:2 341 0; // 1:0 342 miscRegs[MISCREG_NMRR_NS] = 343 (1 << 30) | // 31:30 344 (0 << 26) | // 27:26 345 (0 << 24) | // 25:24 346 (3 << 22) | // 23:22 347 (2 << 20) | // 21:20 348 (0 << 18) | // 19:18 349 (0 << 16) | // 17:16 350 (1 << 14) | // 15:14 351 (0 << 12) | // 13:12 352 (2 << 10) | // 11:10 353 (0 << 8) | // 9:8 354 (3 << 6) | // 7:6 355 (2 << 4) | // 5:4 356 (0 << 2) | // 3:2 357 0; // 1:0 358 359 miscRegs[MISCREG_CPACR] = 0; 360 361 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 362 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 363 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 364 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 365 366 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 367 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 368 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 369 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 370 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 371 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 372 373 miscRegs[MISCREG_FPSID] = p->fpsid; 374 375 if (haveLPAE) { 376 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 377 ttbcr.eae = 0; 378 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 379 // Enforce consistency with system-level settings 380 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 381 } 382 383 if (haveSecurity) { 384 miscRegs[MISCREG_SCTLR_S] = sctlr; 385 miscRegs[MISCREG_SCR] = 0; 386 miscRegs[MISCREG_VBAR_S] = 0; 387 } else { 388 // we're always non-secure 389 miscRegs[MISCREG_SCR] = 1; 390 } 391 392 //XXX We need to initialize the rest of the state. 393} 394 395void 396ISA::clear64(const ArmISAParams *p) 397{ 398 CPSR cpsr = 0; 399 Addr rvbar = system->resetAddr64(); 400 switch (system->highestEL()) { 401 // Set initial EL to highest implemented EL using associated stack 402 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 403 // value 404 case EL3: 405 cpsr.mode = MODE_EL3H; 406 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 407 break; 408 case EL2: 409 cpsr.mode = MODE_EL2H; 410 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 411 break; 412 case EL1: 413 cpsr.mode = MODE_EL1H; 414 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 415 break; 416 default: 417 panic("Invalid highest implemented exception level"); 418 break; 419 } 420 421 // Initialize rest of CPSR 422 cpsr.daif = 0xf; // Mask all interrupts 423 cpsr.ss = 0; 424 cpsr.il = 0; 425 miscRegs[MISCREG_CPSR] = cpsr; 426 updateRegMap(cpsr); 427 428 // Initialize other control registers 429 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 430 if (haveSecurity) { 431 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 432 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 433 } else if (haveVirtualization) { 434 // also MISCREG_SCTLR_EL2 (by mapping) 435 miscRegs[MISCREG_HSCTLR] = 0x30c50830; 436 } else { 437 // also MISCREG_SCTLR_EL1 (by mapping) 438 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 439 // Always non-secure 440 miscRegs[MISCREG_SCR_EL3] = 1; 441 } 442 443 // Initialize configurable id registers 444 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 445 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 446 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 447 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 448 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 449 450 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 451 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 452 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 453 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 454 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 455 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 456 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 457 458 miscRegs[MISCREG_ID_DFR0_EL1] = 459 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 460 461 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 462 463 // Enforce consistency with system-level settings... 464 465 // EL3 466 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 467 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 468 haveSecurity ? 0x2 : 0x0); 469 // EL2 470 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 471 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 472 haveVirtualization ? 0x2 : 0x0); 473 // Large ASID support 474 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 475 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 476 haveLargeAsid64 ? 0x2 : 0x0); 477 // Physical address size 478 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 479 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 480 encodePhysAddrRange64(physAddrRange64)); 481} 482 483MiscReg 484ISA::readMiscRegNoEffect(int misc_reg) const 485{ 486 assert(misc_reg < NumMiscRegs); 487 488 auto regs = getMiscIndices(misc_reg); 489 int lower = regs.first, upper = regs.second; 490 return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 491 |(miscRegs[upper] << 32)); 492} 493 494 495MiscReg 496ISA::readMiscReg(int misc_reg, ThreadContext *tc) 497{ 498 CPSR cpsr = 0; 499 PCState pc = 0; 500 SCR scr = 0; 501 502 if (misc_reg == MISCREG_CPSR) { 503 cpsr = miscRegs[misc_reg]; 504 pc = tc->pcState(); 505 cpsr.j = pc.jazelle() ? 1 : 0; 506 cpsr.t = pc.thumb() ? 1 : 0; 507 return cpsr; 508 } 509 510#ifndef NDEBUG 511 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 512 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 513 warn("Unimplemented system register %s read.\n", 514 miscRegName[misc_reg]); 515 else 516 panic("Unimplemented system register %s read.\n", 517 miscRegName[misc_reg]); 518 } 519#endif 520 521 switch (unflattenMiscReg(misc_reg)) { 522 case MISCREG_HCR: 523 { 524 if (!haveVirtualization) 525 return 0; 526 else 527 return readMiscRegNoEffect(MISCREG_HCR); 528 } 529 case MISCREG_CPACR: 530 { 531 const uint32_t ones = (uint32_t)(-1); 532 CPACR cpacrMask = 0; 533 // Only cp10, cp11, and ase are implemented, nothing else should 534 // be readable? (straight copy from the write code) 535 cpacrMask.cp10 = ones; 536 cpacrMask.cp11 = ones; 537 cpacrMask.asedis = ones; 538 539 // Security Extensions may limit the readability of CPACR 540 if (haveSecurity) { 541 scr = readMiscRegNoEffect(MISCREG_SCR); 542 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 543 if (scr.ns && (cpsr.mode != MODE_MON)) { 544 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 545 // NB: Skipping the full loop, here 546 if (!nsacr.cp10) cpacrMask.cp10 = 0; 547 if (!nsacr.cp11) cpacrMask.cp11 = 0; 548 } 549 } 550 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 551 val &= cpacrMask; 552 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 553 miscRegName[misc_reg], val); 554 return val; 555 } 556 case MISCREG_MPIDR: 557 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 558 scr = readMiscRegNoEffect(MISCREG_SCR); 559 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 560 return getMPIDR(system, tc); 561 } else { 562 return readMiscReg(MISCREG_VMPIDR, tc); 563 } 564 break; 565 case MISCREG_MPIDR_EL1: 566 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 567 return getMPIDR(system, tc) & 0xffffffff; 568 case MISCREG_VMPIDR: 569 // top bit defined as RES1 570 return readMiscRegNoEffect(misc_reg) | 0x80000000; 571 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 572 case MISCREG_REVIDR: // not implemented, so alias MIDR 573 case MISCREG_MIDR: 574 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 575 scr = readMiscRegNoEffect(MISCREG_SCR); 576 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 577 return readMiscRegNoEffect(misc_reg); 578 } else { 579 return readMiscRegNoEffect(MISCREG_VPIDR); 580 } 581 break; 582 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 583 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 584 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 585 case MISCREG_AIDR: // AUX ID set to 0 586 case MISCREG_TCMTR: // No TCM's 587 return 0; 588 589 case MISCREG_CLIDR: 590 warn_once("The clidr register always reports 0 caches.\n"); 591 warn_once("clidr LoUIS field of 0b001 to match current " 592 "ARM implementations.\n"); 593 return 0x00200000; 594 case MISCREG_CCSIDR: 595 warn_once("The ccsidr register isn't implemented and " 596 "always reads as 0.\n"); 597 break; 598 case MISCREG_CTR: 599 { 600 //all caches have the same line size in gem5 601 //4 byte words in ARM 602 unsigned lineSizeWords = 603 tc->getSystemPtr()->cacheLineSize() / 4; 604 unsigned log2LineSizeWords = 0; 605 606 while (lineSizeWords >>= 1) { 607 ++log2LineSizeWords; 608 } 609 610 CTR ctr = 0; 611 //log2 of minimun i-cache line size (words) 612 ctr.iCacheLineSize = log2LineSizeWords; 613 //b11 - gem5 uses pipt 614 ctr.l1IndexPolicy = 0x3; 615 //log2 of minimum d-cache line size (words) 616 ctr.dCacheLineSize = log2LineSizeWords; 617 //log2 of max reservation size (words) 618 ctr.erg = log2LineSizeWords; 619 //log2 of max writeback size (words) 620 ctr.cwg = log2LineSizeWords; 621 //b100 - gem5 format is ARMv7 622 ctr.format = 0x4; 623 624 return ctr; 625 } 626 case MISCREG_ACTLR: 627 warn("Not doing anything for miscreg ACTLR\n"); 628 break; 629 630 case MISCREG_PMXEVTYPER_PMCCFILTR: 631 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 632 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 633 case MISCREG_PMCR ... MISCREG_PMOVSSET: 634 return pmu->readMiscReg(misc_reg); 635 636 case MISCREG_CPSR_Q: 637 panic("shouldn't be reading this register seperately\n"); 638 case MISCREG_FPSCR_QC: 639 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 640 case MISCREG_FPSCR_EXC: 641 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 642 case MISCREG_FPSR: 643 { 644 const uint32_t ones = (uint32_t)(-1); 645 FPSCR fpscrMask = 0; 646 fpscrMask.ioc = ones; 647 fpscrMask.dzc = ones; 648 fpscrMask.ofc = ones; 649 fpscrMask.ufc = ones; 650 fpscrMask.ixc = ones; 651 fpscrMask.idc = ones; 652 fpscrMask.qc = ones; 653 fpscrMask.v = ones; 654 fpscrMask.c = ones; 655 fpscrMask.z = ones; 656 fpscrMask.n = ones; 657 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 658 } 659 case MISCREG_FPCR: 660 { 661 const uint32_t ones = (uint32_t)(-1); 662 FPSCR fpscrMask = 0; 663 fpscrMask.ioe = ones; 664 fpscrMask.dze = ones; 665 fpscrMask.ofe = ones; 666 fpscrMask.ufe = ones; 667 fpscrMask.ixe = ones; 668 fpscrMask.ide = ones; 669 fpscrMask.len = ones; 670 fpscrMask.stride = ones; 671 fpscrMask.rMode = ones; 672 fpscrMask.fz = ones; 673 fpscrMask.dn = ones; 674 fpscrMask.ahp = ones; 675 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 676 } 677 case MISCREG_NZCV: 678 { 679 CPSR cpsr = 0; 680 cpsr.nz = tc->readCCReg(CCREG_NZ); 681 cpsr.c = tc->readCCReg(CCREG_C); 682 cpsr.v = tc->readCCReg(CCREG_V); 683 return cpsr; 684 } 685 case MISCREG_DAIF: 686 { 687 CPSR cpsr = 0; 688 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 689 return cpsr; 690 } 691 case MISCREG_SP_EL0: 692 { 693 return tc->readIntReg(INTREG_SP0); 694 } 695 case MISCREG_SP_EL1: 696 { 697 return tc->readIntReg(INTREG_SP1); 698 } 699 case MISCREG_SP_EL2: 700 { 701 return tc->readIntReg(INTREG_SP2); 702 } 703 case MISCREG_SPSEL: 704 { 705 return miscRegs[MISCREG_CPSR] & 0x1; 706 } 707 case MISCREG_CURRENTEL: 708 { 709 return miscRegs[MISCREG_CPSR] & 0xc; 710 } 711 case MISCREG_L2CTLR: 712 { 713 // mostly unimplemented, just set NumCPUs field from sim and return 714 L2CTLR l2ctlr = 0; 715 // b00:1CPU to b11:4CPUs 716 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 717 return l2ctlr; 718 } 719 case MISCREG_DBGDIDR: 720 /* For now just implement the version number. 721 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 722 */ 723 return 0x5 << 16; 724 case MISCREG_DBGDSCRint: 725 return 0; 726 case MISCREG_ISR: 727 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 728 readMiscRegNoEffect(MISCREG_HCR), 729 readMiscRegNoEffect(MISCREG_CPSR), 730 readMiscRegNoEffect(MISCREG_SCR)); 731 case MISCREG_ISR_EL1: 732 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 733 readMiscRegNoEffect(MISCREG_HCR_EL2), 734 readMiscRegNoEffect(MISCREG_CPSR), 735 readMiscRegNoEffect(MISCREG_SCR_EL3)); 736 case MISCREG_DCZID_EL0: 737 return 0x04; // DC ZVA clear 64-byte chunks 738 case MISCREG_HCPTR: 739 { 740 MiscReg val = readMiscRegNoEffect(misc_reg); 741 // The trap bit associated with CP14 is defined as RAZ 742 val &= ~(1 << 14); 743 // If a CP bit in NSACR is 0 then the corresponding bit in 744 // HCPTR is RAO/WI 745 bool secure_lookup = haveSecurity && 746 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 747 readMiscRegNoEffect(MISCREG_CPSR)); 748 if (!secure_lookup) { 749 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 750 val |= (mask ^ 0x7FFF) & 0xBFFF; 751 } 752 // Set the bits for unimplemented coprocessors to RAO/WI 753 val |= 0x33FF; 754 return (val); 755 } 756 case MISCREG_HDFAR: // alias for secure DFAR 757 return readMiscRegNoEffect(MISCREG_DFAR_S); 758 case MISCREG_HIFAR: // alias for secure IFAR 759 return readMiscRegNoEffect(MISCREG_IFAR_S); 760 case MISCREG_HVBAR: // bottom bits reserved 761 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 762 case MISCREG_SCTLR: 763 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 764 case MISCREG_SCTLR_EL1: 765 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 766 case MISCREG_SCTLR_EL2: 767 case MISCREG_SCTLR_EL3: 768 case MISCREG_HSCTLR: 769 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 770 771 case MISCREG_ID_PFR0: 772 // !ThumbEE | !Jazelle | Thumb | ARM 773 return 0x00000031; 774 case MISCREG_ID_PFR1: 775 // !Timer | Virti | !M Profile | TrustZone | ARMv4 776 return 0x00000001 777 | (haveSecurity ? 0x00000010 : 0x0) 778 | (haveVirtualization ? 0x00001000 : 0x0); 779 780 // Generic Timer registers 781 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 782 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 783 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 784 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 785 return getGenericTimer(tc).readMiscReg(misc_reg); 786 787 default: 788 break; 789 790 } 791 return readMiscRegNoEffect(misc_reg); 792} 793 794void 795ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 796{ 797 assert(misc_reg < NumMiscRegs); 798 799 auto regs = getMiscIndices(misc_reg); 800 int lower = regs.first, upper = regs.second; 801 if (upper > 0) { 802 miscRegs[lower] = bits(val, 31, 0); 803 miscRegs[upper] = bits(val, 63, 32); 804 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 805 misc_reg, lower, upper, val); 806 } else { 807 miscRegs[lower] = val; 808 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 809 misc_reg, lower, val); 810 } 811} 812 813void 814ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 815{ 816 817 MiscReg newVal = val; 818 int x; 819 bool secure_lookup; 820 bool hyp; 821 System *sys; 822 ThreadContext *oc; 823 uint8_t target_el; 824 uint16_t asid; 825 SCR scr; 826 827 if (misc_reg == MISCREG_CPSR) { 828 updateRegMap(val); 829 830 831 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 832 int old_mode = old_cpsr.mode; 833 CPSR cpsr = val; 834 if (old_mode != cpsr.mode) { 835 tc->getITBPtr()->invalidateMiscReg(); 836 tc->getDTBPtr()->invalidateMiscReg(); 837 } 838 839 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 840 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 841 PCState pc = tc->pcState(); 842 pc.nextThumb(cpsr.t); 843 pc.nextJazelle(cpsr.j); 844 845 // Follow slightly different semantics if a CheckerCPU object 846 // is connected 847 CheckerCPU *checker = tc->getCheckerCpuPtr(); 848 if (checker) { 849 tc->pcStateNoRecord(pc); 850 } else { 851 tc->pcState(pc); 852 } 853 } else { 854#ifndef NDEBUG 855 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 856 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 857 warn("Unimplemented system register %s write with %#x.\n", 858 miscRegName[misc_reg], val); 859 else 860 panic("Unimplemented system register %s write with %#x.\n", 861 miscRegName[misc_reg], val); 862 } 863#endif 864 switch (unflattenMiscReg(misc_reg)) { 865 case MISCREG_CPACR: 866 { 867 868 const uint32_t ones = (uint32_t)(-1); 869 CPACR cpacrMask = 0; 870 // Only cp10, cp11, and ase are implemented, nothing else should 871 // be writable 872 cpacrMask.cp10 = ones; 873 cpacrMask.cp11 = ones; 874 cpacrMask.asedis = ones; 875 876 // Security Extensions may limit the writability of CPACR 877 if (haveSecurity) { 878 scr = readMiscRegNoEffect(MISCREG_SCR); 879 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 880 if (scr.ns && (cpsr.mode != MODE_MON)) { 881 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 882 // NB: Skipping the full loop, here 883 if (!nsacr.cp10) cpacrMask.cp10 = 0; 884 if (!nsacr.cp11) cpacrMask.cp11 = 0; 885 } 886 } 887 888 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 889 newVal &= cpacrMask; 890 newVal |= old_val & ~cpacrMask; 891 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 892 miscRegName[misc_reg], newVal); 893 } 894 break; 895 case MISCREG_CPACR_EL1: 896 { 897 const uint32_t ones = (uint32_t)(-1); 898 CPACR cpacrMask = 0; 899 cpacrMask.tta = ones; 900 cpacrMask.fpen = ones; 901 newVal &= cpacrMask; 902 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 903 miscRegName[misc_reg], newVal); 904 } 905 break; 906 case MISCREG_CPTR_EL2: 907 { 908 const uint32_t ones = (uint32_t)(-1); 909 CPTR cptrMask = 0; 910 cptrMask.tcpac = ones; 911 cptrMask.tta = ones; 912 cptrMask.tfp = ones; 913 newVal &= cptrMask; 914 cptrMask = 0; 915 cptrMask.res1_13_12_el2 = ones; 916 cptrMask.res1_9_0_el2 = ones; 917 newVal |= cptrMask; 918 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 919 miscRegName[misc_reg], newVal); 920 } 921 break; 922 case MISCREG_CPTR_EL3: 923 { 924 const uint32_t ones = (uint32_t)(-1); 925 CPTR cptrMask = 0; 926 cptrMask.tcpac = ones; 927 cptrMask.tta = ones; 928 cptrMask.tfp = ones; 929 newVal &= cptrMask; 930 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 931 miscRegName[misc_reg], newVal); 932 } 933 break; 934 case MISCREG_CSSELR: 935 warn_once("The csselr register isn't implemented.\n"); 936 return; 937 938 case MISCREG_DC_ZVA_Xt: 939 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 940 return; 941 942 case MISCREG_FPSCR: 943 { 944 const uint32_t ones = (uint32_t)(-1); 945 FPSCR fpscrMask = 0; 946 fpscrMask.ioc = ones; 947 fpscrMask.dzc = ones; 948 fpscrMask.ofc = ones; 949 fpscrMask.ufc = ones; 950 fpscrMask.ixc = ones; 951 fpscrMask.idc = ones; 952 fpscrMask.ioe = ones; 953 fpscrMask.dze = ones; 954 fpscrMask.ofe = ones; 955 fpscrMask.ufe = ones; 956 fpscrMask.ixe = ones; 957 fpscrMask.ide = ones; 958 fpscrMask.len = ones; 959 fpscrMask.stride = ones; 960 fpscrMask.rMode = ones; 961 fpscrMask.fz = ones; 962 fpscrMask.dn = ones; 963 fpscrMask.ahp = ones; 964 fpscrMask.qc = ones; 965 fpscrMask.v = ones; 966 fpscrMask.c = ones; 967 fpscrMask.z = ones; 968 fpscrMask.n = ones; 969 newVal = (newVal & (uint32_t)fpscrMask) | 970 (readMiscRegNoEffect(MISCREG_FPSCR) & 971 ~(uint32_t)fpscrMask); 972 tc->getDecoderPtr()->setContext(newVal); 973 } 974 break; 975 case MISCREG_FPSR: 976 { 977 const uint32_t ones = (uint32_t)(-1); 978 FPSCR fpscrMask = 0; 979 fpscrMask.ioc = ones; 980 fpscrMask.dzc = ones; 981 fpscrMask.ofc = ones; 982 fpscrMask.ufc = ones; 983 fpscrMask.ixc = ones; 984 fpscrMask.idc = ones; 985 fpscrMask.qc = ones; 986 fpscrMask.v = ones; 987 fpscrMask.c = ones; 988 fpscrMask.z = ones; 989 fpscrMask.n = ones; 990 newVal = (newVal & (uint32_t)fpscrMask) | 991 (readMiscRegNoEffect(MISCREG_FPSCR) & 992 ~(uint32_t)fpscrMask); 993 misc_reg = MISCREG_FPSCR; 994 } 995 break; 996 case MISCREG_FPCR: 997 { 998 const uint32_t ones = (uint32_t)(-1); 999 FPSCR fpscrMask = 0; 1000 fpscrMask.ioe = ones; 1001 fpscrMask.dze = ones; 1002 fpscrMask.ofe = ones; 1003 fpscrMask.ufe = ones; 1004 fpscrMask.ixe = ones; 1005 fpscrMask.ide = ones; 1006 fpscrMask.len = ones; 1007 fpscrMask.stride = ones; 1008 fpscrMask.rMode = ones; 1009 fpscrMask.fz = ones; 1010 fpscrMask.dn = ones; 1011 fpscrMask.ahp = ones; 1012 newVal = (newVal & (uint32_t)fpscrMask) | 1013 (readMiscRegNoEffect(MISCREG_FPSCR) & 1014 ~(uint32_t)fpscrMask); 1015 misc_reg = MISCREG_FPSCR; 1016 } 1017 break; 1018 case MISCREG_CPSR_Q: 1019 { 1020 assert(!(newVal & ~CpsrMaskQ)); 1021 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1022 misc_reg = MISCREG_CPSR; 1023 } 1024 break; 1025 case MISCREG_FPSCR_QC: 1026 { 1027 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1028 (newVal & FpscrQcMask); 1029 misc_reg = MISCREG_FPSCR; 1030 } 1031 break; 1032 case MISCREG_FPSCR_EXC: 1033 { 1034 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1035 (newVal & FpscrExcMask); 1036 misc_reg = MISCREG_FPSCR; 1037 } 1038 break; 1039 case MISCREG_FPEXC: 1040 { 1041 // vfpv3 architecture, section B.6.1 of DDI04068 1042 // bit 29 - valid only if fpexc[31] is 0 1043 const uint32_t fpexcMask = 0x60000000; 1044 newVal = (newVal & fpexcMask) | 1045 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1046 } 1047 break; 1048 case MISCREG_HCR: 1049 { 1050 if (!haveVirtualization) 1051 return; 1052 } 1053 break; 1054 case MISCREG_IFSR: 1055 { 1056 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1057 const uint32_t ifsrMask = 1058 mask(31, 13) | mask(11, 11) | mask(8, 6); 1059 newVal = newVal & ~ifsrMask; 1060 } 1061 break; 1062 case MISCREG_DFSR: 1063 { 1064 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1065 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1066 newVal = newVal & ~dfsrMask; 1067 } 1068 break; 1069 case MISCREG_AMAIR0: 1070 case MISCREG_AMAIR1: 1071 { 1072 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1073 // Valid only with LPAE 1074 if (!haveLPAE) 1075 return; 1076 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1077 } 1078 break; 1079 case MISCREG_SCR: 1080 tc->getITBPtr()->invalidateMiscReg(); 1081 tc->getDTBPtr()->invalidateMiscReg(); 1082 break; 1083 case MISCREG_SCTLR: 1084 { 1085 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1086 scr = readMiscRegNoEffect(MISCREG_SCR); 1087 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 1088 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 1089 SCTLR sctlr = miscRegs[sctlr_idx]; 1090 SCTLR new_sctlr = newVal; 1091 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1092 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1093 tc->getITBPtr()->invalidateMiscReg(); 1094 tc->getDTBPtr()->invalidateMiscReg(); 1095 } 1096 case MISCREG_MIDR: 1097 case MISCREG_ID_PFR0: 1098 case MISCREG_ID_PFR1: 1099 case MISCREG_ID_DFR0: 1100 case MISCREG_ID_MMFR0: 1101 case MISCREG_ID_MMFR1: 1102 case MISCREG_ID_MMFR2: 1103 case MISCREG_ID_MMFR3: 1104 case MISCREG_ID_ISAR0: 1105 case MISCREG_ID_ISAR1: 1106 case MISCREG_ID_ISAR2: 1107 case MISCREG_ID_ISAR3: 1108 case MISCREG_ID_ISAR4: 1109 case MISCREG_ID_ISAR5: 1110 1111 case MISCREG_MPIDR: 1112 case MISCREG_FPSID: 1113 case MISCREG_TLBTR: 1114 case MISCREG_MVFR0: 1115 case MISCREG_MVFR1: 1116 1117 case MISCREG_ID_AA64AFR0_EL1: 1118 case MISCREG_ID_AA64AFR1_EL1: 1119 case MISCREG_ID_AA64DFR0_EL1: 1120 case MISCREG_ID_AA64DFR1_EL1: 1121 case MISCREG_ID_AA64ISAR0_EL1: 1122 case MISCREG_ID_AA64ISAR1_EL1: 1123 case MISCREG_ID_AA64MMFR0_EL1: 1124 case MISCREG_ID_AA64MMFR1_EL1: 1125 case MISCREG_ID_AA64PFR0_EL1: 1126 case MISCREG_ID_AA64PFR1_EL1: 1127 // ID registers are constants. 1128 return; 1129 1130 // TLBI all entries, EL0&1 inner sharable (ignored) 1131 case MISCREG_TLBIALLIS: 1132 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1133 assert32(tc); 1134 target_el = 1; // el 0 and 1 are handled together 1135 scr = readMiscReg(MISCREG_SCR, tc); 1136 secure_lookup = haveSecurity && !scr.ns; 1137 sys = tc->getSystemPtr(); 1138 for (x = 0; x < sys->numContexts(); x++) { 1139 oc = sys->getThreadContext(x); 1140 assert(oc->getITBPtr() && oc->getDTBPtr()); 1141 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1142 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1143 1144 // If CheckerCPU is connected, need to notify it of a flush 1145 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1146 if (checker) { 1147 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1148 target_el); 1149 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1150 target_el); 1151 } 1152 } 1153 return; 1154 // TLBI all entries, EL0&1, instruction side 1155 case MISCREG_ITLBIALL: 1156 assert32(tc); 1157 target_el = 1; // el 0 and 1 are handled together 1158 scr = readMiscReg(MISCREG_SCR, tc); 1159 secure_lookup = haveSecurity && !scr.ns; 1160 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1161 return; 1162 // TLBI all entries, EL0&1, data side 1163 case MISCREG_DTLBIALL: 1164 assert32(tc); 1165 target_el = 1; // el 0 and 1 are handled together 1166 scr = readMiscReg(MISCREG_SCR, tc); 1167 secure_lookup = haveSecurity && !scr.ns; 1168 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1169 return; 1170 // TLBI based on VA, EL0&1 inner sharable (ignored) 1171 case MISCREG_TLBIMVAIS: 1172 case MISCREG_TLBIMVA: 1173 assert32(tc); 1174 target_el = 1; // el 0 and 1 are handled together 1175 scr = readMiscReg(MISCREG_SCR, tc); 1176 secure_lookup = haveSecurity && !scr.ns; 1177 sys = tc->getSystemPtr(); 1178 for (x = 0; x < sys->numContexts(); x++) { 1179 oc = sys->getThreadContext(x); 1180 assert(oc->getITBPtr() && oc->getDTBPtr()); 1181 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1182 bits(newVal, 7,0), 1183 secure_lookup, target_el); 1184 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1185 bits(newVal, 7,0), 1186 secure_lookup, target_el); 1187 1188 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1189 if (checker) { 1190 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1191 bits(newVal, 7,0), secure_lookup, target_el); 1192 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1193 bits(newVal, 7,0), secure_lookup, target_el); 1194 } 1195 } 1196 return; 1197 // TLBI by ASID, EL0&1, inner sharable 1198 case MISCREG_TLBIASIDIS: 1199 case MISCREG_TLBIASID: 1200 assert32(tc); 1201 target_el = 1; // el 0 and 1 are handled together 1202 scr = readMiscReg(MISCREG_SCR, tc); 1203 secure_lookup = haveSecurity && !scr.ns; 1204 sys = tc->getSystemPtr(); 1205 for (x = 0; x < sys->numContexts(); x++) { 1206 oc = sys->getThreadContext(x); 1207 assert(oc->getITBPtr() && oc->getDTBPtr()); 1208 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1209 secure_lookup, target_el); 1210 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1211 secure_lookup, target_el); 1212 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1213 if (checker) { 1214 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1215 secure_lookup, target_el); 1216 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1217 secure_lookup, target_el); 1218 } 1219 } 1220 return; 1221 // TLBI by address, EL0&1, inner sharable (ignored) 1222 case MISCREG_TLBIMVAAIS: 1223 case MISCREG_TLBIMVAA: 1224 assert32(tc); 1225 target_el = 1; // el 0 and 1 are handled together 1226 scr = readMiscReg(MISCREG_SCR, tc); 1227 secure_lookup = haveSecurity && !scr.ns; 1228 hyp = 0; 1229 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1230 return; 1231 // TLBI by address, EL2, hypervisor mode 1232 case MISCREG_TLBIMVAH: 1233 case MISCREG_TLBIMVAHIS: 1234 assert32(tc); 1235 target_el = 1; // aarch32, use hyp bit 1236 scr = readMiscReg(MISCREG_SCR, tc); 1237 secure_lookup = haveSecurity && !scr.ns; 1238 hyp = 1; 1239 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1240 return; 1241 // TLBI by address and asid, EL0&1, instruction side only 1242 case MISCREG_ITLBIMVA: 1243 assert32(tc); 1244 target_el = 1; // el 0 and 1 are handled together 1245 scr = readMiscReg(MISCREG_SCR, tc); 1246 secure_lookup = haveSecurity && !scr.ns; 1247 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1248 bits(newVal, 7,0), secure_lookup, target_el); 1249 return; 1250 // TLBI by address and asid, EL0&1, data side only 1251 case MISCREG_DTLBIMVA: 1252 assert32(tc); 1253 target_el = 1; // el 0 and 1 are handled together 1254 scr = readMiscReg(MISCREG_SCR, tc); 1255 secure_lookup = haveSecurity && !scr.ns; 1256 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1257 bits(newVal, 7,0), secure_lookup, target_el); 1258 return; 1259 // TLBI by ASID, EL0&1, instrution side only 1260 case MISCREG_ITLBIASID: 1261 assert32(tc); 1262 target_el = 1; // el 0 and 1 are handled together 1263 scr = readMiscReg(MISCREG_SCR, tc); 1264 secure_lookup = haveSecurity && !scr.ns; 1265 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1266 target_el); 1267 return; 1268 // TLBI by ASID EL0&1 data size only 1269 case MISCREG_DTLBIASID: 1270 assert32(tc); 1271 target_el = 1; // el 0 and 1 are handled together 1272 scr = readMiscReg(MISCREG_SCR, tc); 1273 secure_lookup = haveSecurity && !scr.ns; 1274 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1275 target_el); 1276 return; 1277 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1278 case MISCREG_TLBIALLNSNH: 1279 case MISCREG_TLBIALLNSNHIS: 1280 assert32(tc); 1281 target_el = 1; // el 0 and 1 are handled together 1282 hyp = 0; 1283 tlbiALLN(tc, hyp, target_el); 1284 return; 1285 // TLBI all entries, EL2, hyp, 1286 case MISCREG_TLBIALLH: 1287 case MISCREG_TLBIALLHIS: 1288 assert32(tc); 1289 target_el = 1; // aarch32, use hyp bit 1290 hyp = 1; 1291 tlbiALLN(tc, hyp, target_el); 1292 return; 1293 // AArch64 TLBI: invalidate all entries EL3 1294 case MISCREG_TLBI_ALLE3IS: 1295 case MISCREG_TLBI_ALLE3: 1296 assert64(tc); 1297 target_el = 3; 1298 secure_lookup = true; 1299 tlbiALL(tc, secure_lookup, target_el); 1300 return; 1301 // @todo: uncomment this to enable Virtualization 1302 // case MISCREG_TLBI_ALLE2IS: 1303 // case MISCREG_TLBI_ALLE2: 1304 // TLBI all entries, EL0&1 1305 case MISCREG_TLBI_ALLE1IS: 1306 case MISCREG_TLBI_ALLE1: 1307 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1308 case MISCREG_TLBI_VMALLE1IS: 1309 case MISCREG_TLBI_VMALLE1: 1310 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1311 case MISCREG_TLBI_VMALLS12E1IS: 1312 case MISCREG_TLBI_VMALLS12E1: 1313 // @todo: handle VMID and stage 2 to enable Virtualization 1314 assert64(tc); 1315 target_el = 1; // el 0 and 1 are handled together 1316 scr = readMiscReg(MISCREG_SCR, tc); 1317 secure_lookup = haveSecurity && !scr.ns; 1318 tlbiALL(tc, secure_lookup, target_el); 1319 return; 1320 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1321 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1322 // from the last level of translation table walks 1323 // @todo: handle VMID to enable Virtualization 1324 // TLBI all entries, EL0&1 1325 case MISCREG_TLBI_VAE3IS_Xt: 1326 case MISCREG_TLBI_VAE3_Xt: 1327 // TLBI by VA, EL3 regime stage 1, last level walk 1328 case MISCREG_TLBI_VALE3IS_Xt: 1329 case MISCREG_TLBI_VALE3_Xt: 1330 assert64(tc); 1331 target_el = 3; 1332 asid = 0xbeef; // does not matter, tlbi is global 1333 secure_lookup = true; 1334 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1335 return; 1336 // TLBI by VA, EL2 1337 case MISCREG_TLBI_VAE2IS_Xt: 1338 case MISCREG_TLBI_VAE2_Xt: 1339 // TLBI by VA, EL2, stage1 last level walk 1340 case MISCREG_TLBI_VALE2IS_Xt: 1341 case MISCREG_TLBI_VALE2_Xt: 1342 assert64(tc); 1343 target_el = 2; 1344 asid = 0xbeef; // does not matter, tlbi is global 1345 scr = readMiscReg(MISCREG_SCR, tc); 1346 secure_lookup = haveSecurity && !scr.ns; 1347 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1348 return; 1349 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1350 case MISCREG_TLBI_VAE1IS_Xt: 1351 case MISCREG_TLBI_VAE1_Xt: 1352 case MISCREG_TLBI_VALE1IS_Xt: 1353 case MISCREG_TLBI_VALE1_Xt: 1354 assert64(tc); 1355 asid = bits(newVal, 63, 48); 1356 target_el = 1; // el 0 and 1 are handled together 1357 scr = readMiscReg(MISCREG_SCR, tc); 1358 secure_lookup = haveSecurity && !scr.ns; 1359 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1360 return; 1361 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1362 // @todo: handle VMID to enable Virtualization 1363 case MISCREG_TLBI_ASIDE1IS_Xt: 1364 case MISCREG_TLBI_ASIDE1_Xt: 1365 assert64(tc); 1366 target_el = 1; // el 0 and 1 are handled together 1367 scr = readMiscReg(MISCREG_SCR, tc); 1368 secure_lookup = haveSecurity && !scr.ns; 1369 sys = tc->getSystemPtr(); 1370 for (x = 0; x < sys->numContexts(); x++) { 1371 oc = sys->getThreadContext(x); 1372 assert(oc->getITBPtr() && oc->getDTBPtr()); 1373 asid = bits(newVal, 63, 48); 1374 if (!haveLargeAsid64) 1375 asid &= mask(8); 1376 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1377 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1378 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1379 if (checker) { 1380 checker->getITBPtr()->flushAsid(asid, 1381 secure_lookup, target_el); 1382 checker->getDTBPtr()->flushAsid(asid, 1383 secure_lookup, target_el); 1384 } 1385 } 1386 return; 1387 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1388 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1389 // entries from the last level of translation table walks 1390 // @todo: handle VMID to enable Virtualization 1391 case MISCREG_TLBI_VAAE1IS_Xt: 1392 case MISCREG_TLBI_VAAE1_Xt: 1393 case MISCREG_TLBI_VAALE1IS_Xt: 1394 case MISCREG_TLBI_VAALE1_Xt: 1395 assert64(tc); 1396 target_el = 1; // el 0 and 1 are handled together 1397 scr = readMiscReg(MISCREG_SCR, tc); 1398 secure_lookup = haveSecurity && !scr.ns; 1399 sys = tc->getSystemPtr(); 1400 for (x = 0; x < sys->numContexts(); x++) { 1401 // @todo: extra controls on TLBI broadcast? 1402 oc = sys->getThreadContext(x); 1403 assert(oc->getITBPtr() && oc->getDTBPtr()); 1404 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1405 oc->getITBPtr()->flushMva(va, 1406 secure_lookup, false, target_el); 1407 oc->getDTBPtr()->flushMva(va, 1408 secure_lookup, false, target_el); 1409 1410 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1411 if (checker) { 1412 checker->getITBPtr()->flushMva(va, 1413 secure_lookup, false, target_el); 1414 checker->getDTBPtr()->flushMva(va, 1415 secure_lookup, false, target_el); 1416 } 1417 } 1418 return; 1419 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1420 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1421 case MISCREG_TLBI_IPAS2LE1_Xt: 1422 case MISCREG_TLBI_IPAS2E1IS_Xt: 1423 case MISCREG_TLBI_IPAS2E1_Xt: 1424 assert64(tc); 1425 target_el = 1; // EL 0 and 1 are handled together 1426 scr = readMiscReg(MISCREG_SCR, tc); 1427 secure_lookup = haveSecurity && !scr.ns; 1428 sys = tc->getSystemPtr(); 1429 for (x = 0; x < sys->numContexts(); x++) { 1430 oc = sys->getThreadContext(x); 1431 assert(oc->getITBPtr() && oc->getDTBPtr()); 1432 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 1433 oc->getITBPtr()->flushIpaVmid(ipa, 1434 secure_lookup, false, target_el); 1435 oc->getDTBPtr()->flushIpaVmid(ipa, 1436 secure_lookup, false, target_el); 1437 1438 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1439 if (checker) { 1440 checker->getITBPtr()->flushIpaVmid(ipa, 1441 secure_lookup, false, target_el); 1442 checker->getDTBPtr()->flushIpaVmid(ipa, 1443 secure_lookup, false, target_el); 1444 } 1445 } 1446 return; 1447 case MISCREG_ACTLR: 1448 warn("Not doing anything for write of miscreg ACTLR\n"); 1449 break; 1450 1451 case MISCREG_PMXEVTYPER_PMCCFILTR: 1452 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1453 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1454 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1455 pmu->setMiscReg(misc_reg, newVal); 1456 break; 1457 1458 1459 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1460 { 1461 HSTR hstrMask = 0; 1462 hstrMask.tjdbx = 1; 1463 newVal &= ~((uint32_t) hstrMask); 1464 break; 1465 } 1466 case MISCREG_HCPTR: 1467 { 1468 // If a CP bit in NSACR is 0 then the corresponding bit in 1469 // HCPTR is RAO/WI. Same applies to NSASEDIS 1470 secure_lookup = haveSecurity && 1471 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1472 readMiscRegNoEffect(MISCREG_CPSR)); 1473 if (!secure_lookup) { 1474 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1475 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1476 newVal = (newVal & ~mask) | (oldValue & mask); 1477 } 1478 break; 1479 } 1480 case MISCREG_HDFAR: // alias for secure DFAR 1481 misc_reg = MISCREG_DFAR_S; 1482 break; 1483 case MISCREG_HIFAR: // alias for secure IFAR 1484 misc_reg = MISCREG_IFAR_S; 1485 break; 1486 case MISCREG_ATS1CPR: 1487 case MISCREG_ATS1CPW: 1488 case MISCREG_ATS1CUR: 1489 case MISCREG_ATS1CUW: 1490 case MISCREG_ATS12NSOPR: 1491 case MISCREG_ATS12NSOPW: 1492 case MISCREG_ATS12NSOUR: 1493 case MISCREG_ATS12NSOUW: 1494 case MISCREG_ATS1HR: 1495 case MISCREG_ATS1HW: 1496 { 1497 Request::Flags flags = 0; 1498 BaseTLB::Mode mode = BaseTLB::Read; 1499 TLB::ArmTranslationType tranType = TLB::NormalTran; 1500 Fault fault; 1501 switch(misc_reg) { 1502 case MISCREG_ATS1CPR: 1503 flags = TLB::MustBeOne; 1504 tranType = TLB::S1CTran; 1505 mode = BaseTLB::Read; 1506 break; 1507 case MISCREG_ATS1CPW: 1508 flags = TLB::MustBeOne; 1509 tranType = TLB::S1CTran; 1510 mode = BaseTLB::Write; 1511 break; 1512 case MISCREG_ATS1CUR: 1513 flags = TLB::MustBeOne | TLB::UserMode; 1514 tranType = TLB::S1CTran; 1515 mode = BaseTLB::Read; 1516 break; 1517 case MISCREG_ATS1CUW: 1518 flags = TLB::MustBeOne | TLB::UserMode; 1519 tranType = TLB::S1CTran; 1520 mode = BaseTLB::Write; 1521 break; 1522 case MISCREG_ATS12NSOPR: 1523 if (!haveSecurity) 1524 panic("Security Extensions required for ATS12NSOPR"); 1525 flags = TLB::MustBeOne; 1526 tranType = TLB::S1S2NsTran; 1527 mode = BaseTLB::Read; 1528 break; 1529 case MISCREG_ATS12NSOPW: 1530 if (!haveSecurity) 1531 panic("Security Extensions required for ATS12NSOPW"); 1532 flags = TLB::MustBeOne; 1533 tranType = TLB::S1S2NsTran; 1534 mode = BaseTLB::Write; 1535 break; 1536 case MISCREG_ATS12NSOUR: 1537 if (!haveSecurity) 1538 panic("Security Extensions required for ATS12NSOUR"); 1539 flags = TLB::MustBeOne | TLB::UserMode; 1540 tranType = TLB::S1S2NsTran; 1541 mode = BaseTLB::Read; 1542 break; 1543 case MISCREG_ATS12NSOUW: 1544 if (!haveSecurity) 1545 panic("Security Extensions required for ATS12NSOUW"); 1546 flags = TLB::MustBeOne | TLB::UserMode; 1547 tranType = TLB::S1S2NsTran; 1548 mode = BaseTLB::Write; 1549 break; 1550 case MISCREG_ATS1HR: // only really useful from secure mode. 1551 flags = TLB::MustBeOne; 1552 tranType = TLB::HypMode; 1553 mode = BaseTLB::Read; 1554 break; 1555 case MISCREG_ATS1HW: 1556 flags = TLB::MustBeOne; 1557 tranType = TLB::HypMode; 1558 mode = BaseTLB::Write; 1559 break; 1560 } 1561 // If we're in timing mode then doing the translation in 1562 // functional mode then we're slightly distorting performance 1563 // results obtained from simulations. The translation should be 1564 // done in the same mode the core is running in. NOTE: This 1565 // can't be an atomic translation because that causes problems 1566 // with unexpected atomic snoop requests. 1567 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1568 Request req(0, val, 0, flags, Request::funcMasterId, 1569 tc->pcState().pc(), tc->contextId()); 1570 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1571 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1572 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1573 1574 MiscReg newVal; 1575 if (fault == NoFault) { 1576 Addr paddr = req.getPaddr(); 1577 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1578 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1579 newVal = (paddr & mask(39, 12)) | 1580 (tc->getDTBPtr()->getAttr()); 1581 } else { 1582 newVal = (paddr & 0xfffff000) | 1583 (tc->getDTBPtr()->getAttr()); 1584 } 1585 DPRINTF(MiscRegs, 1586 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1587 val, newVal); 1588 } else { 1589 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1590 // Set fault bit and FSR 1591 FSR fsr = armFault->getFsr(tc); 1592 1593 newVal = ((fsr >> 9) & 1) << 11; 1594 if (newVal) { 1595 // LPAE - rearange fault status 1596 newVal |= ((fsr >> 0) & 0x3f) << 1; 1597 } else { 1598 // VMSA - rearange fault status 1599 newVal |= ((fsr >> 0) & 0xf) << 1; 1600 newVal |= ((fsr >> 10) & 0x1) << 5; 1601 newVal |= ((fsr >> 12) & 0x1) << 6; 1602 } 1603 newVal |= 0x1; // F bit 1604 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1605 newVal |= armFault->isStage2() ? 0x200 : 0; 1606 DPRINTF(MiscRegs, 1607 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1608 val, fsr, newVal); 1609 } 1610 setMiscRegNoEffect(MISCREG_PAR, newVal); 1611 return; 1612 } 1613 case MISCREG_TTBCR: 1614 { 1615 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1616 const uint32_t ones = (uint32_t)(-1); 1617 TTBCR ttbcrMask = 0; 1618 TTBCR ttbcrNew = newVal; 1619 1620 // ARM DDI 0406C.b, ARMv7-32 1621 ttbcrMask.n = ones; // T0SZ 1622 if (haveSecurity) { 1623 ttbcrMask.pd0 = ones; 1624 ttbcrMask.pd1 = ones; 1625 } 1626 ttbcrMask.epd0 = ones; 1627 ttbcrMask.irgn0 = ones; 1628 ttbcrMask.orgn0 = ones; 1629 ttbcrMask.sh0 = ones; 1630 ttbcrMask.ps = ones; // T1SZ 1631 ttbcrMask.a1 = ones; 1632 ttbcrMask.epd1 = ones; 1633 ttbcrMask.irgn1 = ones; 1634 ttbcrMask.orgn1 = ones; 1635 ttbcrMask.sh1 = ones; 1636 if (haveLPAE) 1637 ttbcrMask.eae = ones; 1638 1639 if (haveLPAE && ttbcrNew.eae) { 1640 newVal = newVal & ttbcrMask; 1641 } else { 1642 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1643 } 1644 } 1645 case MISCREG_TTBR0: 1646 case MISCREG_TTBR1: 1647 { 1648 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1649 if (haveLPAE) { 1650 if (ttbcr.eae) { 1651 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1652 // ARMv8 AArch32 bit 63-56 only 1653 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1654 newVal = (newVal & (~ttbrMask)); 1655 } 1656 } 1657 } 1658 case MISCREG_SCTLR_EL1: 1659 { 1660 tc->getITBPtr()->invalidateMiscReg(); 1661 tc->getDTBPtr()->invalidateMiscReg(); 1662 setMiscRegNoEffect(misc_reg, newVal); 1663 } 1664 case MISCREG_CONTEXTIDR: 1665 case MISCREG_PRRR: 1666 case MISCREG_NMRR: 1667 case MISCREG_MAIR0: 1668 case MISCREG_MAIR1: 1669 case MISCREG_DACR: 1670 case MISCREG_VTTBR: 1671 case MISCREG_SCR_EL3: 1672 case MISCREG_HCR_EL2: 1673 case MISCREG_TCR_EL1: 1674 case MISCREG_TCR_EL2: 1675 case MISCREG_TCR_EL3: 1676 case MISCREG_SCTLR_EL2: 1677 case MISCREG_SCTLR_EL3: 1678 case MISCREG_HSCTLR: 1679 case MISCREG_TTBR0_EL1: 1680 case MISCREG_TTBR1_EL1: 1681 case MISCREG_TTBR0_EL2: 1682 case MISCREG_TTBR0_EL3: 1683 tc->getITBPtr()->invalidateMiscReg(); 1684 tc->getDTBPtr()->invalidateMiscReg(); 1685 break; 1686 case MISCREG_NZCV: 1687 { 1688 CPSR cpsr = val; 1689 1690 tc->setCCReg(CCREG_NZ, cpsr.nz); 1691 tc->setCCReg(CCREG_C, cpsr.c); 1692 tc->setCCReg(CCREG_V, cpsr.v); 1693 } 1694 break; 1695 case MISCREG_DAIF: 1696 { 1697 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1698 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1699 newVal = cpsr; 1700 misc_reg = MISCREG_CPSR; 1701 } 1702 break; 1703 case MISCREG_SP_EL0: 1704 tc->setIntReg(INTREG_SP0, newVal); 1705 break; 1706 case MISCREG_SP_EL1: 1707 tc->setIntReg(INTREG_SP1, newVal); 1708 break; 1709 case MISCREG_SP_EL2: 1710 tc->setIntReg(INTREG_SP2, newVal); 1711 break; 1712 case MISCREG_SPSEL: 1713 { 1714 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1715 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1716 newVal = cpsr; 1717 misc_reg = MISCREG_CPSR; 1718 } 1719 break; 1720 case MISCREG_CURRENTEL: 1721 { 1722 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1723 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1724 newVal = cpsr; 1725 misc_reg = MISCREG_CPSR; 1726 } 1727 break; 1728 case MISCREG_AT_S1E1R_Xt: 1729 case MISCREG_AT_S1E1W_Xt: 1730 case MISCREG_AT_S1E0R_Xt: 1731 case MISCREG_AT_S1E0W_Xt: 1732 case MISCREG_AT_S1E2R_Xt: 1733 case MISCREG_AT_S1E2W_Xt: 1734 case MISCREG_AT_S12E1R_Xt: 1735 case MISCREG_AT_S12E1W_Xt: 1736 case MISCREG_AT_S12E0R_Xt: 1737 case MISCREG_AT_S12E0W_Xt: 1738 case MISCREG_AT_S1E3R_Xt: 1739 case MISCREG_AT_S1E3W_Xt: 1740 { 1741 RequestPtr req = new Request; 1742 Request::Flags flags = 0; 1743 BaseTLB::Mode mode = BaseTLB::Read; 1744 TLB::ArmTranslationType tranType = TLB::NormalTran; 1745 Fault fault; 1746 switch(misc_reg) { 1747 case MISCREG_AT_S1E1R_Xt: 1748 flags = TLB::MustBeOne; 1749 tranType = TLB::S1E1Tran; 1750 mode = BaseTLB::Read; 1751 break; 1752 case MISCREG_AT_S1E1W_Xt: 1753 flags = TLB::MustBeOne; 1754 tranType = TLB::S1E1Tran; 1755 mode = BaseTLB::Write; 1756 break; 1757 case MISCREG_AT_S1E0R_Xt: 1758 flags = TLB::MustBeOne | TLB::UserMode; 1759 tranType = TLB::S1E0Tran; 1760 mode = BaseTLB::Read; 1761 break; 1762 case MISCREG_AT_S1E0W_Xt: 1763 flags = TLB::MustBeOne | TLB::UserMode; 1764 tranType = TLB::S1E0Tran; 1765 mode = BaseTLB::Write; 1766 break; 1767 case MISCREG_AT_S1E2R_Xt: 1768 flags = TLB::MustBeOne; 1769 tranType = TLB::S1E2Tran; 1770 mode = BaseTLB::Read; 1771 break; 1772 case MISCREG_AT_S1E2W_Xt: 1773 flags = TLB::MustBeOne; 1774 tranType = TLB::S1E2Tran; 1775 mode = BaseTLB::Write; 1776 break; 1777 case MISCREG_AT_S12E0R_Xt: 1778 flags = TLB::MustBeOne | TLB::UserMode; 1779 tranType = TLB::S12E0Tran; 1780 mode = BaseTLB::Read; 1781 break; 1782 case MISCREG_AT_S12E0W_Xt: 1783 flags = TLB::MustBeOne | TLB::UserMode; 1784 tranType = TLB::S12E0Tran; 1785 mode = BaseTLB::Write; 1786 break; 1787 case MISCREG_AT_S12E1R_Xt: 1788 flags = TLB::MustBeOne; 1789 tranType = TLB::S12E1Tran; 1790 mode = BaseTLB::Read; 1791 break; 1792 case MISCREG_AT_S12E1W_Xt: 1793 flags = TLB::MustBeOne; 1794 tranType = TLB::S12E1Tran; 1795 mode = BaseTLB::Write; 1796 break; 1797 case MISCREG_AT_S1E3R_Xt: 1798 flags = TLB::MustBeOne; 1799 tranType = TLB::S1E3Tran; 1800 mode = BaseTLB::Read; 1801 break; 1802 case MISCREG_AT_S1E3W_Xt: 1803 flags = TLB::MustBeOne; 1804 tranType = TLB::S1E3Tran; 1805 mode = BaseTLB::Write; 1806 break; 1807 } 1808 // If we're in timing mode then doing the translation in 1809 // functional mode then we're slightly distorting performance 1810 // results obtained from simulations. The translation should be 1811 // done in the same mode the core is running in. NOTE: This 1812 // can't be an atomic translation because that causes problems 1813 // with unexpected atomic snoop requests. 1814 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1815 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1816 tc->pcState().pc()); 1817 req->setContext(tc->contextId()); 1818 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1819 tranType); 1820 1821 MiscReg newVal; 1822 if (fault == NoFault) { 1823 Addr paddr = req->getPaddr(); 1824 uint64_t attr = tc->getDTBPtr()->getAttr(); 1825 uint64_t attr1 = attr >> 56; 1826 if (!attr1 || attr1 ==0x44) { 1827 attr |= 0x100; 1828 attr &= ~ uint64_t(0x80); 1829 } 1830 newVal = (paddr & mask(47, 12)) | attr; 1831 DPRINTF(MiscRegs, 1832 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1833 val, newVal); 1834 } else { 1835 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1836 // Set fault bit and FSR 1837 FSR fsr = armFault->getFsr(tc); 1838 1839 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1840 if (cpsr.width) { // AArch32 1841 newVal = ((fsr >> 9) & 1) << 11; 1842 // rearrange fault status 1843 newVal |= ((fsr >> 0) & 0x3f) << 1; 1844 newVal |= 0x1; // F bit 1845 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1846 newVal |= armFault->isStage2() ? 0x200 : 0; 1847 } else { // AArch64 1848 newVal = 1; // F bit 1849 newVal |= fsr << 1; // FST 1850 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 1851 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 1852 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 1853 newVal |= 1 << 11; // RES1 1854 } 1855 DPRINTF(MiscRegs, 1856 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1857 val, fsr, newVal); 1858 } 1859 delete req; 1860 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1861 return; 1862 } 1863 case MISCREG_SPSR_EL3: 1864 case MISCREG_SPSR_EL2: 1865 case MISCREG_SPSR_EL1: 1866 // Force bits 23:21 to 0 1867 newVal = val & ~(0x7 << 21); 1868 break; 1869 case MISCREG_L2CTLR: 1870 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1871 miscRegName[misc_reg], uint32_t(val)); 1872 break; 1873 1874 // Generic Timer registers 1875 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1876 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1877 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1878 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1879 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1880 break; 1881 } 1882 } 1883 setMiscRegNoEffect(misc_reg, newVal); 1884} 1885 1886void 1887ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1888 bool secure_lookup, uint8_t target_el) 1889{ 1890 if (!haveLargeAsid64) 1891 asid &= mask(8); 1892 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1893 System *sys = tc->getSystemPtr(); 1894 for (int x = 0; x < sys->numContexts(); x++) { 1895 ThreadContext *oc = sys->getThreadContext(x); 1896 assert(oc->getITBPtr() && oc->getDTBPtr()); 1897 oc->getITBPtr()->flushMvaAsid(va, asid, 1898 secure_lookup, target_el); 1899 oc->getDTBPtr()->flushMvaAsid(va, asid, 1900 secure_lookup, target_el); 1901 1902 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1903 if (checker) { 1904 checker->getITBPtr()->flushMvaAsid( 1905 va, asid, secure_lookup, target_el); 1906 checker->getDTBPtr()->flushMvaAsid( 1907 va, asid, secure_lookup, target_el); 1908 } 1909 } 1910} 1911 1912void 1913ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1914{ 1915 System *sys = tc->getSystemPtr(); 1916 for (int x = 0; x < sys->numContexts(); x++) { 1917 ThreadContext *oc = sys->getThreadContext(x); 1918 assert(oc->getITBPtr() && oc->getDTBPtr()); 1919 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1920 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1921 1922 // If CheckerCPU is connected, need to notify it of a flush 1923 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1924 if (checker) { 1925 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1926 target_el); 1927 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1928 target_el); 1929 } 1930 } 1931} 1932 1933void 1934ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1935{ 1936 System *sys = tc->getSystemPtr(); 1937 for (int x = 0; x < sys->numContexts(); x++) { 1938 ThreadContext *oc = sys->getThreadContext(x); 1939 assert(oc->getITBPtr() && oc->getDTBPtr()); 1940 oc->getITBPtr()->flushAllNs(hyp, target_el); 1941 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1942 1943 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1944 if (checker) { 1945 checker->getITBPtr()->flushAllNs(hyp, target_el); 1946 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1947 } 1948 } 1949} 1950 1951void 1952ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1953 uint8_t target_el) 1954{ 1955 System *sys = tc->getSystemPtr(); 1956 for (int x = 0; x < sys->numContexts(); x++) { 1957 ThreadContext *oc = sys->getThreadContext(x); 1958 assert(oc->getITBPtr() && oc->getDTBPtr()); 1959 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1960 secure_lookup, hyp, target_el); 1961 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1962 secure_lookup, hyp, target_el); 1963 1964 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1965 if (checker) { 1966 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1967 secure_lookup, hyp, target_el); 1968 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1969 secure_lookup, hyp, target_el); 1970 } 1971 } 1972} 1973 1974BaseISADevice & 1975ISA::getGenericTimer(ThreadContext *tc) 1976{ 1977 // We only need to create an ISA interface the first time we try 1978 // to access the timer. 1979 if (timer) 1980 return *timer.get(); 1981 1982 assert(system); 1983 GenericTimer *generic_timer(system->getGenericTimer()); 1984 if (!generic_timer) { 1985 panic("Trying to get a generic timer from a system that hasn't " 1986 "been configured to use a generic timer.\n"); 1987 } 1988 1989 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1990 return *timer.get(); 1991} 1992 1993} 1994 1995ArmISA::ISA * 1996ArmISAParams::create() 1997{ 1998 return new ArmISA::ISA(this); 1999} 2000